Visualisation and Resolution of Coding Conflicts in

Asynchronous Circuit Design

A. Madalinski, V. Khomenko, A. Bystrov and A. YakovlevUniversity of Newcastle upon Tyne

2

Outline

Motivation Background

Signal Transition Graph and its unfolding State encoding problem

Detection of coding conflicts Visualisation and Resolution of conflicts Case study Conclusions and future work

3

Motivation

International Technology Roadmap for Semiconductors (ITRS) system complexity communication over

computation communications-centric design

distributed implementation over centralised implementation

time domain 1

time domain 2

asynchronous interface(glue-logic)

4

Motivation

Design Flow

Reachability analysis

State encoding

Boolean minimization

Logic decomposition

Technology mapping

Specification

Signal Transition Graph

State Graph

Complete State Encoding

Next-state functions

Decomposed functions

Gate netlist

Complete State Encoding

Next-state functions

Decomposed functions

Gate netlist

Specification

Signal Transition Graph

dtack-dsr+ lds+

d-lds- ldtack- ldtack+

d+dtack+dsr-

State Graphdtack- dsr+

dtack- dsr+

dtack- dsr+

01000

ldtack- ldtack- ldtack-

0000010000

lds- lds- lds-

01010 00010 10010

lds+

ldtack+

d+

dtack+dsr-d-

01110 0011010110

01111 11111 10111

10110

10100 Complete State Encoding

dtack- dsr+

dtack- dsr+

dtack- dsr+

010000

ldtack- ldtack- ldtack-

000000 100000

lds- lds- lds-

010100 000100 100100

lds+

ldtack+

d+

dtack+dsr-

d-

011100 001100 101100

011111 111111 101111

101101

101001

011110

csc+

csc-

100001

Next-state functions)(csccsc

csc

csc

LDTACKDSr

LDTACKD

DDTACK

DLDS

Decomposed functions

Gate netlist

DTACKD

DSr

LDS

LDTACK

csc

map

Resolution ofcoding conflicts

5

Motivation

state coding is a necessary for implementability manual vs. automatic resolution of coding

conflicts automatic can produce sub-optimal solutions manual crucial for finding good (low-latency,

compact & elegant) synthesis solutions interactivity is good!

visualisation concept: emphasise on essential & compact elements

6

Signal Transition Graph (STG)

Dev

ice

VME BusController

ldsldtack

d

Data TransceiverBus

dsrdsw

dtack

dsr

lds

ldtack

d

dtack

dtack- dsr+ lds+

d-lds- ldtack- ldtack+

d+dtack+dsr-

7

dtack- dsr+ lds+

d-lds- ldtack- ldtack+

d+dtack+dsr-

Signal Transition Graph (STG)

Dev

ice

VME BusController

ldsldtack

d

Data TransceiverBus

dsrdsw

dtack

Read cycle

8

Implementation problem: State Enoding

pairs of semantically different states with the same binary encoding

not distinguishable at the circuit level necessary condition for deriving the logic

implementation: Complete State Coding (CSC):

2 states may have the same code iff the set of non-input signals is the same

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dtack- dsr+

dtack- dsr+

dtack- dsr+

01000

ldtack- ldtack- ldtack-

0000010000

lds- lds- lds-

01010 00010 10010

lds+

ldtack+

d+

dtack+dsr-d-

01110 00110 10110

01111 11111 10111

10110

10100

M’’ M’

dtack- dsr+

dtack- dsr+

dtack- dsr+

01000

ldtack- ldtack- ldtack-

0000010000

lds- lds- lds-

01010 00010 10010

lds+

ldtack+

d+

dtack+dsr-d-

01110 00110 10110

01111 11111 10111

10110

10100

Example: CSC conflict

10

M’’ M’

Example: enforcing CSCdtack- dsr+

dtack- dsr+

dtack- dsr+

010000

ldtack- ldtack- ldtack-

000000 100000

lds- lds- lds-

010100 000100 100100

lds+

ldtack+

d+

dtack+dsr-

d-

011100 001100 101100

011111 111111 101111

101101

101001

011110

csc+

csc-

100001

11

STG unfolding

partial order model acyclic net, infinite, simple structure finite complete prefix

finite initial part of unfolding alleviate state space explosion problem contains all reachable states more visual then state graphs proven efficient for model checking

12

State Graphs vs. Unfoldings

lds-

e1

e2

e3

e4

e5

e6

e7

e9

e11

e12

e10

e8

dsr+

ldtack+

dsr-

ldtack-

lds+

d+

dtack+

d-dtack-

dsr+lds+

M’M’’

M’

M’’

dtack- dsr+

dtack- dsr+

dtack- dsr+

01000

ldtack- ldtack- ldtack-

0000010000

lds- lds- lds-

01010 00010 10010

lds+

ldtack+

d+

dtack+dsr-d-

01110 00110 10110

01111 11111 10111

10110

10100

initial statetransitions

13

Visualisation of coding conflicts

representation of conflicts as pairs of configurations is not efficient already a small number of

conflicts is difficult to depict

Propagation effect

888 CSC conflicts!

14

Visualisation of coding conflicts

visualising only the essential parts involved in conflicts compact representation avoids explicit representation based on complementary sets

{b0+,b1+,b0-,b1-}

15

Coding conflict detection in a prefix

integer programming technique

V. Khomenko, M. Koutny and A. Yakovlev: Detecting State Coding Conflicts in STGs Using Integer Programming. Proc of DATE’02, IEEE Comp. Soc. Press (2002) 338-345.

CSC conflict representation as unordered conflict pair of configurations

21 ,CC

C1C2

16

Classification of conflicts type I:

C1C2

type II:C1\C2 ≠ ≠ C2\C1,

and there exist e1C1\C2

and e2C2\C1 such that e1# e2

Conflicts of type I and II

C1

C2

C1 C2

e1 e2

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Cores

complementary set CS=C1C2

C1,C2 is a conflict pair is the symmetric set difference CS is of type I/II if C1,C2 is of type I/II

CS is a core if it cannot be represented as union of several disjoint complementary sets

18

Resolution of coding conflicts

Core

t+

t- introduction of additional

internal signals destroying cores insert t+ in a core t- must be added outside

the core preserving signal consistency

inserted transitions cannot trigger an input signal

19

Visualisation of conflicts: Height map

Core1

Core3

Core2

cores often overlap high-density areas are good candidates

for signal insertion analogy with physical map in geography

A1A2A3

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Height map: an example

Core map Height map

csc1+

21

Given an STG with conflicts

Overview of resolving process

Construction of STG’s prefix & computation of cores

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Overview of resolving process

Conflicts exists?

No -> process terminated

Yes -> Phase 1 & 2Location is determinate where t+ & t- is inserted

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Overview of resolving process

Transferring inserted signal to STG

Process can consists of several cycles, depending on the number of cores

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Phase 1

Case study: part of async. AD converter controller

csc1+

Phase 1

Core mapHeight map

25

csc1+

Phase 2Phase 2

csc1-

Height map Core map

csc1+

Case study: part of async. AD converter controller

26

Case study: Handshake decoupling element

Core map Part of the solving process

csc1+

csc1-

Phase 1 Phase 2

csc1+

27

Case study: Handshake decoupling element

initial STG STG derived by our method

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Conclusions

approach for visualisation and resolution of state coding conflict was designed

main ingredients of the approach compact representation of concurrent

behaviour compact representation of conflicts compact representation of constrains for

resolutionunfolding prefix+ cores+ height map

29

Future work

improving our tool ConfRes using concurrency reduction in addition to

signal insertion for resolving conflicts using timing assumptions full design cycle based on STG unfoldings,

not involving state graphs at any stage

ACSD 2003