vitesse mobile backhaul solution presentation (3)

Vitesse Mobile Access Solution Overview

February 2012

IP Edge is the main Investment Focus

Carrier migration from 3G to 4G/LTE Advanced (LTE-A) Base stations, cell site routers,

small cells Pre-aggregation routers and switches

Business Services and Cloud Ethernet Access Devices Network Interface Devices

Market Challenge Intelligence to handle Carrier-class

services at the Edge Power constraints QoS to handle variable bandwidth

Microwave Backhaul OAM and QoS to guarantee Business

Cloud Services

Small Cell Equipment & Access Routers

2

Timing Synchronization Is A Critical Requirement And…It’s Getting Harder

Network migration to 4G/LTE Base stations, small cells, cell routers Pre-aggregation routers, switches

Market challenge Delivering < 10ns synchronization

required for 4G/LTE-A networks

3G

4G/LTE

LTE-A

Timing Accuracy Requirements for 3G/4G

2008 2010 2012 2014

Timing Is Required At Multiple Network Points

3

What Problems we are Solving

High-bandwidth Mobile Audio/Video Content (LTE and LTE-A) require nanosecond-accurate timing VTSS timing solutions deliver

Small Cell MW Backhaul is essential to deploy LTE in urban environments Only VTSS can solve timing over MW

With LTE Microwave and Small Cell Backhaul turned from an RF problem into a complex networking problem We are the only ones supporting requirements at low enough power

4

Two Winning Solutions for the IP Edge

PHYs

Switch

CPU

1588 NPU,

ASIC or FPGA

PHYs

PHYs

Legacy Multichip Solution

Integrated Switch Engines

50% Lower Power

Standalone 1588 PHYs

NPU or FPGA

PHYs 1588

OAM Switc

hing

50% Lower Cost

PHYs 1588

OAM

5

Where We Fit In The Mobile Access Network

PHYs

Switch Engines

OTN/FEC Optimized for Timing, Synchronization & OAM

1. Low Power, highly integrated Edge Switches where there is no competing solution 2. 1588/OAM PHYs that actually solve all Mobile Access Timing and OAM problems

6

256-

1024

CE Switch Engine Applications for the IP Edge

Pico Micro Cells

Caracal-1

Serval-1

Serval-2

64-1

28

2k-4

k

Jaguar-3 Jaguar-2

Microwave ODU Microwave/Fiber IDU/Router

Micro Macro Cell

Ethernet Cloud Services NID

User

s/Ser

vices

C1

S1

S2

J2 J3

7

Vitesse Fit in Mobile Access

Pico/Micro Cell Macro Cell

J1,2,3 C1/S1

GE 1/10GE

PHY

PHY

J2,3

Cell Site Router or MW IDU

1/10GE Transport over Fiber

Small Cell BH or MW ODU

C1 S1,2

GE Transport over Microwave

Cells

Backhaul

NPU/ ASIC

MODEM

BB & GPP BB BB BB

GPP

BB

GPP

MW IDU/ODU Connection

8

Winning Innovations for Mobile Backhaul

• SyncE Ring Resiliency for 1000Base-T • ns-accurate 1588v2, Y.1731, and MPLS-OAM • 1588v2 Timing over Adaptive Microwave Links • Transparent Clocks in PTP-unaware systems

Solving LTE/LTE-A Timing Challenges

• MPLS LER and LSR support in small switches • Extremely low Power (<2W) • Full H-QoS in small switches • Dynamic QoS for Adaptive MW Modulation

Advanced Networking for Small

Cell Backhaul

9

Industry’s Only 1588 Synchronization Technology Meeting LTE-A Timing Requirements

Patented synchronization technology Broadest portfolio of 1588 solutions GbE Access, Edge 10GbE Edge, Metro 10GbE OTN Metro, Core

Design wins at major Tier 1 OEMs

PHYs PHYs

PHYs

Integration Expands Functionality

PHYs 1588 Security

Clas

sifica

tion

10

http://www.rad.com/

http://www.motorola.com/Consumers/US-EN/Home

Serval™ Switch Engine Highest feature set at lowest power

NPU packet processing at half the cost and power < 2W vs. competition’s 10W

Solves small cell access equipment constraints On-board intelligence Compact footprint LTE Timing & synchronization Embedded TCAM & Packet

Buffering to lower cost

Price

, Pow

er &

Foo

tprin

t NPU

FPGA

Integrated Switch Engines

Industry’s best Carrier Access networking solution for small cell, mobile backhaul and network IP Edge applications

PHYs

1588

OAM Switc

hing

11

Serval – Our Newest IP Edge Switch Engine

Jaguar Reference Design

Available at www.Vitesse.com * Specific release dates for specific features are available upon request

Caracal Reference Design

CUSTOMER COLLATERAL

JAGUAR LYNX

CARACAL-1 CARACAL-2

SERVAL

Datasheets Device Samples

Initial Production Released

Q2 2012

Software* Q1 2012 Reference Designs

Q1 2012

Serval Reference Design

12

http://www.vitesse.com/

Vitesse Mobile Access Solution Value Proposition

February 2012

Executive Summary of Vitesse Solutions

Three Solutions that fit different needs 1. GE switch with integrated Cu PHY - VSC7428 and VSC7429 (Caracal) 2. GE switch and external PHY - VSC8574(Tesla) + VSC7418 (Serval-1) 3. GE/10GE switch - VSC8574 (Tesla) + VSC8488-15 (10G PHY) + VSC746X (Lynx-1

/Jaguar-1) – (roadmap – Serval-2/Lynx-2/Jaguar-2) Value Propositions: Innovative Features

– SyncE Ring Resiliency support over 1000-Base-T links – High accuracy IEEE1588v2 Transparent Clock support over Microwave link and over PTP unaware

system – Advanced CE features such as OAM, Performance measurements and ring/linear protection – Priority Queuing, shaping and Flow control

Low power and low cost Mature HW and SW solution

– Caracal, Tesla, Lynx-1 and Jaguar-1 available today – can demonstrate ring resiliency, 1588v2 TC support

– Participated in EANTC tests to demo 1588v2 TC, Y1731 and G.8032 interop Strong roadmap

14

Vitesse Delivers on All Key Mobile Access Requirements Caracal, Lynx/Jaguar-1

shipping to customers today Half the power of competing

solutions Excellent fit for Network Access

requirements

Vitesse Product development aligned with future requirements Next generation Caracal Serval Adding MPLS, MPLS-TP, 1588 Transparent Clock over Microwave and H-QoS Even lower power

BW & Features

VSC7428 Caracal-1™ 9x1G+1 1G/2.5G w/8 CuPHY

VSC7429 Caracal-2™ 25x1G+1G/2.5G w/12 CuPHY

VSC7462 LynX-1™ 12x1G+2x10G

VSC7460 Jaguar-1™ 24x1G+4x10G

TYPICAL COMPETITION Caracal (8x1G Cu/Fiber + 2x2.5G) 4.5W 9W (Winpath+External PHY) Jaguar-1 (24x1G+4x10G) 5W 13W (BCM56334) Serval (8x1G Fiber + 2x2.5G) <2W ----

VSC7418 Serval-1™ 10-Port CE Switch

15

Caracal based Solution Highest integration and Lowest power CE Access Switch

KEY NEW FEATURES CARACAL DELIVERS

Reduced BOM cost – integrated Cu PHY and integrated processor Up to 8xCu, 9xSGMII ports

Linear and Ring protection G8031/2

Class of Service mapping based on 802.1p, ToS/DSCP for QoS prioritization

Rate Limiting using Committed Information Rate (CIR) and Committed Burst Size (CBS) per UNI, EVC and CoS

1588v2 single step and two step with both internal and external CPU

HW based IEEE 802.3ah and IEEE 802.1ag OAM

HW based Y1731 delay and loss measurements

CCM frame generation in hardware (including 3.3ms – tested in EANTC)

Extended Temperature Range

Radio

1000-Base-T

SGMII SGMII

16

Baseband Processing & DFE

VSC7428 Caracal™ CE Switch

Serval Adds more capabilities

SGMII

VSC7418 VSC8662 : SyncE VSC8552: SyncE + ring resliency VSC8572 : SyncE + ring resliency + 1588v2

1000-Base-T SGMII

VSC7418 Value Propositions: Low power – 2W + PHY Adds L3 classification Transparent Clock support over Microwave link Adds Ring Resiliency over 1000-Base-T (Cu) links MPLS, MPLS-TP H-QoS More OAM – UP and DOWN MEP Y1564 – SAM

17

CE Switch

Dual Cu PHY

Example Requirements Vitesse Products

Customer Requirements Caracal-1 Serval-1

Port Configurations -combination of Cu and Fiber 8x1G Cu or 8x1G SGMII+ 2x 1/2.5G

9x 1G + 2x 1/2.5G SGMII

HW based EOAM, ECFM

HW based Y1731

1588 – Transparent clock TC support for MW

1588 – Boundary clock

Queues Per port 8Qs/port H-QoS, More than 2K Qs

Two level Metering Per port and per Queue

Per port, per COS or Service

Scheduling – priority queuing and WFQ 2 SP+6 DWRR All Strict Priority (SP) All Weighted (DWRR)

Any mix of strict/weighted

MEF E-Tree, E-LAN compliance 256 services, E-LINE, E-LAN, E-TREE over Q-Q

1K services, E-LINE, E-LAN, E-TREE

over Q-Q or MPLS

MPLS-TP PWE, VPLS, LSR

- H-VPLS

Linear and Ring Prot.

18

All-outdoor Microwave ODU Backhaul Solution

1 or 2G SGMII

Interface to (fiber) network or other ODUs (e.g., in ring/mesh)

SGMII PCIe

Custom stuff (Control Plane, custom FPGA)

Some customers are going to use programmable multi-core (Digital Signal) Processing ICs here instead of FPGAs or custom (BRCM/Provigent) solutions)

Ext. PHY required only for Serval

19

SGMII

VSC74xx Caracal™ Serval™ CE Switch

VSC8572 VSC8552 Dual Cu PHY


RF Subsystem

Serval Small Cell Solution

SGMII

SGMII

PoE CuPHY network interface (to fiber NTE or MW ODU) and powering.

SGMII PCIe

Custom stuff (e.g., Control Plane Processing)

Some customers are going to use programmable multi-core (Digital Signal) Processing ICs here

20

VSC74xx Caracal™ Serval™ CE Switch

VSC8572 VSC8552 Dual Cu PHY


LTE/WCDM A RF Subsystem

Serval-1 Value propositions for Microwave Backhaul and Small Cells Solving LTE/LTE-A Timing Challenges SyncE Ring Resiliency <10ns accuracy for 1588v2, Y.1731, and MPLS-OAM Transparent Clocks over Microwave Links Transparent Clocks in PTP-unaware systems

Advanced Protocols required for LTE – MPLS (-TP) LER and LSR support in small switches

Advanced QoS Hierarchical QoS in small switches Dynamic QoS to match Microwave link rate adaptation

Comprehensive OAM including Up/Down-MEPs Low power – less than 2W

Increased Networking Requirements require Advanced Switching Solutions that cannot be met by competing products

21

Managing Dynamic Link BW using Serval-1 [Three CoS shown for simplicity; Serval-1 supports 8 CoS]

Port Shaper Always set to Link BW, let QoS Scheduler determine how to best use this BW. Reduces queuing in Modem. Adjust dynamically from Modem using standard CSR register read/write or in-band VRAP commands (quicker, all-hardware)

QoS Scheduler High Priority always gets sent over Link with lowest latency (< 3 uS for small high-priority frames) Service Medium strictly over Low Priority, or give Medium and Low Priorities each a % of the remaining Link BW (to not starve Low

Priority) Queue System Resource Manager

When Link BW is reduced, Queue System fills up Two choices to manage congestion: Prioritized Discard, or Per-Priority Flow Control

Prioritized Discard Drop Low Priority frames first, then Medium, as Queue System fills Buffers always available for High Priority

Per-Priority Flow Control (standard 802.1Qbb) Issue Pause frame to customer equipment to throttle Low Priority, then Medium Priority, as Queue System fills Pushes discard decision back to customer equipment (if 802.1Qbb supported)

Buffering capacity Example calculation: (8 Mbits) / (200 Mbps oversubscription) = 40 mS [adjusts linearly based on oversubscription amount]

COS HIGH

CustomerEquipment

Priority may be marked

QoSClassification

QueueSystem

ResourceManager

COS MED

COS LOW

QoSScheduler

Always send High Priority. Send Med and Low Priorities as Link BW allows.

ShaperModem

To RF

Modem dynamically adjusts rate to match Link BW using VRAP

Prioritized Discard or Per-Priority Flow Control as Queue System fills due to slow Link

802.1Qbb Per-Priority Flow Control to Customer Equipment (if supported)

Serval-1

22

IEEE-1588v2 Switch and PHY Solutions Only portfolio that can meet LTE network accuracy needs

* HW-accurate with external PHYs

DEVICES TIMESTAMPING ONE-STEP

TIMESTAMPING TWO-STEP

GE Switch - Caracal (VSC7428 and VSC7429) HW HW GE/10GE Switch - Jaguar-1 (VSC7460 and VSC7462) SW* HW GE Switch - Serval (VSC7418) HW HW GE/10GE Switch - Jaguar-2 (VSC7468) HW HW 1G PHY – Cu and Fiber (VSC8574 and VSC8572) HW HW 10G PHY – LAN/WAN(VSC8488-15 and VSC8484-15) HW HW 10G PHY – LAN/WAN/OTN (VSC8492 and VSC8494) HW HW

All IEEE-1588v2 clock types: Ordinary Clock (master or slave) Peer-to-Peer Transparent Clock End-to-End Transparent Clock Boundary Clock

1588 TOD output, with 1PPS and ref clock inputs/outputs Switches with MIPS processor for running PTP protocol and filtering SW

23

FEATURE/PARAMETERS VITESSE COMPETITOR B Long term phase accurate Yes No Compensates delay Asymmetry Yes No 1588 over MPLS Yes No Accurate Transparent clock Yes No Meet low frequency wander needs – Separate SyncE and 1588 clock Yes No

Y1731 and MPLS OAM timestamp Yes No

Ring resiliency for SyncE Yes No

Vitesse 1588 Differentiators

Competitor B solution can not be deployed in LTE network, since It can not meet the required phase accuracy of 1.5us It can not take care of delay asymmetry It does not support 1588 over MPLS It does not provide an accurate transparent clock It does not meet low frequency wander requirements

24

Test Results for OC-M – 10xTC – OC-S

PTP Master (OC-M) TC PTP Slave

(OC-S) x10

Ethernet Ethernet

VSC7428 VSC7428 VSC7428

1588 TS clock (OCXO): 250 MHz VTSS slave filter algorithm

Clk.ref.: OCXO Sync/Pdelay_req: 1/8 fps

E2E

No Traffic load

20ksec meas. time

Slave wander is below G.823 PRC corresponding to < 80nsec over 5.6 hours

Better than LTE-A requirements

25

Meeting LTE Timing Specs with IEEE-1588 Application Example

LTE requires Upstream/Downstream Symmetry and Nanosecond-precision Timestamping MPLS co-routing eliminates network-level uncertainty

Slave Delay Range calculation of ½ RT delay is invalid if different Up/Down paths Transparent Clock eliminates box-level uncertainty

Eliminates Packet Delay Variation, improving Frequency recovery of Slave servo Eliminates Up/Down asymmetry from Slave Delay Range calculation, improving Phase/TOD

– In the above example, a 50 uS Phase Error would exist without TC – Slave servo algorithm cannot remove this Phase Error

Nanosecond-precision Timestamping required LTE requires < 1.5 uS phase error, per-hop equipment budget much less (10’s of nS max) Equipment PHYs must not have asymmetric Tx/Rx delays typical of Ethernet PHYs

PTP Master (OC-M)

PTP Slave (OC-S)

Sync (carries TOD)

Delay Request-Response (determines round-trip delay)

TC

Downstream Queuing Delay = 100 uS Upstream Queuing Delay = 2 uS

26

C B

A

D B-D link fail affects D’s clock

X

C B

A

D

C-D link uses ring resiliency to restore D’s timing

X

C D Master Slave

D C Master Slave

Solving 1000BT Master/Slave Issue for SyncE

The Issue 1000BASE-T operation requires master/slave timing Can only change 1000BT master/slave by first dropping the

link and then re-establishing it during the re-linkup phase Takes several seconds causing severe network downtime

The Solution Vitesse provides new Ring Resiliency solution Reconfigures 1000BASE-T master/slave with no link drop See “Ring Resiliency Appnote” for more information

1000BASE-T Ring Resiliency is supported in the new VSC8574 and VSC8572 PHY devices

27

Vitesse Software Highlights

Capabilities A decade of providing production worthy APIs (3rd generation) Approx 100 different managed solutions provided Turnkey L2 fully managed protocol stack Carrier Ethernet protocol support (1588, SyncE, OAM)

Worldwide SW Support Dedicated application support and software teams located in US, Denmark, India,

Taiwan and China Software Development Cross-site team with one well structured process (Denmark, India, Taiwan) Dedicated SQA team

Mature Software Shipping to both Enterprise and Carrier customers Successfully participated in multiple multi-vendor interoperability tests

Vitesse Software is mature, supported by strong team and development process

28

Vitesse Software Solutions

3 types of components Unified API - Covers all Vitesse

Ethernet devices (Switches, MAC’s, PHY’s, OTN)

Board Support Package – Operating System Specific configuration

Applications – high level control plane protocols to enable management of traffic within the system

3 types of solutions Horizontal Components- APIs and

shims Vertical Components- Protocols and

specific features Turnkey - Complete bundled solution

Model depends on product & customer

Hardware Software

I/O Layer

Application Interface Layer

Caracal Jaguar VSC8484 VSC8574 Chip Interface Layer

Application Programming Interface (API)

Layer

Initialization Port Control

Packet Control Security

Layer 2 Quality of Service

Layer 3 Management

Caracal VSC7428

1G PHY

Vitesse Devices

10G PHY

Jaguar VSC7460

1G PHY 10G PHY

Serval-1 VSC7418

1G PHY 10G PHY

Graphical User Interface (Web)

Network Management

Interface (SNMP) Command Line Interface (CLI)

Management Layer

802.1Q Bridging

Port Protection Security Protocols QoS

PBB Bridging

VLAN Translation

Link Aggregation

MSTP

RSTP

802.1X

ACLs Stacking Protocols

SPOM

SPROUT

Topology

MPLS/MPLS-TP

IGMP

MLD

E-Line/E-LAN

1588 PTP

SyncE

OAM

GVRP

L3 Static

Application & Control

Plane Protocols (Subset Shown)

29

Brocade Juniper Calnex Solutions Metaswitch Cisco Systems Spirent Communications Ericsson Symmetricom Hitachi Telco Systems Huawei Technologies Vitesse Ixia

IEEE-1588 packet timing Ethernet Ring Protection

Switching (G.8032) Y.1731 Delay and Loss

measurements

Successfully demonstrated interoperability for the listed features

Results published in EANTC Whitepaper: http://www.eantc.de/fileadmin/eantc/downloads/events/MPLS2011/EANTC-MPLSEWC2011-WhitePaper-1_0.pdf

http://www.eantc.de/fileadmin/eantc/downloads/events/2007-2010/CEWC2010/EANTC-CEWC2010-WhitePaper-v1_0.pdf

Participating Vendors

Proven Interoperability at Multiple Plug Fests

30

http://www.eantc.de/fileadmin/eantc/downloads/events/MPLS2011/EANTC-MPLSEWC2011-WhitePaper-1_0.pdf
















Ethernet Ring Protection Test (G.8032/ERPS)

Vitesse (VSC7428, Caracal based system) was part of the successful G.8032 Ethernet Ring Protection Switching tests

We successfully performed two tests. The first consisted of Brocade MLXe Router, Ericsson OMS1410, Telco systems T-Marc 380 and Vitesse VSC7428 where A CCM interval of 3.33ms was used. - EANTC Test White Paper

31

Y.1731 Frame Loss and Delay Measurement Test

Vitesse (VSC7460, Jaguar based system) was one of the few vendors who successfully conducted both Frame loss and Frame Delay testing

During the delay and delay variation test, we noticed that the measurements performed by most vendors are so accurate that their results are within a few tens of microseconds of each other - EANTC Test White Paper

32

Vitesse Device and Software Portfolio for Mobile Access

February 2012

Expanding Portfolio For Mobile Access

Target Applications New Products Intro Yr. IDU, ODU, NID, Small Cells Serval™ Ethernet Switch Engines 2012 MW IDU, ODU Caracal-1™ Ethernet Switch Engines 2011 Cell Site Router, Pre-Aggregation

Caracal-2™ Ethernet Switch Engines 2011

Mobile Access Aggregation LynX™ Ethernet Switch Engines 2010 Mobile Access Edge/Metro Jaguar™ Ethernet Switch Engines 2010 Metro Packet Transport VSC8494 Quad 10G OTN Mapper with 1588v2 2011 1GbE interfaces w/ Packet Timing

VSC8664 Quad GbE with SyncE VSC8574 Quad GbE with 1588v2, Y.1731

2009 2011

10GbE interfaces w/ Packet Timing

VSC8486 10GbE with SyncE VSC8488-15 Quad 10GbE with 1588v2, Y.1731

2009 2011

FTTx Optical Interconnect New 1, 2, 10G PMD and PHYs 2011

Switching Transitioning to Ethernet

Connectivity 1G – 10G and Above

34

VSC8574 – Quad-port Q/SGMII SyncE/1588 PHY

Quad Gigabit Dual Media Interface 10/100/1000BASE-T copper 100/1000BX fiber + Cu SFP

MAC I/F = QSGMII / SGMII Key Notes:

IEEE-1588 time stamping – encapsulation support – Interoperable with all Vitesse IEEE-1588 timestamp products

SyncE support – Dual recovered clock outputs with selectable frequency – Clock squelching and fast link failure support

EcoEthernet v2.0 – EEE – Linkdown and cable reach power savings

Extended Temperature Support

SGMII QSGMII

10/100/1000BASE-T 100/1000BASE-X/ Cu SFP Support

VSC8574 Dual Media Q/SGMII PHY w/SyncE 1588

35

VSC8487/8-15 Single/Dual 10GE SyncE/1588 PHY

2x10GBE 10GBASE-R/W XFI/SFI 10GBASE-KR

1/2x XAUI

16x16mm VSC8488-15 (Dual) 16x16mm VSC8487-15 (Single)

Samples Now

1x10GE Linecard

VSC8487

XPT XAUI PHY

XFI/SFI PHY

XAUI PHY

XFP/SFP+

1 x XAUI (Working)

1 x XAUI (Protect)

Nx10GE Switch Card (Active)

Nx10GE Switch Card (Standby)

10GE LAN/WAN

KEY FEATURES DETAILS Retains key VSC8484 features, “-15” suffix for 1588 support

•SFP+/QSFP+ support •Full 10GBASE-KR capability - Autoneg/link training/Optional KR-FEC •Integrated protection-switching (see below) •Fully integrated VScopeTM

•10GE LAN/WAN and Sync-E support Adds 1588v2 Adds 1588v2 timestamp correction, 1731 OAM Pin Compatible VSC8488 pin- & reg-compatible

VSC8487/8-15 1/2X 10GE PHY

36

BW

Carrier Ethernet Features

10G

60G

40G

100G

Adds Integrated 10G PHY, MPLS-TP with

OAM, H-QoS and L3 routing

80G

Adds MPLS-TP, H-QoS,

L3 awareness, Y.1731 HW OAM

Both Up-MEP and

Down-MEP, Service scale

Adds IP/MPLS, Service scale

Adds Integrated 10G PHY, MPLS-TP with

OAM, and H-QoS

Increased BW IP/MPLS

Adds IP/MPLS, Service scale

Integrated 10G PHY,

2x Memory

Comprehensive CE Switch Roadmap

VSC7428 Caracal-1™ 11-Port CE Switch

VSC7429 Caracal-2™ 26-Port CE Switch

20G

VSC7460 Jaguar-1™ 24x1G+4x10G CE Switch

VSC7462 Lynx-1™ 12x1G+4x10G CE Switch

VSC7438 Serval-2™ 12x1G+2x10G

VSC7464 Lynx-2™ 12x1G+4x10G 24x1G+2x10G

VSC7468 Jaguar-2™ 24x1G+4x10G 48x1G+2x10G

VSC74XX Jaguar-3™ 48x1G+4x10G CE Switch

VSC74XX Lynx-3™ 12x1G+4x10G 24x1G+2x10G

Sampling

=Today = Development = Concept

VSC7418 Serval-1™ 10-Port CE Switch

VSC74XX Serval-3™ 12x1G+2x10G CE Switch

37

Vitesse Mobile Access Switch Product Snapshot

38

FEATURE VSC7428 CARACAL-1

VSC7429 CARACAL-2

VSC7462/VSC7460 LYNX-1/JAGUAR-1

VSC7418 SERVAL-1

VSC7438 SERVAL-2

LYNX-2 JAGUAR-2

I/O Bandwidth 13 Gbps 26 Gbps 52/68 Gbps 14 Gbps 32 Gbps 52/68 Gbps

Port Configurations 8x1G Cu + 2x 1/2.5G

12x1G Cu +12x 1G + 2x 1/2.5G

12/24x1G+4x10G XAUI, up to 8x 2.5G

9x 1G + 2x 1/2.5G

12x 1G + 2x 10G XFI/XAUI

12/24/48x 1G + 4x10G XFI/ 2XAUI

Service Endpoints E-Line, E-LAN, E-TREE

256 256 4K 1K 1K 4K

QoS 8Qs/port 8Qs/port 8Qs/port H-QoS, More than 2K

Qs

H-QoS 2K H-QoS Qs

H-QoS 8K H-QoS Qs

Q-Q

PBB/PBB-TE - - - - -

MPLS-TP PWE, VPLS, LSR

- - - H-VPLS

H-VPLS edge

H-VPLS edge

Ethernet OAM HW

Linear and Ring Prot.

SyncE, 1588v2 -

TC support for

MW

TC support for

MW

TC support for MW

Memory 4Mbit 4Mbit 4MByte 8Mbit 2MByte 4MByte I-temp Power 4.25W typ

5.1W max 6.5W typ 7.8W max

4.5W typ 12W max

<2W typ 3.5W max

3.5W typ 4.5W typ 5.5W typ

Caracal-1™ Key Features

8x GbE (Cu PHY or SGMII)

1GbE/2.5G

27x27mm HSBGA Industrial Temperature Range

1GbE/2.5G

Available Now

KEY FEATURES DETAILS 11-port GbE Switch 9-port GbE SGMII or with 8 integrated Cu PHYs

2-port 1GbE/2.5G SGMII Service Aware Classifier (TCAM)

Service Aware Classification – Support for 256 Services Flexible TCAM QoS classification E-LAN, E-Line, E-Tree

Advanced QoS and MEF Compliant Policing

Shared Buffer memory with per color watermarks guaranteeing dedicated memory areas 256 Color aware programmable DLB Policers per port and CoS Shaping per port and CoS

Robust Statistics Counters Red, Yellow, Green, byte/ frame counters per Port, CoS Transmit and drop byte/ frame counters

Integrated Timing IEEE-1588v2 - one and two step modes Synchronous Ethernet.

Ethernet OAM Performance Monitoring

Ethernet OAM frames generated and forwarded to MIPS CPU HW generation of Continuity Check messages Link monitoring and protection switching

Embedded Processor 416 MHz MIPS24KEc Processor Warm restart capability

VSC7428 Caracal-1™ CE Switch

DDR2

PI/SI

NPI

39

Caracal-2™ Key Features

27x27mm HSBGA Industrial Temperature Range

24 Port GbE

1GbE/2.5G 1GbE/2.5G

Available Now

VSC7429 Caracal-2™ CE Switch

KEY FEATURES DETAILS 26-port GbE switch with integrated Cu PHYS and 2 Port 1GbE/2.5G

12-port GbE SGMII or with integrated Cu PHYs 12-port QSGMII 2-port 1GbE/2.5G SGMII

Service Aware Classifier (TCAM)

Service Aware Classification – Support for 256 Services Flexible TCAM QoS classification E-LAN, E-Line, E-Tree

Advanced QoS and MEF Compliant Policing

Shared Buffer memory with per color watermarks guaranteeing dedicated memory areas 256 Color aware programmable DLB Policers per port and CoS Shaping per port and CoS

Robust Statistics Counters

Red, Yellow, Green, byte/ frame counters per Port, CoS Transmit and drop byte/ frame counters

Integrated Timing IEEE-1588v2 - one and two step modes Synchronous Ethernet.


Ethernet OAM frames generated and forwarded to MIPS CPU HW generation of Continuity Check messages Link monitoring and protection switching

Embedded Processor 416 MHz MIPS24KEc Processor Warm restart capability

DDR2

PI/SI

NPI

40

LynX-1™ Key Features

12 x SGMII/SerDes/100FX

2 XAUI 2 VAUI*

27x27mm FCBGA Industrial Temperature Range

Available Now

KEY FEATURES DETAILS 12 x 10/100/1000 SGMII w/SerDes, 2x10G XAUI/VAUI

10/100/1000 GbE ports support 1000 Base-X SerDes, 100 Base FX 4x 10G XAUI ports supporting standard XAUI, RXAUI + 8 x 2.4G port (12x1GbE +4x10G, 8xGbE + 8x2.5G, 12x1GbE + 4x2.5G + 10G)


Service Aware Classification – 4K services (Port, MAC, S-Tag, C-Tag, Pri, DSCP, E-Type, L3, L4 fields), QoS treatment, DE Marking, Color, Policing actions, OAM, Performance monitoring & IEEE-1588 function

Advanced QoS and MEF Compliant Policing (~5K Policers)

32Mb Shared buffer Memory, 5 level Hierarchial Policing and Shaping MEF compliant Policers (4K Service, 512 Tunnels, 32 Global, 8 Priority, 4 port level)


~50K Statistics Counter Arrival, Departure, Discard Stats – RYG (Bytes, Frames)

Integrated Timing Both IEEE-1588v2 & SyncE Ethernet OAM Performance Monitoring

Ethernet OAM – Hardware support for 4K services, 512 Paths, 32 ports IEEE 802.1ag (CFM), 802.3 (EFM), ITU-T Y.1731 (Eth-OAM), MEF-16

Embedded Processor

416 MHz MIPS24KEc Processor

VSC7462 LynX-1™ CE Switch

DDR2

PI/SI

NPI

41

Jaguar-1™ Key Features

24 x SGMII/SERDES/100FX

2x 10G XAUI 2x 10G VAUI*


Available Now

VSC7460 Jaguar-1™ CE Switch

KEY FEATURES DETAILS 24 x 10/100/1000 SGMII w/SerDes, 2 x 10G XAUI + 2 x 12G XAUI/VAUI

10/100/1000 GbE ports support 1000 Base-X SerDes,100Base-FX

4x 10G XAUI ports supporting standard XAUI, RXAUI + 8x 2.4G


Service Aware Classification – 4K services (Port, MAC, S-Tag, C-Tag, Pri, DSCP, E-Type, L3, L4 fields), QoS treatment, DE Marking, Color, Policing actions, OAM, Performance monitoring & IEEE-1588 function,

Advanced QoS and MEF Compliant Policing (~5K Policers)

32Mb Shared buffer Memory, 5 level hierarchical Policing and Shaping MEF Complaint Policers (4K Service, 512 Tunnels, 32 Global, 8 Priority, 4 port level)


~50K Statistics Counter Arrival, Departure, Discard Stats – RYG (Bytes, Frames)

Integrated Timing Both IEEE 1588v2 & SyncE


Ethernet OAM – Hardware support for 4K services, 512 Paths, 32 ports IEEE 802.1ag (CFM), 802.3 (EFM), ITU-T Y.1731 (Eth-OAM), MEF-16

Embedded Processor 416 MHz MIPS24KEc Processor

DDR2

PI/SI

NPI

42

Serval-1™ VSC7418 Product Summary

8x GbE SGMII

24x24mm Industrial Temperature Range

1G/2.5G SGMII

Sampling Now

DDR2/3

PCIe

NPI

KEY FEATURES DETAILS 11-Port GbE Switch 8xSGMII+2x1G/2.5G SGMII+1xSGMII (NPI)

PCIe interface for external CPU connectivity

Carrier Service Architecture

Service Aware TCAM Classification –1K Service points •E-LINE, E-LAN, E-TREE over Q-Q or MPLS Policing, OAM, encaps, queuing, protection, stats per-service

H-QoS and MEF-compliant DLB Policing and Shaping

8 Mbits Shared Buffer memory, 2.6K queues, WRED Three-level scheduling, four-level shaping Pool of 256 DLB shapers, SLB shaper per strict-priority queue Pool of 1156 DLB policers, for Service, Port, COS/port, ACL


Per-service arrival/departure/discard counters Per-COS per-port arrival/departure/discard counters

Integrated Timing IEEE-1588v2 – one and two step in hw, 1588 over MPLS Synchronous Ethernet

Integrated OAM Engine

11 Port MEPs + pool of 64 Service/Path/Port Up/Down MEPs Continuity Check, Loopback, Delay, Loss in hardware RFC-2544/Y.1564 Service Activation Measurement (TST PDU)

Embedded Processor 416 MHz MIPS24KEc Processor, 1 Gbyte external DDR2/3 Warm restart capability

VSC7418 Serval-1™ CE Switch

2x 1G/2.5G SGMII

43

Serval-2™ VSC7438 Product Summary

12x GbE SGMII

2 XAUI/XFI

DDR2/3

PCIe

NPI

KEY FEATURES DETAILS Port Configurations 12x1G SGMII + 2x10G XAUI/XFI + SGMII NPI port , or

12x 1G SGMII + 4x 2.5G + 1x 10G (XFI/XAUI) + NPI, or 12x 1G SGMII + 8x 2.5G + NPI


Service Aware TCAM Classification – 1K Service points •E-LINE, E-LAN, E-TREE over Q-Q or MPLS Policing, OAM, encaps, queuing, protection, stats per-service


16 Mbits Shared Buffer memory, 2K queues, WRED Three-level scheduling, four-level shaping DLB shapers, DLB policers





Per-Port MEPs + pool of 256 Service/Path/Port Up/Down MEPs Ethernet OAM: Continuity Check, Loopback, Delay, Loss in hardware Sequence numbering, loss counters, timestamping, OAM statistics RFC-2544/Y.1564 Service Activation Measurement (TST PDU) MPLS-TP OAM: BFD generation/checking

Embedded Processor 500 MHz MIPS24KEc Processor, 1 Gbyte external DDR2/3 Warm restart capability, PCIe external CPU control interface

VSC7438 Serval-2™ CE Switch

44


Powerful Feature Enhancements in Jaguar-2™/LynX-2™ from Jaguar-1™/LynX-1™

KEY FEATURES DETAILS Migration Path from JR-1 Includes all existing function and software from Jaguar-1.

Maximum GE ports goes from 24 to 48, max 2.5G port support goes from 8 to 24 Integrated 10G SerDes XFP/SFP+, KR with FEC

Also support for XAUI/RXAUI H-QoS Per EVC queuing (>8K queues)

Three-level scheduling, four-level shaping DLB shapers, DLB policers

MPLS Ethernet Pseudowire LER, VPLS, LSR

L3 Classification and Routing 4K/1K IPv4/v6 LPM, 4K/1K hosts 2K/512 IPv4/v6 SSM multicast groups, 1K spread patterns

OAM and Performance Monitoring

Fully in HW for Ethernet and MPLS OAM: Continuity Check Loopback with address swap Frame Loss Measurement Up and Down MEP Delay Measurement Y.156SAM

Network Timing IEEE-1588v2 one and two step modes fully in HW, 1588 over MPLS

Integrated CPU Update Higher performance MIPS CPU, PCI-e, DDR2/3

Lynx-2™ Key Features

46

12/ 24x GbE SGMII

DDR2/3

PCIe

NPI

KEY FEATURES DETAILS Port Configurations •12x1G SGMII + 2x10G XAUI/XFI + 2x10G XFI + SGMII NPI port

•24x1G SGMII + 2x10G XAUI/XFI + SGMII NPI port •Up to 12x 2.5G ports (the total BW of the switch ports should be less than or equal to 52G)




32 Mbits Shared Buffer memory, >8K queues, WRED Three-level scheduling, four-level shaping DLB shapers, DLB policers





Per-Port MEPs + pool of 1K Service/Path/Port Up/Down MEPs Ethernet OAM: Continuity Check, Loopback, Delay, Loss in hardware Sequence numbering, loss counters, timestamping, OAM statistics RFC-2544/Y.1564 Service Activation Measurement (TST PDU) MPLS-TP OAM: BFD generation/checking

Embedded Processor 500 MHz MIPS24KEc Processor, 1 Gbyte external DDR2/3 Warm restart capability, PCIe external CPU control interface

VSC7464 Lynx-2™ CE Switch

2x 10G XAUI/XFI + 2x XFI


Jaguar-2™ Key Features

47

DDR2/3

PCIe

NPI

VSC7468 Jaguar-2™ CE Switch

24x GbE SGMII/SERDES/100FX or

48x GbE QSGMII

2x 10G XAUI/XFI + 2x XFI KEY FEATURES DETAILS

Port Configurations •24x1G/2.5G SGMII + 2x10G XAUI/XFI + 2x10G XFI+ SGMII NPI port •48x1G QSGMII + 2x10G XAUI/XFI + SGMII NPI port •Up to 24x 2.5G ports (the total BW of the switch ports should be less than or equal to 68G)




32 Mbits Shared Buffer memory, 8K queues, WRED Three-level scheduling, four-level shaping DLB shapers, DLB policers

Routing 4K/1K IPv4/v6 LPM, 4K/1K hosts 2K/512 IPv4/v6 SSM multicast groups, 1K spread patterns




Integrated OAM Engine Per-Port MEPs + pool of 1K Service/Path/Port Up/Down MEPs Ethernet OAM: Continuity Check, Loopback, Delay, Loss in hardware Sequence numbering, loss counters, timestamping, OAM statistics RFC-2544/Y.1564 Service Activation Measurement (TST PDU) MPLS-TP OAM: BFD generation/checking

Embedded Processor 500MHz MIPS24KEc Processor, 1 Gbyte external DDR2/3 Warm restart capability, PCIe external CPU control interface

Vitesse Software Components

Board Support Package OS running on the internal CPU

API Portable driver software for switch/MAC/PHY

Application Switch/MAC software running eCos on internal

CPU

Application

API

BSP

48

Vitesse Software Packages

PACKAGES SKU DESCRIPTIONS APPLICABLE TO Unified API VSC6802API Software API Switches, MACs and PHYs

CE Services SDK VSC6810SDK Carrier Ethernet software VSC7401/05/07, VSC7428/29, VSC7460/62, VSC7364/66

UnSparX SDK VSC6811SDK Unmanaged software for SparX-III VSC7420, VSC7421, VSC7422

WebStaX SDK VSC6812SDK Basic L2 managed VSC7424-29, VSC7432/34, VSC7401/05/07

SMBStaX SDK VSC6813SDK Advanced L2 managed VSC7424-29, VSC7432/34, VSC7401/05/07

Linux BSP VSC6830BSP Runs on the internal MIPS CPU VSC7424-29, VSC7432/34, VSC7460/62

WebSparX SDK VSC6821APP SparX web managed 8051 turnkey software VSC7385/88/89/90/91/95/98

49

SMBStaX

FEATURE VSC742x VSC743x Port Control: (Port Speed/Duplex Mode/Flow Ctrl, Frame Size, Status, Statistics, VeriPHY, POE/POE+, etc.) X X

Power Management: EEE, ActiPHY, PerfectReach, Adaptive Fan Control, LED Control, X (X)

QoS: Port/Queue/Service Policing, Port/Queue Shaping, SP/DWRR X X

QoS: DiffServ (RFC2474) & Tag Remarking X X

L2: IEEE-802.10D Bridge, IEEE-802.10Q VLAN, MAC & Protocol based VLAN, MRP, MVRP X X

L2: IEEE-802.10ad Provider Bridge (Native or Translated VLAN) X X

L2: LACP, MSTP, BPDU Guard & Restricted Role, IGMPv3 & MLDv2 snooping, Port & Flow mirroring X X

L3: DHCP Client/option 82 Relay, UPNP, IP MAC Binding X X

L3: IPv4/IPv6 Unicast: Static routing, IPv4/IPv6 Muticast Routing X

Stacking: Mixed 24/48-port stack X

Synchronization: NTPv4 X X

Security: Network Access Server (NAS): Port/Single/Multiple based 802.1X, MAC based Authent. Guest VLAN,ACL X X

Security: RADIUS Accounting, TACAS+, MAC Limit, Web & CLI Authent., 15 authorization levels, IP Src guard X X

Management: HTTP/HTTPs, CLI, Telnet, SSHv2, SNMPv3 MIBs, Stack Manamgement, IPv6 Management X X

Management: Cisco Discovery Protocol (CDP), sFlow X X

Management: IEEE 802.1AB-2005 Link Layer Discovery – LLDP, TIA 1057 LLDP-MED X X

Management: SMON X

50

CEServices

FEATURE CARACAL JAGUAR SERVAL

Power Management: EEE, ActiPHY, PerfectReach, Adaptive Fan Control, LED Control, X (X) X

QoS: Port/Queue/Service Policing, Port/Queue Shaping, SP/DWRR X X X

QoS: DiffServ (RFC2474) & Tag Remarking X X X

QoS: HQoS X

L2: IEEE-802.10D Bridge, IEEE-802.10Q VLAN, MAC & Protocol based VLAN, MRP, MVRP X X X

L2: IEEE-802.10ad Provider Bridge (Native or Translated VLAN) X X X

L2: LACP, MSTP, BPDU Guard & Restricted Role, IGMPv3 & MLDv2 snooping, Port & Flow mirroring X X X

L2: G.8031/G.8032v2 X X X

L2: PB EVC Services E-LINE, E-LAN, E-TREE, Service Protection X X X

L2: MPLS-TP LER/LSR Services E-LINE, E-LAN, E-TREE, Service Protection X

L3: DHCP Client/option 82 Relay, UPNP, IP MAC Binding X X X

OAM: Flow OAM IEEE802.1ag/Y.1731 (FM, PM), Link OAM 802.3ah, UP-MEP/Down-MEP (X) (X) X

Synchronization: SyncE SSM, 1588 PTP single/two-step Clock, BC, TC, NTPv4 X X X

Security: NAS: Port/Single/Multiple based 802.1X, MAC based Authent. Guest VLAN, ACL X X X

Security: RADIUS Accounting, TACAS+, MAC Limit, Web & CLI Authent., 15 authorization levels, IP Src guard X X X

Management: HTTP/HTTPs, CLI, Telnet, SSHv2, SNMPv3 MIBs, IPv6 Mng.,Cisco Discovery Protocol (CDP) X X X

Management: IEEE 802.1AB-2005 Link Layer Discovery – LLDP, TIA 1057 LLDP-MED, sFlow X X X

Power Management: EEE, ActiPHY, PerfectReach, Adaptive Fan Control, LED Control, X (X) X

51

Transparent Clock Support Over Microwave Links

February 2012

The Problem: PDV Across Microwave Link

53

The Problem: PDV Across Microwave Link

The fundamental assumption in PTP protocol is that the round trip path delay between the master and slave clocks are symmetric, or at least fixed, not variable.

IEEE1588v2 Transparent clock (both End-to-End and Peer-to-Peer) removes the packet delay variation within the switch elements from the equation.

Microwave links present another challenge: packet delay across microwave link are not fixed, and may not be symmetric: Bitrate changes on the wireless link Modulation scheme change as well as FEC used Packet buffering in modems

This reduces timing accuracy across a microwave link in model A)

54

Vitesse Solution: Distributed Transparent Clock

Patent pending solution to solve packet transmission delay variations across microwave link.

Distributed Transparent Clock Uses Vitesse’s hardware based 1588v2 solution providing

accuracy <10ns

Two options: Solution based on Caracal switch (Solution- B) Solution based on Serval switch (Solution - D)

55

Solution B

56

Solution B: TOD Sync up Between Two Caracals

Prerequisite: frequency & phase locked 1PPS signal available on two Caracals at both sides of the microwave link.

Upon receiving a 1PPS, master Caracal sends a “TOD preset message” in-band to the slave Caracal with the following info: “set TOD to xx:yy:zz (zz represents ns accuracy) when receive the next 1PPS”. Xx:yy:zz is master Caracal’s TOD + 1s.

Assuming the slave Caracal consumes the message before the next 1PPS arrives. At the arrival of the next 1PPS, both Caracals have synchronized TOD.

Both Caracals will now advance their TOD at the same pace as they both use the 1PPS signals to advance their clocks.

The protocol can be repeated to avoid drifting of TOD.

57

Serval’s Timing Over Microwave

Prerequisite: Synchronization of Serval-1’s at both sides of the microwave link (see next slide)

All hardware distributed transparent clock for fiber interfaces Similar to Vitesse’s 1588v2 PHY model

Standard CuPHYs (non-1588 aware) can be used in front of Serval for copper interfaces Alternatively Vitesse 1588v2 CuPHYs can be used for copper interfaces for higher accuracy

58

Synchronizing the devices at both ends

The Serval devices in each end of the link needs to be synchronized The accuracy of this synchronization affects the accuracy of the distributed TC operation

The synchronization of the Serval devices can be done in several ways: 1. Modem has a proprietary synchronization feature that can deliver a synchronization pulse to each of the Serval

– Can be done using special synchronization code-groups – layer 1 2. Modem has a fixed known RX/TX latency (low bandwidth sidechannel) path through the modem that can be

used by the two Servals to synchonize using special PTP messages – Uses a local PTP time domain for this communication

3. Modem has a fixed and known RX/TX latency for each modulation scheme and can provide information about the current modulation scheme to Serval – The two Servals can take the Modem latency into account when synchronizing the two Servals using a

special PTP protocol, see next slide 4. Modem does not have any special PTP features but has symmetrical or known latency skew

– The two Servals can be synchronized using a local PTP connection using an advanced PTP filtering algorithm

– This is the least accurate method The two Servals can be frequency locked through a SyncE channel if supported by the Modems

Can also use PTP/1PPS syntonized clock This requires a more stable frequency reference like TCXO or OCXO

59

Improved IEEE1588 operation for timing unaware ODUs using Serval-1.

The two Serval devices are not 1PPS and TOD synchronized. Each side of link has local timing reference and uses a local PTP connection to synchronize the two devices to a local time

domain (low PTP packet rate – 1-16 frames/second) Servals internal CPU communicate with Modem to get modulation scheme information

(current latency and bandwidth thought the modem). PDV in wireless transmission (modem -> wireless link -> modem) is reduced as follows:

By knowing the current maximum bandwidth currently used by modems, the two Servals adusts the shaper bandwidth of the modem ports to match the modem bandwidth, resulting in no buffering in the modem, but buffering in the Serval devices

The local PTP connection takes the actual modem latencies into account when running the PTP protocol and discards any synchronization frames sent during a modulation change

60

Caracal-1

February 2012

VSC7429 Block Diagram

Ingress Processing

Device Interface

PortModule

#0

PortModule

#1

PortModule

#11

PortModule

#12

PortModule

#23

PortModule

#24

PortModule

#25

12 x CuPHY

P0_D

[3:0]NP

0_D[3:0]P

P1_D

[3:0]NP

1_D[3:0]P

P11_D

[3:0]NP

11_D[3:0]P

Egress Processing

Shared Queue System

CPUPort

Module

Security Enforcement

Ingress Statistics

L2 Forwarding

ClassificationVLAN and QoS

Translation/Remarking

S1 TCAM

Rewriter

VLAN translationPush/pop tags

DSCP remapping

ES0 TCAM

S2 TCAM

Policers

Egress Statistics

Shared Memory Pool

Memory Controller

Shaper and Scheduler

SGMIIMacro

SGMIIMacro

QSGMIIMacro8-11

QSGMIIMacro

4-7

QSGMIIMacro

0-3

4x 4x 4x

Switch-core

Copper P

HY

s

High S

peed I/Os

EJTAG

MIPS 24KEc

MMU

I-Cache32 kB

D-Cache32 kB

CPU Systems Bus

GenericDMA

FrameDMA

TargetAccess

TimerRTCWDT

Arbiter

CPU System – Vcore-III

QS

GM

II1_TxPQ

SG

MII1_TxN

QS

GM

II1_RxP

QS

GM

II1_RxN

QS

GM

II2_TxPQ

SG

MII2_TxN

QS

GM

II2_RxP

QS

GM

II2_RxN

SG

MII0_TxP

SG

MII0_TxN

SG

MII0_R

xPS

GM

II0_RxN

QS

GM

II0_TxPQ

SG

MII0_TxN

QS

GM

II0_RxP

QS

GM

II0_RxN

SG

MII1_TxN

SG

MII1_TxP

SG

MII1_R

xNS

GM

II1_RxP

SI_ClkSI_DISI_DOSI_nEn

MDC_0MDIO_0

DD

R2 M

emory C

ontroller

GPIOPI

LEDSer.GPIO

UARTSFPTWI

GPIO[31:0]

MIIM

SI

JTAG_CLKJTAG_DIJTAG_DOJTAG_TMSJTAG_TRT

JTAG

CPU I/F

Vcore_cfg[1:0]nRESETVCore_EJTAG_nEnRefClk_Sel[2:0]RefClkPRefClkN

MAC MAC MAC MAC MAC MAC MAC

DDR_DQSDDR_DQSnDDR_DMDDR_DQ[7:0]DDR_ODTDDR_CkDDR_CknDDR_nRASDDR_nWEDDR_CkeDDR_nCASDDR_BA[2:0]DDR_A[13:0]

CPURegisters

416MHz MIPS CPU system With DDR2 memory interface

1024 T-CAM based Package inspection engines

4Mbit shared memory pool and 8 queues per port

12 x GE CuPHYs

26x 1G MACs

3xQSGMII & 1xSGMII & 1x1/2.5G SGMII

IEEE1588v2 SyncE

1588 SyncE

62

CPU Systems

CPUPort

Module

EJTAG

MIPS 24KEc

MMU

I-Cache32 kB

D-Cache32 kB

CPU Systems Bus

GenericDMA

FrameDMA

TargetAccess

TimerRTCWDT

Arbiter



MDC_0MDIO_0

DD

R2 M

emory C

ontroller

GPIOPI

LEDSer.GPIO

UARTSFPTWI

GPIO[31:0]

MIIM

SI


JTAG

CPU I/FDDR_DQSDDR_DQSnDDR_DMDDR_DQ[7:0]DDR_ODTDDR_CkDDR_CknDDR_nRASDDR_nWEDDR_CkeDDR_nCASDDR_BA[2:0]DDR_A[13:0]

CPURegisters

Ingress Processing

Device Interface

PortModule

#0

PortModule

#1

PortModule

#11

PortModule

#12

PortModule

#23

PortModule

#24

PortModule

#25

12 x CuPHY

P0_D

[3:0]NP

0_D[3:0]P

P1_D

[3:0]NP

1_D[3:0]P

P11_D

[3:0]NP

11_D[3:0]P

Egress Processing

Shared Queue System

CPUPort

Module


Ingress Statistics

L2 Forwarding

ClassificationVLAN and QoS

Translation/Remarking

S1 TCAM

Rewriter


DSCP remapping

ES0 TCAM

S2 TCAM

Policers

Egress Statistics

Shared Memory Pool

Memory Controller

Shaper and Scheduler

SGMIIMacro

SGMIIMacro

QSGMIIMacro8-11

QSGMIIMacro

4-7

QSGMIIMacro

0-3

4x 4x 4x

Switch-core

Copper P

HY

s

High S

peed I/Os

EJTAG

MIPS 24KEc

MMU

I-Cache32 kB

D-Cache32 kB

CPU Systems Bus

GenericDMA

FrameDMA

TargetAccess

TimerRTCWDT

Arbiter


QS

GM

II1_TxPQ

SG

MII1_TxN

QS

GM

II1_RxP

QS

GM

II1_RxN

QS

GM

II2_TxPQ

SG

MII2_TxN

QS

GM

II2_RxP

QS

GM

II2_RxN

SG

MII0_TxP

SG

MII0_TxN

SG

MII0_R

xPS

GM

II0_RxN

QS

GM

II0_TxPQ

SG

MII0_TxN

QS

GM

II0_RxP

QS

GM

II0_RxN

SG

MII1_TxN

SG

MII1_TxP

SG

MII1_R

xNS

GM

II1_RxP


MDC_0MDIO_0

DD

R2 M

emory C

ontroller

GPIOPI

LEDSer.GPIO

UARTSFPTWI

GPIO[31:0]

MIIM

SI


JTAG

CPU I/F

Vcore_cfg[1:0]nRESETVCore_EJTAG_nEnRefClk_Sel[2:0]RefClkPRefClkN

MAC MAC MAC MAC MAC MAC MAC

DDR_DQSDDR_DQSnDDR_DMDDR_DQ[7:0]DDR_ODTDDR_CkDDR_CknDDR_nRASDDR_nWEDDR_CkeDDR_nCASDDR_BA[2:0]DDR_A[13:0]

CPURegisters 416MHz MIPS

CPU system With DDR2 memory interface

MIPS 24KEc™ CPU system with memory management unit (MMU) 32 KB I-cache and 32 KB D-cache

CPU frame extraction (eight queues)

and injection (one queue) through DMA, which enables data transfer between Ethernet ports and CPU

EJTAG debug interface 8-bit DDR2 SDRAM interface

63

QoS Overview

Caracal is designed to deliver Flexible service offerings with guaranteed per-service SLAs

Class-based Queue System with Hierarchical QoS overlay Three levels of hierarchy Service/Class/Priority Port Global

Flexible mappings on every ingress and egress port PCP, DEI, VID, DSCP

SLA-aware Queue System Guaranteed delivery of committed rates Best-effort delivery of excess rates

64

Quality of Service with 8 Priority Queues

8 QoS queues per port with strict or deficit weighted round robin scheduling (DWRR)

TCAM-based QoS classification with pattern matching against L2 - L4 information

256 QoS and VLAN TCAM entries

DSCP translation, both ingress and/or egress

DSCP remarking based on QoS class

Per-queue and per-port policing and shaping, programmable in steps of 100 kbps

Full-duplex flow control (IEEE802.3x) and half-duplex backpressure, symmetric and asymmetric

Strict Prio

PolicerQ7Q6

Q5Q4Q3

Q2Q1

Q0VoIP

IPTV

VoIP

IPTV

www www

VPN

Game

FTP FTP

Updates

Game

File share

DWWR

PolicerVoIPGame

Arbiter 8 Queues

Queue System

Looks at QoS

Very flexible Quality of Service with 8 queues Most competitors only have 4 or less!

65

Hierarchical Policing

Three Levels of Policing 1. Service/Priority Policers (8 per port)

MEF-compliant Dual Leaky Bucket Policers Color-Blind or Color-Aware Remarking and Discard Bandwidth based, 100 kbps granularity One Service Policer can be triggered per frame

2. Ingress Port Policers (1 per Port) MEF-compliant Dual Leaky Bucket Policers Color-Blind or Color-Aware Remarking and Discard Bandwidth based, 100 kbps granularity One Ingress Port Policer can be triggered per frame CPU-redirected special frames (IEEE reserved MAC addresses) can bypass policers.

3. Global VCAP Policers (Up to 256) MEF-compliant Dual Leaky Bucket Policers Color-Blind or Color-Aware Remarking and Discard Bandwidth based, 100 kbps granularity 1 Global VCAP Policer can be triggered per frame, triggering based on VCAP-II S2 action Multiple services can map to one VCAP policer enabling tunnel policing Example: Limit CPU traffic to prevent DOS attacks, IGMP traffic limits, Learn limits Sticky bit set, can use to detect abnormal traffic

66

Priority Queuing, Scheduling, Shaping in Caracal

DWRR

Q5Wt_5

Q4Wt_4

Q3Wt_3

Q2Wt_2

Q1Wt_1

Q0Wt_0

Q7

Q6Med

High

Low

STRICT

PortShaper

Q6Shaper

Q7Shaper

Ethernet Line Port

67

Three-level Egress Scheduling and Shaping

Hierarchical QoS by looping traffic on unused ports

First pass through the switch: Scheduling and shaping based on

CoS per EVC Second pass through the switch:

Scheduling and shaping based on EVC

Using this scheme a large number of queues can be scheduled against a single egress port.

With 8 unused ports, 64 queues can be achieved.

Unused port

Unused port

Unused port

N EVCs

STRICT

Q6Q7

Q5

Q0

S/DWRR

STRICT

Q6Q7

Q5

Q0

S/DWRR

STRICT

Q6Q7

Q5

Q0

S/DWRR

SDWRR

Port M-2

Port M+N-1

Port M+N-2

PortM

PortM+N-1

Port M+N-2

PortM

PortM+N

2nd pass1st pass

CoS Scheduling and Shaping in EVC.Per EVC shaping

Scheduling and Shaping of EVCs.Per Port shaping

Single leaky bucket shaping

EVCN

EVCN-1

EVC0

Unused Caracal ports

SSS

S

SSS

S

SSS

S

Q6Q7

Q5

Q0

SSS

S

S

Port M-1

Port 0

S Probably not used

FC

FC

FC

68

Vitesse CE devices support reference clock generation

G.8261 Synchronous Ethernet and IEEE-1588

Time stamping in HW, PTP Software runs on embedded CPU. Vitesse CE Service software supports following clock types:

Ordinary Clock (master or slave)

Peer-to-Peer Transparent Clock

End-to-End Transparent Clock

Boundary Clock

PDV algorithm from 3rd party- Zarlink and Symmetricom

Vitesse switches provide 1588 TOD, 1PPS and reference clk outputs

Reference clock output unfiltered, frequency is programmable 10 – 25 MHz. Requires using external clock synchronization logic, Such as SiLabs, Zarlink, Semtech, Maxim

accepts TOD load and 1PPS inputs when operated as Master

Caracal based IEEE-1588 Architecture

SFP

SFP

VSC7462LynX-1VSC742x1 GbE

1 GbE

ClockSynchronization

Circuitry

RCVR

D_CL

K0

SPI/I

2C C

ontro

l

Central Reference Clock InCentral Reference Clock Out

Local Ref.Clock In

RCVR

D_CL

K1

1588

_Clo

ck

REFC

LK1000BASE-T andSGMII

1GbE 1000Base-T

SGMII

For GE/2.5G only applications, Caracal is the lowest power, size and cost solution in the industry

VSC7428 Caracal-1™

69

Serval-1

February 2012

Serval-1 Block Diagram

Buffer Memory Hierarchical QoS

Ingress Processing

Port Module Interface

Port Module

#0

Port Module

#7

Port Module

#8

Egress Processing

Shared Queue System


Ingress Statistics

L2 Forwarding

VLAN and QoS Classification

Translation/RemarkingIS1 TCAM

Rewriter

MPLS encapsulation


DSCP remapping

ES0 TCAM

IS2 TCAM

Policers

Egress Statistics

Shared Memory Pool8Mbit

Memory Controller

Hierarchical QoSShaper and Scheduler

SerDes6G#0

(2.5G SGMII)

Switch-core

High Speed I/Os

EJTAG

MIPS 24KEc

MMU

I-Cache32 kB

D-Cache32 kB

CPU Systems Bus

GenericDMA

FrameDMA

TargetAccess

TimerRTCWDT

Arbiter


SerD

es_E0_TxP

SerD

es_E0_TxN

SerD

es_E0_R

xPS

erDes_E

0_RxN

CPU I/F

nRESETVCore_ICE_nEnRefClk_Sel[2:0]RefClkPRefClkN

MAC1588

MAC1588

CPU Registers

MAC/PCS1588

Port Module

#9MAC/PCS

1588

Port Module

#10MAC/PCS

1588

SerDes1G#0

(SGMII)

SerDes1G#7

(SGMII)

SerD

es7_TxNS

erDes7_TxP

SerD

es7_RxN

SerD

es7_RxP

SerD

es0_TxNS

erDes0_TxP

SerD

es0_RxN

SerD

es0_RxP

SerDes6G#1

(2.5G SGMII)

SerDes1G#8

(SGMII)

SerD

es_E1_TxP

SerD

es_E1_TxN

SerD

es_E1_R

xPS

erDes_E

1_RxN

SerD

es_8_TxPS

erDes_8_TxN

SerD

es_8_RxP

SerD

es_8_RxN

MPLS Classification

IS0 TCAM

CPU Port Module

OAM Engine

Register Read/Write Access

CPUExtraction and Injection

DDR2

SPI

MIIM

MIIM Slave (GPIO)

JTAG

GPIOs (32)

UART (GPIO)

TWI (GPIO)

Serial GPIO (GPIO)

Temp Diodes (2)

External Interrupts (GPIO)

SPI Chip Selects (GPIO)

IEEE1588 Pulse (GPIO)

Fan Controller (Tacho, PWM) (GPIO)

SFP Signal Detect (GPIO)

SyncE Recovered Clocks (2)

PCI-E

10 switch ports: 8x 1GbE + 2x 1GbE/ 2.5GbE

TCAM Packet Processing Ingress and Egress

416 MHz MIPS CPU w/ 1GBytes external DDR2/3

External CPU Intf. 1 GbE “NPI” Port

Switch core

71

Integrated CPU System

416 MHz MIPS24KEc 1GB external DDR2/DDR3 memory 32 KB I-cache and 32 KB D-cache Injection and extraction of data frames via FDMA FDMA has 1Gbps Interface to switch core shared

between injection and extraction Boot options Internal MIPS and FLASH DDR Memory required for MIPS External CPU w/out Flash and no MIPS FDMA can be controlled from external CPU. Requires

DDR memory Switch core can forward between two ports out of boot.

Ingress Processing


Port Module

#0

Port Module

#7

Port Module

#8

Egress Processing

Shared Queue System


Ingress Statistics

L2 Forwarding



Rewriter

MPLS encapsulation


DSCP remapping

ES0 TCAM

IS2 TCAM

Policers

Egress Statistics


Memory Controller


SerDes6G#0

(2.5G SGMII)

Switch-core

High Speed I/Os

EJTAG

MIPS 24KEc

MMU

I-Cache32 kB

D-Cache32 kB

CPU Systems Bus

GenericDMA

FrameDMA

TargetAccess

TimerRTCWDT

Arbiter


SerD

es_E0_TxP

SerD

es_E0_TxN

SerD

es_E0_R

xPS

erDes_E

0_RxN

CPU I/F


MAC1588

MAC1588

CPU Registers

MAC/PCS1588

Port Module

#9MAC/PCS

1588

Port Module

#10MAC/PCS

1588

SerDes1G#0

(SGMII)

SerDes1G#7

(SGMII)

SerD

es7_TxNS

erDes7_TxP

SerD

es7_RxN

SerD

es7_RxP

SerD

es0_TxNS

erDes0_TxP

SerD

es0_RxN

SerD

es0_RxP

SerDes6G#1

(2.5G SGMII)

SerDes1G#8

(SGMII)

SerD

es_E1_TxP

SerD

es_E1_TxN

SerD

es_E1_R

xPS

erDes_E

1_RxN

SerD

es_8_TxPS

erDes_8_TxN

SerD

es_8_RxP

SerD

es_8_RxN

MPLS Classification

IS0 TCAM

CPU Port Module

OAM Engine



DDR2

SPI

MIIM

MIIM Slave (GPIO)

JTAG

GPIOs (32)

UART (GPIO)

TWI (GPIO)

Serial GPIO (GPIO)

Temp Diodes (2)







PCI-E

72

Shared Queue System

8 Mbit Buffer Memory Minimum speedup = 5x 8 QoS classes per port with guaranteed buffer Up to 2600 Service Queues

Guaranteed scheduling bandwidth per service queue No buffer Guarantees per service queue

Hierarchical Queuing and scheduling Port, queue and Service modes 4 dual-rate shaping levels and 3 scheduling levels

Buffer Memory Management Reserved Memory – Watermarks per Qos Class and Port Shared Memory – Per service queue WRED per QoS Class and color (green/yellow)

Highly Configurable Queuing and Scheduling Modes LEGO™-like configuration of scheduling hierarchy

Ingress Processing


Port Module

#0

Port Module

#7

Port Module

#8

Egress Processing

Shared Queue System


Ingress Statistics

L2 Forwarding



Rewriter

MPLS encapsulation


DSCP remapping

ES0 TCAM

IS2 TCAM

Policers

Egress Statistics


Memory Controller


SerDes6G#0

(2.5G SGMII)

Switch-core

High Speed I/Os

EJTAG

MIPS 24KEc

MMU

I-Cache32 kB

D-Cache32 kB

CPU Systems Bus

GenericDMA

FrameDMA

TargetAccess

TimerRTCWDT

Arbiter


SerD

es_E0_TxP

SerD

es_E0_TxN

SerD

es_E0_R

xPS

erDes_E

0_RxN

CPU I/F


MAC1588

MAC1588

CPU Registers

MAC/PCS1588

Port Module

#9MAC/PCS

1588

Port Module

#10MAC/PCS

1588

SerDes1G#0

(SGMII)

SerDes1G#7

(SGMII)

SerD

es7_TxNS

erDes7_TxP

SerD

es7_RxN

SerD

es7_RxP

SerD

es0_TxNS

erDes0_TxP

SerD

es0_RxN

SerD

es0_RxP

SerDes6G#1

(2.5G SGMII)

SerDes1G#8

(SGMII)

SerD

es_E1_TxP

SerD

es_E1_TxN

SerD

es_E1_R

xPS

erDes_E

1_RxN

SerD

es_8_TxPS

erDes_8_TxN

SerD

es_8_RxP

SerD

es_8_RxN

MPLS Classification

IS0 TCAM

CPU Port Module

OAM Engine



DDR2

SPI

MIIM

MIIM Slave (GPIO)

JTAG

GPIOs (32)

UART (GPIO)

TWI (GPIO)

Serial GPIO (GPIO)

Temp Diodes (2)







PCI-E

73

Comprehensive Service Awareness

Three independent lookups per frame VLAN, QoS, Service Port, VLANs, SMAC, DMAC, SIP, SPORT, DPORT, IP Proto, DSCP Filter IGMP, MLD frames

Ingress service classification with the following parameters: Service policing Ingress service statistics

– Green/Yellow/Red arrivals (bytes and frames) – Green and Yellow discards (bytes and frames) due to L2 forward and queue discards

Path protection group – 64 Paths are supported

Egress TCAM lookup for per-port encapsulation and statistics Egress service statistics

– Green/Yellow departures (bytes and frames)

Color-aware Port/COS counters also Green/Yellow/Red arrivals on each COS on each port Green/Yellow discards on each COS on each port Green/Yellow departures on each COS on each port

74

Policing

4-levels of Hierarchical policing Up to 3 policers per frame: (Service or COS/port), Port, and ACL-triggered policers MEF-compliant DLB policers OAM frames are not policed by service policers, but can be policed separately

A total of 1152 DLB policers 1024 dedicated policers for Service 96 policers for COS/port 12 policers for Port 20 policers for ACL. Unused COS/port and Port policers can be used by ACLs

75

Hierarchical Queuing and Scheduling

Best in Class Scheduling Capabilities Priority Fairness

– Guarantees priority fairness regardless of the ingress port Port Fairness

– Guarantees each ingress port a fair share of the egress port bandwidth independent of the distribution of priority traffic on each ingress port

Standard Service Group scheduling – Guarantees service group fairness independent of the priority traffic on each

service group Advanced Service Group scheduling

– 4 shaping levels, and 3 scheduling levels – supports MEF service definition Priority Scheduling All Strict Priority (SP), 2 SP+6 DWRR , 3 SP+5 DWRR , all Weighted (8 DWRR)

Priority based flow control

76

Priority Fairness Mode

Scheduling for one port: Default scheduling mode 8 QoS classes per output port

DLB shaping of the output port and each QoS class

Scheduling Level 1: Scheduling among QoS classes

Scheduling Level 2: Scheduling among Input Ports within each class One Virtual Input Queue per output Port COS

Total Scheduling: 8x12 = 96 queues

Guarantees each QoS class and input port a fair share of the bandwidth on the output port independent of traffic distribution among ingress ports.

77

Port Fairness Mode MAC-like Queuing

DLB shaping of the Aggregation Port and each input Port

Scheduling Level 1: Flexible scheduling among input Ports

Scheduling Level 2: Flexible scheduling of QoS classes within

each input Port Each input Port scheduler has a dedicated

queue for each QoS class SLB shaping of each SP queue Total Scheduling: 12x8 = 96 queues

Scheduling for one port:

Guarantees each Input Port a fair share of bandwidth on the Aggregation Port independent of traffic distribution among QoS classes within each Input Port

78

Service Group Scheduling

12 Service Groups per destination port Similar to Port Fairness

Organization into Service Groups rather than Input Ports

One or more services can map to a Service Group

Service classification is performed by the Analyzer

Service Group mapping may be independent of Input Port

Each service can be policed at ingress before being assigned to a Service Group


Guarantees each Service Group a fair share of bandwidth on the Aggregation Port independently of the traffic distribution among QoS classes within each Service Group

79

Advanced Service Group Scheduling

96 Service Groups on up to two destination ports

Hierarchical scheduling and shaping Shaping levels 1, 2, and 3 are DLB Shaping level 4 (QoS Class) is SLB Sch Levels 1 and 2 schedules

between Service Groups Sch Level 3 schedules between

priorities within a Service Group


An EVC or E-LSP (with more than one priority) can be mapped to a dedicated Service Group. A group of EVCs or L-LSPs (each with one priority) can share a Service Group

80

Fully Integrated MPLS/MPLS-TP

MPLS/MPLS-TP EoMPLS PW LER (Single-Segment and Multi-Segment) MPLS LSR MPLS-TP OAM support for int/ext CPU software or external OAM engine

MPLS-TP protection MPLS over Ethernet Ring

– Drop and Continue using G.8032 at the MPLS Link Layer – PW termination or LSR operation on the locally dropped data

Linear Protection – 1:1 LSP or PW switch over (one service at a time) – 1:1 Protect Group switch over (a group of services at a time)

Facility Bypass protection per RFC-4090 (a group of services at a time)

81

Highest Feature IEEE 1588 Solution

One and two step modes HW-based frame modification on ingress/egress, better than 10 nS accuracy Asymmetry and path delay adjustment functions

– Symmetry and one-step accuracy are critical to meeting LTE TOD/phase accuracy specifications All IEEE-1588v2 clock types:

Ordinary Clock (master or slave) Peer-to-Peer Transparent Clock End-to-End Transparent Clock Boundary Clock

Timestamp and Transparent Clock for 1588 over MPLS: IP/MPLS and PWE Use of MPLS is critical to meeting LTE TOD/phase accuracy specifications

1588 TOD output, with 1PPS and ref clock inputs/outputs Unfiltered reference clock output, frequency is programmable 10 – 25 MHz Accepts 1PPS input for TOD load Separate SyncE/1588 reference clocks is critical to meeting LTE wander specifications

Internal MIPS processor for running PTP protocol and filtering SW

82

Carrier Class OAM Functionality

OAM Functions – at the Port, Service and Path level IEEE 802.1ag (CFM) IEEE 802.3 (EFM) MEF-16 (E-LMI) ITU-T Y.1731 (ETH-OAM)

Y.1731/802.1ag OAM Hardware support In Ethernet and Ethernet Pseudowires

Loopback, Continuity Checks (CCM), Frame Delay Measurements, one-way and two-way Frame Loss Measurements Frame modification on ingress and egress for Tx Counters and Timestamps OAM Delay/Loss frames fully updated in HW. Full SW protocol support also provided by Vitesse. Ethernet Loopback with SA/DA swap up to 2.5Gb/s rate and modification from LBM to LBR op code Sequence number update/check and OAM statistics

UP and DOWN MEP support in Hardware Service Activation Measurement support in Hardware

83

OAM (continued)

MEP/MIP hardware support 1 hardware MEP/MIP per port Pool of 64 hardware MEP/MIPs to use for port/path/service layers MEP/MIP nesting up to 3 layers deep No TCAM resources required to utilize MEP/MIP hardware

Pool of 1K dedicated OAM flow generators Generate CCM, DMM, LMM, LBM /TST per MEP/MIP

– For example, 4 flows x 75 MEP/MIPs = 300 OAM flow generators consumed – Remaining 724 OAM flow generators can be used by SW-implemented MEP/MIPs if needed

Configurable rate for each flow, no bandwidth restriction – 8 timers shared by all flows, 200 nS min timer setting, 200 nS resolution

Sequence number, timestamp, frame count all updated/checked by hardware for HW MEP/MIPs – IS2 can implement partial checking for SW-implemented MEP/MIPs if needed

Service Activation hardware support Use OAM generator for single TST frame sent repeatedly

– Sequence number support provided by HW MEP/MIP Use FDMA inject for multi-thread patterns sent repeatedly No support for PRBS gen/check or payload CRC check

– Frame FCS is generated and checked

84

Ethernet OAM Summary

KEY FEATURES SCALE Port MEPs 11. Down-MEP only Path/Service MEPs Pool of 64. Both Up- and Down-MEP support

HW MEPs require no extra TCAM resources OAM Loopback Down-MEP loopback all in HW

Per port Out-of-Service Up-MEP loopback all in HW In-Service Up-MEP loopback is HW accurate but SW assisted. SW performs traffic looping using received copy of original OAM frame

Automatic HW OAM frame generation

1K single frame timer based injections targeted at CCM, LMM, DMM, and LBM/TST. No bandwidth limitation. Sequence numbering, frame count updates and timestamp values performed by HW MEP Both Up- and Down-MEP injections supported. Up-MEP injection requires dedicated loop port

FDMA assisted OAM frame generation

600Mbps SAM multi frame flow bandwidth supported (LBM/TST) Sequence numbering performed by HW MEP Both Up- and Down-MEP injections supported without dedicated loop port.

HW OAM checking Sequence number, frame count checks performed by HW MEP TST frames discarded by HW MEP

Assist functions for additional SW MEPs

Partial filtering for CCMs can be performed using VCAP_IS2 rules Automatic OAM frame generation can be used for SW MEPs with no OAM PDU updates.

85

Protection Switching Features

Port, Path, and Service Protection Switching Hardware Ethernet Ring Protection Switching (ERPS) , G.8032 Support for non-overlapping sets of VLANs per port Support for multiple rings

86

Thank You www.vitesse.com/ce

vitesse mobile backhaul solution presentation (3)

Documents

oam phys

mobile access timing

small cell mw

phys npu

timing synchronization

functionality phys

cell site routers

small switches