vlsi design flow
TRANSCRIPT
VLSI Design FlowWith Reference to Xilinx Tool
1
VLSI Design Flow with Reference to Xilinx EDA Tool
3
HDL (VHDL /Verilog)
Synthesize
Netlist
Map
Place
Route
Bitstream
Hardware design is traditionally done by modeling the
system in a hardware description language
An FPGA “compiler” (synthesis tool) generates a netlist,
which is then mapped to the FPGA technology,
the inferred components are placed on the chip,
and the connecting signals are routed through the
interconnection network.
FPGAs FPGA Tool Flow System on Chip (SoC) SoC Tool Flow Demonstration
FPGA Tool Flow
4
Register
ab
output
clk
reset
clear
D Q
process(clk, reset)begin
if reset = ‚1‘ thenoutput <= ‚0‘;
elsif rising_edge(clk) thenoutput <= a XOR b;
end if;end process;
HDL (VHDL /Verilog)
Synthesize
Netlist
Map
Place
Route
Bitstream
FPGAs FPGA Tool Flow System on Chip (SoC) SoC Tool Flow Demonstration
Synthesis Tool
5
HDL (VHDL /Verilog)
Synthesize
Netlist
Map
Place
Route
Bitstream
Register
ab
output
clk
reset
clear
D Q
FPGAs FPGA Tool Flow System on Chip (SoC) SoC Tool Flow Demonstration
Technology Mapping
6
HDL (VHDL /Verilog)
Synthesize
Netlist
Map
Place
Route
Bitstream
FPGAs FPGA Tool Flow System on Chip (SoC) SoC Tool Flow Demonstration
Place & Route
