vlsi design i - bfh · pdf filecomputer-computer--aided test programs (cat) ... design for...

MicroLab, VLSI-20 (1/26)

JMM v1.4

VLSI Design IVLSI Design IVLSI Design IVLSI Design ITest Pattern Generation and Fault SimulationTest Pattern Generation and Fault SimulationTest Pattern Generation and Fault SimulationTest Pattern Generation and Fault Simulation

Let‘s test a chip?Let‘s test a chip?Let‘s test a chip?Let‘s test a chip?

OverviewOverviewOverviewOverview Test pattern generationTest pattern generationTest pattern generationTest pattern generation Fault simulationFault simulationFault simulationFault simulation

Goal: Goal: Goal: Goal: Design for testability terms like Design for testability terms like Design for testability terms like Design for testability terms like controllability and controllability and controllability and controllability and observability observability observability observability are known. You are are known. You are are known. You are are known. You are familiar with test pattern algorithms as well as familiar with test pattern algorithms as well as familiar with test pattern algorithms as well as familiar with test pattern algorithms as well as with testability measure metrics.with testability measure metrics.with testability measure metrics.with testability measure metrics.


JMM v1.4

TestersTestersTestersTestersThe device under testThe device under testThe device under testThe device under test(DUT) can be a site on(DUT) can be a site on(DUT) can be a site on(DUT) can be a site ona wafer or a packageda wafer or a packageda wafer or a packageda wafer or a packagedpart.part.part.part.

ttttCYCLECYCLECYCLECYCLE

nonnonnonnon----returnreturnreturnreturn----totototo----zero (NRZ)zero (NRZ)zero (NRZ)zero (NRZ)

returnreturnreturnreturn----totototo----zero (RTZ)zero (RTZ)zero (RTZ)zero (RTZ)

returnreturnreturnreturn----totototo----one (RTO)one (RTO)one (RTO)one (RTO)

surroundsurroundsurroundsurround----bybybyby----complement (SBC)complement (SBC)complement (SBC)complement (SBC)

datadatadatadata

datadatadatadata

datadatadatadata

datadatadatadata ~data~data~data~data~data~data~data~data

pinpinpinpincircuitrycircuitrycircuitrycircuitry

100’s100’s100’s100’s

Each pin on the chip isEach pin on the chip isEach pin on the chip isEach pin on the chip isdriven/observed by adriven/observed by adriven/observed by adriven/observed by aseparate set of circuitry which typically can drive the pin to oseparate set of circuitry which typically can drive the pin to oseparate set of circuitry which typically can drive the pin to oseparate set of circuitry which typically can drive the pin to one data value ne data value ne data value ne data value per cycle or observe (“strobe”) the value of the pin at a particper cycle or observe (“strobe”) the value of the pin at a particper cycle or observe (“strobe”) the value of the pin at a particper cycle or observe (“strobe”) the value of the pin at a particular point in ular point in ular point in ular point in a clock cycle. Timing of input transitions and sampling of outpa clock cycle. Timing of input transitions and sampling of outpa clock cycle. Timing of input transitions and sampling of outpa clock cycle. Timing of input transitions and sampling of outputs is uts is uts is uts is controlled by a small (<< # of pins) number of highcontrolled by a small (<< # of pins) number of highcontrolled by a small (<< # of pins) number of highcontrolled by a small (<< # of pins) number of high----resolution timing generators. To increase the numberresolution timing generators. To increase the numberresolution timing generators. To increase the numberresolution timing generators. To increase the numberof possible input patterns, different data “formats” are provideof possible input patterns, different data “formats” are provideof possible input patterns, different data “formats” are provideof possible input patterns, different data “formats” are provided:d:d:d:


JMM v1.4

Test pattern generationTest pattern generationTest pattern generationTest pattern generation

� test generation is a time consuming tasktest generation is a time consuming tasktest generation is a time consuming tasktest generation is a time consuming task� computercomputercomputercomputer----aided test programs (CAT) help designer aided test programs (CAT) help designer aided test programs (CAT) help designer aided test programs (CAT) help designer

but do not solve test problemsbut do not solve test problemsbut do not solve test problemsbut do not solve test problems� approaches to manage test problem with increasing approaches to manage test problem with increasing approaches to manage test problem with increasing approaches to manage test problem with increasing

circuit complexity (research fields)circuit complexity (research fields)circuit complexity (research fields)circuit complexity (research fields)� design for testabilitydesign for testabilitydesign for testabilitydesign for testability� algorithms to generate good test vectorsalgorithms to generate good test vectorsalgorithms to generate good test vectorsalgorithms to generate good test vectors

design for testability: controllability, design for testability: controllability, design for testability: controllability, design for testability: controllability, observabilityobservabilityobservabilityobservability� system designer needs DFT knowledgesystem designer needs DFT knowledgesystem designer needs DFT knowledgesystem designer needs DFT knowledge

� adadadad----hoc approaches to augment controllability: hoc approaches to augment controllability: hoc approaches to augment controllability: hoc approaches to augment controllability: partitioning, more testpartitioning, more testpartitioning, more testpartitioning, more test----padspadspadspads

� structured methods, structured methods, structured methods, structured methods, multiplexermultiplexermultiplexermultiplexer approach, scanapproach, scanapproach, scanapproach, scan----path, path, path, path, builtbuiltbuiltbuilt----in logic block observation (BILBO), boundaryin logic block observation (BILBO), boundaryin logic block observation (BILBO), boundaryin logic block observation (BILBO), boundary----scan, scan, scan, scan, signature analysis, etc...signature analysis, etc...signature analysis, etc...signature analysis, etc...


JMM v1.4

Algorithms for test pattern Algorithms for test pattern Algorithms for test pattern Algorithms for test pattern generationgenerationgenerationgeneration

basic concepts for test generation for stuckbasic concepts for test generation for stuckbasic concepts for test generation for stuckbasic concepts for test generation for stuck----at fault at fault at fault at fault models in combinational circuitsmodels in combinational circuitsmodels in combinational circuitsmodels in combinational circuits� algebraic test generation: algebraic test generation: algebraic test generation: algebraic test generation: booleanbooleanbooleanboolean differencedifferencedifferencedifference� DDDD----algorithmalgorithmalgorithmalgorithm� PodemPodemPodemPodem and FAN algorithmsand FAN algorithmsand FAN algorithmsand FAN algorithms� controllability and controllability and controllability and controllability and observabilityobservabilityobservabilityobservability measuringmeasuringmeasuringmeasuring


JMM v1.4

Boolean differenceBoolean differenceBoolean differenceBoolean difference� algebraic method: algebraic method: algebraic method: algebraic method: booleanbooleanbooleanboolean differencedifferencedifferencedifference� circuits function with input vector circuits function with input vector circuits function with input vector circuits function with input vector x

� for for for for iiiithththth component of vector component of vector component of vector component of vector x with fix value we definewith fix value we definewith fix value we definewith fix value we define

� definition of definition of definition of definition of booleanbooleanbooleanboolean differencedifferencedifferencedifference

� circuit with fault circuit with fault circuit with fault circuit with fault α:α:α:α: stuckstuckstuckstuck----atatatat----1 at input 1 at input 1 at input 1 at input xxxxiiii

� to detect sto detect sto detect sto detect s----aaaa----1 faults the two functions 1 faults the two functions 1 faults the two functions 1 faults the two functions ffff((((x) and ) and ) and ) and ffffαααα(1) (1) (1) (1) must produce different results, so the test vector set is must produce different results, so the test vector set is must produce different results, so the test vector set is must produce different results, so the test vector set is defined by defined by defined by defined by TTTT=1=1=1=1

� for sfor sfor sfor s----aaaa----0 faults: 0 faults: 0 faults: 0 faults:

( ) ( )nxxfxf ...1=

( ) ( )niii xxxxff ...,,,,..., 111 11 +−=( ) ( )niii xxxxff ...,,,,..., 111 00 +−=

( ) ( ) ( )ninii

xxxfxxxfxxf ,...,,...,,...,,..., 11 ⊕=

∂∂

( ) ( ) ( )10 iii

ffxxf ⊕=

∂∂

( ) ( ) ( )11 111 αααααααα fxxxxfxf nii == +− ...,,,,...,

( ) ( )i

i xfxxfxfT

∂∂=⊕= αααα

( ) ( )i

ixfxxfxfT

∂∂=⊕= αααα


JMM v1.4

Boolean difference: RulesBoolean difference: RulesBoolean difference: RulesBoolean difference: Rules( ) ( )

ii xxf

xxf

∂∂=

∂∂ ( ) ( )

ii xxf

xxf

∂∂=

∂∂

( ) ( )ijji xxf

xxxf

x ∂∂⋅∂=

∂∂⋅∂

( ) ( )[ ] ( ) ( ) ( ) ( ) ( ) ( )iiiii xxg

xxf

xxfxg

xxgxf

xxgxf

∂∂

∂∂⊕

∂∂⊕

∂∂=

∂∂

( ) ( )[ ] ( ) ( ) ( ) ( ) ( ) ( )iiiii xxg

xxf

xxfxg

xxgxf

xxgxf

∂∂

∂∂⊕

∂∂⊕

∂∂=

∂+∂

( ) ( )[ ] ( ) ( )iii xxg

xxf

xxgxf

∂⊕

∂∂=

∂⊕∂

( ) ( )[ ] ( ) ( )[ ]ii xxgxf

xxgxf

∂⋅∂=

∂+∂

(((( )))) (((( ))))[[[[ ]]]] (((( )))) (((( ))))ii xxfxg

xxgxf

∂∂∂∂====

∂∂∂∂∂∂∂∂

(((( )))) (((( ))))[[[[ ]]]] (((( )))) (((( ))))ii xxfxg

xxgxf

∂∂∂∂====

∂∂∂∂++++∂∂∂∂

(((( ))))xg independent of independent of independent of independent of xxxxiiii


JMM v1.4

Boolean difference: exampleBoolean difference: exampleBoolean difference: exampleBoolean difference: example

Example Ex 20.1 (medium): Example Ex 20.1 (medium): Example Ex 20.1 (medium): Example Ex 20.1 (medium): circuit with stuckcircuit with stuckcircuit with stuckcircuit with stuck----atatatat----1 1 1 1 fault at fault at fault at fault at xxxx3333. Find all test patterns which detect the . Find all test patterns which detect the . Find all test patterns which detect the . Find all test patterns which detect the the fault with means of the the fault with means of the the fault with means of the the fault with means of the booleanbooleanbooleanboolean difference.difference.difference.difference.

≥ 1

G1

≥ 1

G5

G3

&

G4

&

x1

x2

x3

x4

y

s1

s2

s3

G2


JMM v1.4

Test generation: DTest generation: DTest generation: DTest generation: D----algorithmalgorithmalgorithmalgorithm

Basics:Basics:Basics:Basics:� fault fault fault fault sensitisationsensitisationsensitisationsensitisation (provoke error)(provoke error)(provoke error)(provoke error)� fault propagationfault propagationfault propagationfault propagation� line justification line justification line justification line justification

� DDDD----notationnotationnotationnotation� a signal with value D is fault free if D = 1a signal with value D is fault free if D = 1a signal with value D is fault free if D = 1a signal with value D is fault free if D = 1� a signal with value D is faulty if D=0a signal with value D is faulty if D=0a signal with value D is faulty if D=0a signal with value D is faulty if D=0� a signal with value D is fault free if D = 0a signal with value D is fault free if D = 0a signal with value D is fault free if D = 0a signal with value D is fault free if D = 0� a signal with value D is faulty if D=1a signal with value D is faulty if D=1a signal with value D is faulty if D=1a signal with value D is faulty if D=1

� very formal table manipulation procedurevery formal table manipulation procedurevery formal table manipulation procedurevery formal table manipulation procedure� advantage:advantage:advantage:advantage:

� if test vector exists it will be foundif test vector exists it will be foundif test vector exists it will be foundif test vector exists it will be found� programmable for computersprogrammable for computersprogrammable for computersprogrammable for computers

� disadvantage:disadvantage:disadvantage:disadvantage:� conflicts lead to time consuming dummy calculationsconflicts lead to time consuming dummy calculationsconflicts lead to time consuming dummy calculationsconflicts lead to time consuming dummy calculations� not usable for large circuitsnot usable for large circuitsnot usable for large circuitsnot usable for large circuits


JMM v1.4

≥ 1

G1

≥ 1

G5

G3

&

G4

&

x1

x2

x3

x4

y

s1

s2

s3

G2

Test generation: Test generation: Test generation: Test generation: Path Path Path Path sensitisationsensitisationsensitisationsensitisation

Example Ex20.2 (easy):Example Ex20.2 (easy):Example Ex20.2 (easy):Example Ex20.2 (easy): circuit with stuckcircuit with stuckcircuit with stuckcircuit with stuck----atatatat----1 fault 1 fault 1 fault 1 fault at at at at xxxx3333. Find test vectors with means of D. Find test vectors with means of D. Find test vectors with means of D. Find test vectors with means of D----algorithmalgorithmalgorithmalgorithm� sensitization:sensitization:sensitization:sensitization:� fault propagation:fault propagation:fault propagation:fault propagation:� line justificationline justificationline justificationline justification

Step 1: Step 1: Step 1: Step 1: Sensitize circuitSensitize circuitSensitize circuitSensitize circuit. Find input values that . Find input values that . Find input values that . Find input values that produce a value on the faulty node that’s different produce a value on the faulty node that’s different produce a value on the faulty node that’s different produce a value on the faulty node that’s different from the value forced by the fault. For our Sfrom the value forced by the fault. For our Sfrom the value forced by the fault. For our Sfrom the value forced by the fault. For our S----AAAA----1 1 1 1 fault above, want output of AND gate to be 0.fault above, want output of AND gate to be 0.fault above, want output of AND gate to be 0.fault above, want output of AND gate to be 0.� Is this always possible? What would it mean if no such Is this always possible? What would it mean if no such Is this always possible? What would it mean if no such Is this always possible? What would it mean if no such

input values exist?input values exist?input values exist?input values exist?� Is the set of sensitizing input values unique? If not, Is the set of sensitizing input values unique? If not, Is the set of sensitizing input values unique? If not, Is the set of sensitizing input values unique? If not,

which should one choose?which should one choose?which should one choose?which should one choose?� What’s left to do?What’s left to do?What’s left to do?What’s left to do?

SSSS----AAAA----1111XXXX


JMM v1.4

≥ 1

G1

≥ 1

G5

G3

&

G4

&

x1

x2

x3

x4

y

s1

s2

s3

G2

Test generation: Fault propagationTest generation: Fault propagationTest generation: Fault propagationTest generation: Fault propagation

� sensitization:sensitization:sensitization:sensitization:� fault propagation:fault propagation:fault propagation:fault propagation:� line justificationline justificationline justificationline justification

Step 2: Step 2: Step 2: Step 2: Fault propagationFault propagationFault propagationFault propagation. Select a path that . Select a path that . Select a path that . Select a path that propagates the faulty value to an observed output (y propagates the faulty value to an observed output (y propagates the faulty value to an observed output (y propagates the faulty value to an observed output (y in our example).in our example).in our example).in our example).

SSSS----AAAA----1111

XXXX


JMM v1.4

≥ 1

G1

≥ 1

G5

G3

&

G4

&

x1

x2

x3

x4

y

s1

s2

s3

G2

Test generation: Line justificationTest generation: Line justificationTest generation: Line justificationTest generation: Line justification

� sensitization:sensitization:sensitization:sensitization:� fault propagation:fault propagation:fault propagation:fault propagation:� line justificationline justificationline justificationline justification

Step 3: Step 3: Step 3: Step 3: Line justificationLine justificationLine justificationLine justification. Find a set of input . Find a set of input . Find a set of input . Find a set of input values that enables the selected path values that enables the selected path values that enables the selected path values that enables the selected path (backtracking).(backtracking).(backtracking).(backtracking).� Is this always possible? What would it mean if no such Is this always possible? What would it mean if no such Is this always possible? What would it mean if no such Is this always possible? What would it mean if no such

input values exist?input values exist?input values exist?input values exist?� Is the set of enabling input values unique? Is the set of enabling input values unique? Is the set of enabling input values unique? Is the set of enabling input values unique?

If not, which should one choose?If not, which should one choose?If not, which should one choose?If not, which should one choose?

SSSS----AAAA----1111

XXXX


JMM v1.4

Test generation: PTest generation: PTest generation: PTest generation: PODEM, FANODEM, FANODEM, FANODEM, FAN

� more recent algorithms like more recent algorithms like more recent algorithms like more recent algorithms like PodemPodemPodemPodem, FAN or others , FAN or others , FAN or others , FAN or others basically intend to prevent conflict situations or to basically intend to prevent conflict situations or to basically intend to prevent conflict situations or to basically intend to prevent conflict situations or to detect them as early as possibledetect them as early as possibledetect them as early as possibledetect them as early as possible� concept: concept: concept: concept:

� take decisions as late as possible (prevent wrong take decisions as late as possible (prevent wrong take decisions as late as possible (prevent wrong take decisions as late as possible (prevent wrong decisions, perhaps there is later nothing to decide)decisions, perhaps there is later nothing to decide)decisions, perhaps there is later nothing to decide)decisions, perhaps there is later nothing to decide)

� heuristics help to take decisions which succeed with heuristics help to take decisions which succeed with heuristics help to take decisions which succeed with heuristics help to take decisions which succeed with higher probabilityhigher probabilityhigher probabilityhigher probability

�controllability and controllability and controllability and controllability and observabilityobservabilityobservabilityobservability measuring measuring measuring measuring necessarynecessarynecessarynecessary


JMM v1.4

PODEMPODEMPODEMPODEM

� PodemPodemPodemPodem algorithm is simpler to understand than Dalgorithm is simpler to understand than Dalgorithm is simpler to understand than Dalgorithm is simpler to understand than D----algorithmalgorithmalgorithmalgorithm� backtrack (branchbacktrack (branchbacktrack (branchbacktrack (branch----andandandand----bound) algorithm is usedbound) algorithm is usedbound) algorithm is usedbound) algorithm is used

� small steps to reach objectivesmall steps to reach objectivesmall steps to reach objectivesmall steps to reach objective� if objective leads to deadif objective leads to deadif objective leads to deadif objective leads to dead----end, go backend, go backend, go backend, go back

� backtrack (branchbacktrack (branchbacktrack (branchbacktrack (branch----andandandand----bound) in bound) in bound) in bound) in PodemPodemPodemPodem::::� all signals are initialised to "X"all signals are initialised to "X"all signals are initialised to "X"all signals are initialised to "X"� fault sensitisation fault sensitisation fault sensitisation fault sensitisation � during fault propagation D symbols are propagated only during fault propagation D symbols are propagated only during fault propagation D symbols are propagated only during fault propagation D symbols are propagated only

one step to primary outputs (branch)one step to primary outputs (branch)one step to primary outputs (branch)one step to primary outputs (branch)� immediate line justification of selected signal to primary immediate line justification of selected signal to primary immediate line justification of selected signal to primary immediate line justification of selected signal to primary

inputs (new input with value corresponds branch of inputs (new input with value corresponds branch of inputs (new input with value corresponds branch of inputs (new input with value corresponds branch of decision tree)decision tree)decision tree)decision tree)

� succeeding fault simulation immediately detects conflict succeeding fault simulation immediately detects conflict succeeding fault simulation immediately detects conflict succeeding fault simulation immediately detects conflict situations (bound)situations (bound)situations (bound)situations (bound)

� new branchnew branchnew branchnew branch


JMM v1.4

PODEM: ExamplePODEM: ExamplePODEM: ExamplePODEM: Example

� branchbranchbranchbranch----andandandand----bound treebound treebound treebound tree� nodes represent decisionsnodes represent decisionsnodes represent decisionsnodes represent decisions� branches represent PI'sbranches represent PI'sbranches represent PI'sbranches represent PI's� represent 1st decision faultyrepresent 1st decision faultyrepresent 1st decision faultyrepresent 1st decision faulty� example example example example xxxx1111 stuckstuckstuckstuck----atatatat----1111

start

x1=0

x2=1

≥ 1

G1

≥ 1

G5

G3

&

G4

&

x1

x2

x3

x4

y

s1

s2

s3

G2


JMM v1.4

TesTesTesTest pattern generation: Heuristicst pattern generation: Heuristicst pattern generation: Heuristicst pattern generation: Heuristics

Heuristics in FAN algorithmHeuristics in FAN algorithmHeuristics in FAN algorithmHeuristics in FAN algorithm� fault propagationfault propagationfault propagationfault propagation

� propagate to PO on path which is best observablepropagate to PO on path which is best observablepropagate to PO on path which is best observablepropagate to PO on path which is best observable

� line justificationline justificationline justificationline justification� start with the most difficult path to controlstart with the most difficult path to controlstart with the most difficult path to controlstart with the most difficult path to control

� heuristics help to find test vectors fasterheuristics help to find test vectors fasterheuristics help to find test vectors fasterheuristics help to find test vectors faster


JMM v1.4

Controllability and Controllability and Controllability and Controllability and observabilityobservabilityobservabilityobservabilitymeasuremeasuremeasuremeasure

� often used to solve often used to solve often used to solve often used to solve npnpnpnp----complete problemscomplete problemscomplete problemscomplete problems� heuristics do not guarantee to find a solution in a heuristics do not guarantee to find a solution in a heuristics do not guarantee to find a solution in a heuristics do not guarantee to find a solution in a

given timegiven timegiven timegiven time� testability measure methods:testability measure methods:testability measure methods:testability measure methods:

� temastemastemastemas, , , , testscreentestscreentestscreentestscreen, victor, , victor, , victor, , victor, camelotcamelotcamelotcamelot, , , , scoapscoapscoapscoap

� sandiasandiasandiasandia controllability/controllability/controllability/controllability/observabilityobservabilityobservabilityobservability analysis analysis analysis analysis program (program (program (program (scoapscoapscoapscoap))))� each node in a circuit gets values for its each node in a circuit gets values for its each node in a circuit gets values for its each node in a circuit gets values for its

controllability, controllability, controllability, controllability, observabilityobservabilityobservabilityobservability and testabilityand testabilityand testabilityand testability� high values indicate nodes which are hard to control high values indicate nodes which are hard to control high values indicate nodes which are hard to control high values indicate nodes which are hard to control

or to observeor to observeor to observeor to observe� distinguish between "1" and "0" controllabilitydistinguish between "1" and "0" controllabilitydistinguish between "1" and "0" controllabilitydistinguish between "1" and "0" controllability� distinguish between combinational and sequential distinguish between combinational and sequential distinguish between combinational and sequential distinguish between combinational and sequential

valuesvaluesvaluesvalues


JMM v1.4

ObservabilityObservabilityObservabilityObservability & Controllability& Controllability& Controllability& ControllabilityWhen propagating faulty values to observed outputs we are often When propagating faulty values to observed outputs we are often When propagating faulty values to observed outputs we are often When propagating faulty values to observed outputs we are often faced faced faced faced with several choices for which should be the next gate in our pawith several choices for which should be the next gate in our pawith several choices for which should be the next gate in our pawith several choices for which should be the next gate in our path.th.th.th.

XXXX????

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We’d like to have a way to measure the We’d like to have a way to measure the We’d like to have a way to measure the We’d like to have a way to measure the observabilityobservabilityobservabilityobservability of a node, i.e., of a node, i.e., of a node, i.e., of a node, i.e., some indication of how hard it is to observe the node at the outsome indication of how hard it is to observe the node at the outsome indication of how hard it is to observe the node at the outsome indication of how hard it is to observe the node at the outputs of puts of puts of puts of the chip. During fault propagation we could choose the gate whothe chip. During fault propagation we could choose the gate whothe chip. During fault propagation we could choose the gate whothe chip. During fault propagation we could choose the gate whose se se se output was easiest to observe.output was easiest to observe.output was easiest to observe.output was easiest to observe.

Similarly, during backtracking we need a way to choose between Similarly, during backtracking we need a way to choose between Similarly, during backtracking we need a way to choose between Similarly, during backtracking we need a way to choose between alternative ways of forcing a particular value:alternative ways of forcing a particular value:alternative ways of forcing a particular value:alternative ways of forcing a particular value:

want 0 herewant 0 herewant 0 herewant 0 herewhich input shouldwhich input shouldwhich input shouldwhich input shouldwe try to set to 0?we try to set to 0?we try to set to 0?we try to set to 0?

In this case, we’d like to have a way to measure theIn this case, we’d like to have a way to measure theIn this case, we’d like to have a way to measure theIn this case, we’d like to have a way to measure thecontrollabilitycontrollabilitycontrollabilitycontrollability of a node, i.e., some indication of howof a node, i.e., some indication of howof a node, i.e., some indication of howof a node, i.e., some indication of howeasy it is to force the node to 0 or 1. Duringeasy it is to force the node to 0 or 1. Duringeasy it is to force the node to 0 or 1. Duringeasy it is to force the node to 0 or 1. Duringbacktracking we could choose the input that wasbacktracking we could choose the input that wasbacktracking we could choose the input that wasbacktracking we could choose the input that waseasiest to control.easiest to control.easiest to control.easiest to control.


JMM v1.4

Testability measurement:Testability measurement:Testability measurement:Testability measurement:ScoaScoaScoaScoapppp algorithmalgorithmalgorithmalgorithm

� combinational "1" and "0" controllability of a logic gate combinational "1" and "0" controllability of a logic gate combinational "1" and "0" controllability of a logic gate combinational "1" and "0" controllability of a logic gate output output output output yyyy dependent on inputs dependent on inputs dependent on inputs dependent on inputs xxxx1111........xxxx3333

OR gate:OR gate:OR gate:OR gate:

AND gate:AND gate:AND gate:AND gate:

� combinational "1" and "0" combinational "1" and "0" combinational "1" and "0" combinational "1" and "0" observabilityobservabilityobservabilityobservability of a logic gate of a logic gate of a logic gate of a logic gate dependent on output dependent on output dependent on output dependent on output yyyy and inputs and inputs and inputs and inputs xxxx2,2,2,2,xxxx3333

OR gate:OR gate:OR gate:OR gate:

AND gate:AND gate:AND gate:AND gate:

initialization (initialization (initialization (initialization (NNNN are internal nodes, are internal nodes, are internal nodes, are internal nodes, X,YX,YX,YX,Y are PI, PO's)are PI, PO's)are PI, PO's)are PI, PO's)

( ) ( ) ( ) ( ) 130

20

100 +++= xCCxCCxCCyCC

( ) ( ) ( ) ( ){ } 131

21

111 += xCCxCCxCCyCC ,,min

( ) ( ) ( ) ( ){ } 130

20

100 += xCCxCCxCCyCC ,,min

( ) ( ) ( ) ( ) 131

21

111 +++= xCCxCCxCCyCC

( ) ( ) ( ) ( ) 130

20

1 +++= xCCxCCyCOxCO

( ) ( ) ( ) ( ) 131

21

1 +++= xCCxCCyCOxCO

( ) 10 =XCC( ) 11 =XCC

( ) ∞=NCC 0

( ) ∞=NCC 1( ) 0=YCO( ) ∞=NCO


JMM v1.4

Testability measurement:Testability measurement:Testability measurement:Testability measurement:ScoapScoapScoapScoap algorithm (con‘talgorithm (con‘talgorithm (con‘talgorithm (con‘t))))

1,1,1,1,1,1,1,1,----1,1,1,1,1,1,1,1,----

1,1,1,1,1,1,1,1,----1,1,1,1,1,1,1,1,----

1,1,1,1,1,1,1,1,----1,1,1,1,1,1,1,1,----

1,1,1,1,1,1,1,1,----

----....----.0.0.0.0

----....----.0.0.0.0

CC0,CC1,COCC0,CC1,COCC0,CC1,COCC0,CC1,CO

hmmm. I guesshmmm. I guesshmmm. I guesshmmm. I guesssmaller numberssmaller numberssmaller numberssmaller numbersare better...are better...are better...are better...

AAAABBBB ZZZZ

CCCCCCCC0000(Z) = min[CC(Z) = min[CC(Z) = min[CC(Z) = min[CC0000(A), CC(A), CC(A), CC(A), CC0000(B)] + 1(B)] + 1(B)] + 1(B)] + 1CCCCCCCC1111(Z) = CC(Z) = CC(Z) = CC(Z) = CC1111(A) + CC(A) + CC(A) + CC(A) + CC1111(B) + 1(B) + 1(B) + 1(B) + 1CO(A) = CO(Z) + CCCO(A) = CO(Z) + CCCO(A) = CO(Z) + CCCO(A) = CO(Z) + CC1111(B) + 1(B) + 1(B) + 1(B) + 1CO(B) = CO(Z) + CCCO(B) = CO(Z) + CCCO(B) = CO(Z) + CCCO(B) = CO(Z) + CC1111(A) + 1(A) + 1(A) + 1(A) + 1

AAAABBBB ZZZZ

CCCCCCCC0000(Z) = CC(Z) = CC(Z) = CC(Z) = CC0000(A) + CC(A) + CC(A) + CC(A) + CC0000(B) + 1(B) + 1(B) + 1(B) + 1CCCCCCCC1111(Z) = min[CC(Z) = min[CC(Z) = min[CC(Z) = min[CC1111(A), CC(A), CC(A), CC(A), CC1111(B)] + 1(B)] + 1(B)] + 1(B)] + 1CO(A) = CO(Z) + CCCO(A) = CO(Z) + CCCO(A) = CO(Z) + CCCO(A) = CO(Z) + CC0000(B) + 1(B) + 1(B) + 1(B) + 1CO(B) = CO(Z) + CCCO(B) = CO(Z) + CCCO(B) = CO(Z) + CCCO(B) = CO(Z) + CC0000(A) + 1(A) + 1(A) + 1(A) + 1

““““testability” measure assumes that the further a nodetestability” measure assumes that the further a nodetestability” measure assumes that the further a nodetestability” measure assumes that the further a nodeis from an input/output the harder it is to set/observe is from an input/output the harder it is to set/observe is from an input/output the harder it is to set/observe is from an input/output the harder it is to set/observe

if more than one, choose minif more than one, choose minif more than one, choose minif more than one, choose min


JMM v1.4

Fault simulationFault simulationFault simulationFault simulation

goals of fault simulation:goals of fault simulation:goals of fault simulation:goals of fault simulation:� analyze circuit under faults conditionanalyze circuit under faults conditionanalyze circuit under faults conditionanalyze circuit under faults condition� qualify test sequence, fault coveragequalify test sequence, fault coveragequalify test sequence, fault coveragequalify test sequence, fault coverage� reduce fault set during test generationreduce fault set during test generationreduce fault set during test generationreduce fault set during test generation�good quality fault models necessarygood quality fault models necessarygood quality fault models necessarygood quality fault models necessary

fault simulation methodsfault simulation methodsfault simulation methodsfault simulation methods� parallel fault simulationparallel fault simulationparallel fault simulationparallel fault simulation� concurrent fault simulationconcurrent fault simulationconcurrent fault simulationconcurrent fault simulation� deductive fault simulationdeductive fault simulationdeductive fault simulationdeductive fault simulation

� alternative to fault simulation in test generation alternative to fault simulation in test generation alternative to fault simulation in test generation alternative to fault simulation in test generation procedures:procedures:procedures:procedures:� tracing fault sensitive pathstracing fault sensitive pathstracing fault sensitive pathstracing fault sensitive paths


JMM v1.4

Fault simulation (con‘t)Fault simulation (con‘t)Fault simulation (con‘t)Fault simulation (con‘t)

� parallel fault simulationparallel fault simulationparallel fault simulationparallel fault simulation� principle: computing with 1principle: computing with 1principle: computing with 1principle: computing with 1----bit or bit or bit or bit or nnnn----bit wide bit wide bit wide bit wide

variables need similar computing timevariables need similar computing timevariables need similar computing timevariables need similar computing time� test of ntest of ntest of ntest of n----1 faults at the same time1 faults at the same time1 faults at the same time1 faults at the same time

C'=[01110]MA

A'=[01000]A=[00000]

C=[01100]

MB

B'=[00100]B=[00000]MC

≥ 1

bitposition fault1 fault free2 A s-a-13 B s-a-14 C s-a-15 C s-a-0

mask fault valuesMA=[01000] [01000]MB=[00100] [00100]MC=[00011] [00010]


JMM v1.4

Fault GradingFault GradingFault GradingFault GradingSo, you’ve constructed a set of test vectorsSo, you’ve constructed a set of test vectorsSo, you’ve constructed a set of test vectorsSo, you’ve constructed a set of test vectorsusing the techniques described here. Willusing the techniques described here. Willusing the techniques described here. Willusing the techniques described here. Willthey detect all the faulty parts?they detect all the faulty parts?they detect all the faulty parts?they detect all the faulty parts?

�� You could see how many different faultsYou could see how many different faultsYou could see how many different faultsYou could see how many different faultsyour vectors detect by inserting eachyour vectors detect by inserting eachyour vectors detect by inserting eachyour vectors detect by inserting eachpossible fault one at a time, running thepossible fault one at a time, running thepossible fault one at a time, running thepossible fault one at a time, running thevectors, then check to see if some outputvectors, then check to see if some outputvectors, then check to see if some outputvectors, then check to see if some outputwas different from the “good” machine onwas different from the “good” machine onwas different from the “good” machine onwas different from the “good” machine onsome cycle. Need some cycle. Need some cycle. Need some cycle. Need *lots**lots**lots**lots* of simulation…of simulation…of simulation…of simulation…probably impractical for large circuits evenprobably impractical for large circuits evenprobably impractical for large circuits evenprobably impractical for large circuits evenwith hardwarewith hardwarewith hardwarewith hardware----accelerated simulator.accelerated simulator.accelerated simulator.accelerated simulator.

�� You can use the same sorts of statisticalYou can use the same sorts of statisticalYou can use the same sorts of statisticalYou can use the same sorts of statisticalsampling techniques that other QAsampling techniques that other QAsampling techniques that other QAsampling techniques that other QAprograms employ: programs employ: programs employ: programs employ: randomlyrandomlyrandomlyrandomly select a setselect a setselect a setselect a setof faults, fault grade your vectors onof faults, fault grade your vectors onof faults, fault grade your vectors onof faults, fault grade your vectors onthose faults and use standard statisticalthose faults and use standard statisticalthose faults and use standard statisticalthose faults and use standard statisticaltechniques to see if fault coverage exceedstechniques to see if fault coverage exceedstechniques to see if fault coverage exceedstechniques to see if fault coverage exceedsa desired level. The level of confidence maya desired level. The level of confidence maya desired level. The level of confidence maya desired level. The level of confidence maybe increased by increasing the number ofbe increased by increasing the number ofbe increased by increasing the number ofbe increased by increasing the number ofsamples.samples.samples.samples.


JMM v1.4

ConclusionConclusionConclusionConclusion

� defects during chip fabrication are inevitabledefects during chip fabrication are inevitabledefects during chip fabrication are inevitabledefects during chip fabrication are inevitable� faults model defects on higher abstraction levelsfaults model defects on higher abstraction levelsfaults model defects on higher abstraction levelsfaults model defects on higher abstraction levels� higher chip complexity, more gates and less pads higher chip complexity, more gates and less pads higher chip complexity, more gates and less pads higher chip complexity, more gates and less pads

reduce controllability, reduce controllability, reduce controllability, reduce controllability, observabilityobservabilityobservabilityobservability and thus and thus and thus and thus testabilitytestabilitytestabilitytestability� test pattern generation is going to be time test pattern generation is going to be time test pattern generation is going to be time test pattern generation is going to be time

consuming and thus costlyconsuming and thus costlyconsuming and thus costlyconsuming and thus costly� structured design for test during chip development structured design for test during chip development structured design for test during chip development structured design for test during chip development

is requiredis requiredis requiredis required


JMM v1.4

Coming Up...Coming Up...Coming Up...Coming Up...

� Next topic…Next topic…Next topic…Next topic… Design for TestabilityDesign for TestabilityDesign for TestabilityDesign for Testability

Readings for next time…Readings for next time…Readings for next time…Readings for next time…WWWWesteesteesteeste: : : :

� Sections 7.2.2 thru 7.2.5Sections 7.2.2 thru 7.2.5Sections 7.2.2 thru 7.2.5Sections 7.2.2 thru 7.2.5


JMM v1.4

Exercises: VLSIExercises: VLSIExercises: VLSIExercises: VLSI----20 #120 #120 #120 #1

� Ex vlsi20.3 (difficulty: medium):Ex vlsi20.3 (difficulty: medium):Ex vlsi20.3 (difficulty: medium):Ex vlsi20.3 (difficulty: medium): The digital circuit The digital circuit The digital circuit The digital circuit suffers from error suffers from error suffers from error suffers from error αααα ssss----aaaa----0. Try to find test patterns 0. Try to find test patterns 0. Try to find test patterns 0. Try to find test patterns by means of Dby means of Dby means of Dby means of D----algorithm. If you don‘t succeed use algorithm. If you don‘t succeed use algorithm. If you don‘t succeed use algorithm. If you don‘t succeed use the the the the booleanbooleanbooleanboolean difference to calculate the test patterns.difference to calculate the test patterns.difference to calculate the test patterns.difference to calculate the test patterns. Result: T=xResult: T=xResult: T=xResult: T=x1111 xxxx2222 xxxx3333 xxxx4444 found by found by found by found by booleanbooleanbooleanboolean differencedifferencedifferencedifference

G6

G3

&

G4&

x3

x2

x1

x4

y

G2

&

G5&

G1&

α

&


JMM v1.4

≥ 1

G1

≥ 1

G5

G3

&

G4

&

x1

x2

x3

x4

y

s1

s2

s3&

Exercises: VLSIExercises: VLSIExercises: VLSIExercises: VLSI----20 #220 #220 #220 #2

� Ex vlsi20.4 (difficulty: easy):Ex vlsi20.4 (difficulty: easy):Ex vlsi20.4 (difficulty: easy):Ex vlsi20.4 (difficulty: easy): Calculate the Calculate the Calculate the Calculate the ScoapScoapScoapScoapcombinational controllability and combinational controllability and combinational controllability and combinational controllability and observabilityobservabilityobservabilityobservability values values values values for the circuit below (CC0,CC1,CO)for the circuit below (CC0,CC1,CO)for the circuit below (CC0,CC1,CO)for the circuit below (CC0,CC1,CO) Result: xResult: xResult: xResult: x1111 (1,1,7), x(1,1,7), x(1,1,7), x(1,1,7), x2222 (1,1,7), x(1,1,7), x(1,1,7), x(1,1,7), x3333 (1,1,5), x(1,1,5), x(1,1,5), x(1,1,5), x4 4 4 4 (1,1,5), s(1,1,5), s(1,1,5), s(1,1,5), s1111

(3,2,5), s(3,2,5), s(3,2,5), s(3,2,5), s2222 (2,4,3), s(2,4,3), s(2,4,3), s(2,4,3), s3333 (2,3,3), y (4,5,0)(2,3,3), y (4,5,0)(2,3,3), y (4,5,0)(2,3,3), y (4,5,0)

� Ex vlsi20.5 (difficulty: easy):Ex vlsi20.5 (difficulty: easy):Ex vlsi20.5 (difficulty: easy):Ex vlsi20.5 (difficulty: easy): a) circuit with stucka) circuit with stucka) circuit with stucka) circuit with stuck----atatatat----0 fault at 0 fault at 0 fault at 0 fault at ssss1111. b) circuit with stuck. b) circuit with stuck. b) circuit with stuck. b) circuit with stuck----atatatat----0 fault at 0 fault at 0 fault at 0 fault at xxxx1111. . . . Find all test patterns which detect the the fault Find all test patterns which detect the the fault Find all test patterns which detect the the fault Find all test patterns which detect the the fault with means of the with means of the with means of the with means of the booleanbooleanbooleanboolean difference.difference.difference.difference. Result equations a) x=(xResult equations a) x=(xResult equations a) x=(xResult equations a) x=(x1111+x+x+x+x2222)x)x)x)x3333, b) x=x, b) x=x, b) x=x, b) x=x1111xxxx2222xxxx3333

vlsi design i - bfh · pdf filecomputer-computer--aided test programs (cat) ... design for...

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