vlsi design quiz paper

Code No: 05320402 Set No. 1

JAWAHARLAL NEHRU TECNOLOGICAL UNIVERSITY, HYDRABAD

III B.Tech II Sem. II Mid-Term Objective Examinations, Feb. – 2009

VLSI Design Name: ____________________________ HallTicket No. _____________________

Answer All Questions.All Questions Carry Equal Marks. Time: 20 Min. Marks: 20. I. Choose the correct alternative:

1. The approximate number of transistors per VLSI chip in commercial products

[ ] 1.100-1000 2. 1000-20,000 3. 20,000-1,000,000 4. 1,000,000-10,000,000

2. To achieve low threshold voltage in the p-well CMOS fabrication [ ]

1. Deep well diffusion or low well resistivity 2. Deep well diffusion or high well resistivity 3. Lower substrate bias and higher parasitic capacitances 4. Higher substrate bias and higher parasitic capacitances

3. The transit time of electrons will flow from source to drain is [ ]

1. dsLV

µ 2. LVdsµ

3. dsV

Lµ

2

4. µ

dsVL2

4. The threshold voltage Vt may be expressed as [ ]

1. fNB

ms CQ

φφ 20

+ 2. fNSSB

ms CQQ

φφ 20

+−

4. )2(2 0 SBfNSi VqN +φεε 4. )2(2 0 fNSiqN φεε 5. The input and output impedances for BiCMOS inverter is [ ]

1. Both are high 2. Both are low 3. High and low 4.Low and high 6. The minimum separation between two metal-1 contacts in λ based design rules is [ ]

1. 1 λ 2. 2 λ 3. 3 4. 4λ 7. The following is used for local distribution of power [ ]

1. First level metal 2. Second level metal 3. Butting contact 4. Buried contact 8. The gate delay is scaled by [ ]

1. 1/ β 2. β/α2 3. 1/α 4. βα

Cont….2 : 2 :


9. One of the following is used to drive large capacitive loads [ ] 1. N cascaded inverters 2. Small size inverter

3. High Zp.d and Zp.u 4. Small L:W 10. For a given area, the metal to polysilicon capacitance is compared to metal to substrate

[ ] 1. Lower 2.Higher 3.Same 4. Half

II Fill in the blanks: 1. The thickness of silicon dioxide layer is ________________ 2. To increase the gm of a MOS device by __________ its width 3. The establishment of low resistance conducting paths between VDD and VSS due

to the parasitic capacitance is called _______________ 4. ______________ is to guarantee that under the worst cumulative variations of the

processes, the circuit does not fail to operate 5. The problem of driving comparatively large capacitive loads arises when signals

must be propagated from the ------ III True (or) False Statements:

6. BiCMOS technology is most popularly used for I/O and driver circuits 7. Charge induced in channel due to gate voltage is due to the voltage difference between the drain and source 8. The threshold voltage for the nMOS depletion mode device is positive 9. In order to prevent punch-through and maintain transistor action, the length of channel must be at least twice that of depletion width 10. For line metallization, the value of fringing field capacitance can be of the same order as

that of the area capacitance

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1. The common measure of effectiveness of VLSI chip is [ ]

1. Propagation delay 2. Speed power product 3. Gain bandwidth product 4. Power dissipation

2. The advantages of Bipolar technology compared to MOS technology is [ ]

1. Low static power dissipation 2. High input impedance 3. Low drive current 4. Higher gain

3. The expression for drain to source current in non-saturated region for

enhancement MOS device is [ ]

1. 2

)( 2tgs VV

K−

2.2

)( 2tgs VV

LWK

−

3. 2

)( 2tgs VV −

4. ⎟⎟⎠

⎞⎜⎜⎝

⎛−−

2)(

2ds

dstgsV

VVVLWK

4. The charge per unit area in the depletion layer beneath the oxide QB is [ ]

1. fNB

ms CQ

φφ 20

+ 2. fNSSB

ms CQQ

φφ 20

+−

3. )2(2 0 SBfNSi VqN +φεε 4. )2(2 0 fNSiqN φεε 5. The following are remedies for the latch-up problem for CMOS circuits except [ ]

1. High contact resistance to VSS 2. An increase in substrate doping levels 3. A reduction of substrate resistance 3. Introduction of guard rings

6. The minimum separation between two metal-2 contact layers in λ based design

rules is [ ] 1. 1 λ 2. 2 λ 3. 3 4. 4λ

7. The Buried contact is used to [ ]

1. Connect polysilicon to diffusion 2. Metal1 to metal 2 3. Connect VDD 4. Connect ground

Cont….2

: 2 :

Code No: 05320402 Set No. 2 8. The gate capacitance per unit area is called by [ ]

1. 1/β 2. β 3.1/α 4. α 9. The channel resistance of a simple n-type pass transistor has a channel length 2λ

and width 2 λ is [ ] 1. 104 ohm 2. 4 ohm 3.1 ohm 4.4 λ ohm

10. VDD and VSS should be distributed on [ ]

1. Diffusion layer 2. Metal layer 3. Polysilicon layer 4. Silicide layer II Fill in the balnsk: 11. The threshold voltage for depletion mode transistor is ______________ 12. A reduction in the channel length in MOS transistor results in an increase in _________ 13. The BiCMOS inverter has a high current drive capability but occupies____________area 14. __________ is used to convey layer information through the use of a colour code. 15. The inverter pair delay for invertr having 4:1 ratio is ____________ III True (or) False Statements: 16. In the CMOS fabrication p-well process requires lower temperature for

diffusion process than n-well process 17. The threshold voltage needed to invert the charge under the gate and establish the

channel 18. The Pass Transistors are Switching Logic Arrays 19. The diffusion paths can cross the demarcation line 20. The offchip load capacitance must be driven through high resistances

-oOo-





1. In nMOS fabrication, the UV radiation is used for [ ]

1. Etching 2. Polymerization 3. Chemical vapor deposition 4. Self aligning 2. The buried n+ sub collector is added to the n-well CMOS transistor to provide [ ]

1. Emitter region 2. Reduce the output drive current 3. Reduce the n-well collector resistance 4. Base region

3. The gate/channel capacitance for parallel plates is [ ]

1.LD

Woinsεε 2.

DWL

oinsεε 3. oinsεε 4.

DWLoinsεε

4. Dissipation for nMos depletion mode transistor pull-up is high since [ ] 1. Rail to rail current flows when Vin is equal to logical one 2. Switching of output from 0 to 1 begins when Vin exceeds Vt of p.d device 3. Switching of output from 0 to 1 begins when Vin exceeds Vt of p.u device is non-saturated 4. Large space requirements of resistors produced

5. In general BiCMOS inverters offer many advantages but they require [ ]

1. High substrate resistance 2. High load current sinking and sourcing 3. High n-well resistance 4. Low holding current

6. The following all are possible approaches for making contacts between

polysilicon and diffusion in NMOS circuit except [ ] 1. Polysilicon to metal then metal to diffusion 2. Buried contact polysilicon to diffusion 3.Butting contacts 4. Cross contacts

7. The minimum feature size on chip, if λ can be allocated a value of 1µm is [ ]

1. 0.5µm 2.1µm 3. 2µm 4. 4µm 8. For constant field model and constant voltage model the value of β applied is b [ ]

1. 1 and α respectively 2. α and 1 respectively 3. 1 and 0 respectively 4. 0 and 1 respectively

Cont….2

: 2 :

Code No: 05320402 Set No. 3 9. The delay unit for 2µm technology is [ ]

1. 0.1nsec 2. 0.05nsec 3. 0.064nsec 4. 0.046nsec 10. The layer used to speed up the rise time of propagated signal edges is [ ]

1. Diffusion layer 2. Metal layer 3. Polysilicon layer 4. Silicide layer II Fill in the blanks: 11. _________________ type of gate voltage is applied to establish channel between source

and drain of enhancement mode MOS transistor 12. The Maximum voltage across the enhancement mode device corresponds to

_____________ voltage across the depletion mode transistor 13. Zp.u./Zp.d. for an inverter directly driven by an inverter is _____________ 14. By connecting low-resistance NMOSFET in series and high-resistance in parallel,

a NAND gate achieves ________________ 15. The Scaling factor for gate oxide thickness is _______________ III True (or) False Statements: 16. pMOS transistor are inherently faster than the nMOS transistors 17. In BiCMOS, the logical approach is to use MOS switches to perform the logic

function 18. The feature size will scale down without changing design rules 19. Layers cannot join together where contacts are formed 20. The sheet resistance of 1µm per side square slab is twice that of 1 cm per square

side slab of same material if the thickness is the same

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1. To provide a interconnection pattern which of the following layers is used? [ ]

1. Thin layer of SiO2 2. Poly silicon layer 3. Phtoresist layer 4. Aluminum layer

2. The advantages of CMOS technology compared to Bipolar technology [ ]

1. Low delay sensitivity to load 2. High output drive current 3. High packing density 4. High gain

3. The expression for drain to source current in saturated region for enhancement MOS device

is [ ]

1. 2

)( 2tgs VV

K−

2.2

)( 2tgs VV

LWK

−

3. 2

)( 2tgs VV −

4. ⎟⎟⎠

⎞⎜⎜⎝

⎛−−

2)(

2ds

dstgsV

VVVLWK

4. The following are remedies for the latch-up problem for BiCMOS circuits except [ ]

1. High contact resistance to VSS 2. An increase in substrate doping levels 3. A reduction of substrate resistance 4. A reduction of n-well resistance

5. BiCMOS inverter has the following advantage [ ]

1. Low input impedance 2. Low output impedance 3. Low current dive capability 4. Occupies a large area

6. Design efficiency accomplished by all of the following except [ ]

1. Improvements in process technology 2. Layout rule checking 3. Simulation 4. Verification

7. The minimum separation between two polysilicon layers in λ based design rules is

[ ] 1. 1 λ 2. 2 λ 3. 3 4. 4λ

Cont….2

: 2 :

Code No: 05320402 Set No. 4 8. One of the following is the complex logic gate [ ]

1. NAND 2. NOR 3.EX-OR 4. AN-OR-INVERT 9. The delay through a pair of nMOS inverter is [ ]

1. τ)./.( dZpuZp 2. τ)./.1( dZpuZp+ 3. τ)./.1( uZpdZp+ 4. τ

10. The sheet resistance of silicides layer compared to polysilicon layer is [ ]

1. Twice 2. High 3. Low 4. Same

II Fill in the blanks: 11. The gate/channel capacitance Cg and gate capacitance/unit area Co are related as ______________ 12. An inverter driven through one or more pass transistors should have a Zp.u./Zp.d

ratio of _________________ 13. _______________ is used in NMOS circuits to produce depletion mode transistors 14. The parasitic capacitance is scaled by _______________ 15. In CMOS the rise time delay time is _____________times then a fall time delay for equal n

and p transistor geometries III Match the following:

Match the following with respect to stick diagram for a double metal CMOS p-well process

16. P+mask [ ] a. Black 17. p-well [ ] b. Blue 18. p-diffusion [ ] c. Yellow 19. Metal 2 [ ] d. Brown 20. VDD contact [ ] e. Green

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vlsi design quiz paper

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