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  • *VLSI Design Cycle

  • *VLSI Design cycle:VLSI design cycle start with a formal specification of a VLSI chip, follows a series of steps, and eventually produces a packaged chip.

  • *A simple VLSI design cycle:System SpecificationFunctional designLogic designCircuit designPhysical designFabricationPackaging, Testing and Debugging

  • *VLSI Design CycleSystem SpecificationArchitectural DesignLogic DesignCircuit DesignPhysical DesignFunctional DesignFabricationPackaging

  • *System SpecificationFirst step of design process is to lay down the specification of the system.High level representation of the system. Factors considered:PerformanceFunctionalityPhysical dimensionDesign techniqueFabrication technologyIt is a compromise between market requirements, technological and economical viability.

  • *System Specification contd.The end results are specifications ofSizeSpeedPower andFunctionality of the VLSI systemBasic architecture of the system are also specified, such asFloating point unitRISC versus CISC systemNumber of ALUsNumber and structure of the pipelinesSize of the cache, etc.

  • *Functional DesignMain functional units of the system are identifiedIdentifies the interconnect requirements between the unitsThe area, power and other parameters of each unit are estimatedThe behavioral aspects of the system are considered not implementation specification- multiplication needed but does not specify its hardware The key idea is to specify behavior, in terms ofInputOutputTiming of each unitWithout specifying the internal structure.

  • *Functional Design contd.The outcome of functional design is usually a timing diagram or other relationships between units.This information leads to improvement of the overall design process and reduction of complexity of the subsequent phases.Functional design provides a quick emulation of the system and allows fast debugging of the full system.

  • *Logic DesignDesign the logic, that is, Boolean expressions, control flow, word width, register allocation, etc.

    The outcome is called an RTL (Register Transfer Level) description. RTL is expressed in a HDL (Hardware Description Language), such as VHDL and Verilog.

    This description can be used in simulation and verification.As this description consists of Boolean expressions, so they can be minimized to achieve the smallest logic design.X = (AB+CD)(E+F)Y= (A(B+C) + Z + D)

  • Logic Design cont

    Logic and RTL Simulation Logical simulation is used for verifying the logical correctness of a hardware design. Modern HDLs are both simulatable and synthesizable.RTL simulation is made by applying test vectors or by running test benchesLogic Optimization Logic optimization (a part of logic synthesis) is the process of finding an equivalent representation of the specified logic circuit under one or more specified constraints.Generally, the circuit is constrained to minimum chip area meeting a pre-specified delay.

    *X = (AB+CD)(E+F)Y= (A(B+C) + Z + D)

  • Logic Design cont

    Logic SynthesisLogical synthesis is the process of translating an abstract form of a desired circuit behavior into a design implementation in terms of logic gates.This process is carried out by automatic synthesis tools with sophisticated algorithms.The outcome of this logic synthesis is the netlist or schematic.The corresponding circuit hardware realization is carried out by a synthesis tool through two common approaches; namely, FPGA and ASIC.

    *X = (AB+CD)(E+F)Y= (A(B+C) + Z + D)

  • *Circuit DesignThe purpose of the circuit design is to develop a circuit representation based on the logic design.The Boolean expression can be converted into a circuit representation by taking into consideration the speed and power requirements of the original design.Design the circuit including gates, transistors, interconnections, etc. The outcome is called a netlist.Circuit simulation is used to verify the correctness and timing of component.

  • *Physical DesignThe circuit representation of each component is converted into geometric representation.Convert the netlist into a geometric representation. The outcome is called a layout.

    Connections between different components are also expressed as a geometric pattern.

    Exact details depends upon design rules

    It is a complex process and usually broken down into sub-steps.Various verification and validation checks are performed on the layout during physical design.

  • Layout tools*Microwind layout tool: The following figure shows conversion of the NAND gate circuit in to its equivalent geometric pattern(layout). -Other Layout tools includes Magic.

  • *Fabrication Fabrication: Process includes lithography, polishing, deposition, diffusion, etc., to produce a chip.

    Fabrication process consists of several steps and requires various masks.Before the chip is mass produced, a prototype is made and tested.

  • *Packaging, Testing and DebuggingPackaging Put together the chips on a PCB (Printed Circuit Board) or an MCM (Multi-Chip Module)

    Each chip is then packaged and tested to ensure that it meets all the design specifications and that it functions properly.

  • *VLSI Design CycleSystem SpecificationArchitecturalSpecificationRTL in HDLNetlistLayoutTiming & relationshipbetween functional unitsChipsPackaged andtested chipsArchitecturalDesignFunctionalDesignLogicDesignPhysicalDesignFabricationPackagingCircuit DesignorLogic Synthesis

  • *Physical Design Cycle The input of the physical design cycle is a circuit diagram and the output is the layout of the circuit.

  • *Circuit PartitioningA chip may contain several million transistors. So layout of the entire circuit can not be handled due to the limitation of memory space and computation power available.

  • *Circuit Partitioning contd.2. Partition a large circuit into sub-circuits (called blocks).3. Factors like #blocks, block sizes, interconnection between blocks, etc., are considered.4. The output of partitioning is a set of blocks and the interconnections between them.5. Partitioning may be hierarchical.

  • *Floorplanning

    This step is concerned with selecting good layout for each block as well as the entire chip.The area of each block can be estimated after partitioning based approximately on the number and type of components of that block.Interconnect area between blocks is also considered.Done by design engineer rather than CAD tools: human is better in visualization.Certain components are often required to be located at a specific position on the chip.

  • *PlacementThe blocks are exactly positioned on the chip.The goal is to minimize the area arrangement for the blocks that allows completion of interconnections between the blocks while meeting the performance constraints. For example: routable blocks but fails timing goals.FeedthroughStandard cell type 1Standard cell type 2

  • *Placement contd.Two phases: initial placement is created in the first phase. In second phase, initial placement is evaluated and iterative improvements are made until the layout has minimum area.Quality of placement will not be evident until the routing phase has been completed. Placement may lead to an un routable design: More space may be needed.Good routing and circuit performance heavily depends on a good placement algorithm.This is due to the fact that after the position of the block has been fixed, routing can do nothing.

  • *Routing

    Objectives is to complete the interconnections between modules.Routing space is partitioned into channels and switchboxes.Two phases : global routing and detailed routing.

    FeedthroughType 1 standard cel1Type 2 standard cell

  • *Global routing (GR)In global routing, connections are completed between proper blocks of the circuit disregarding exact geometric details of each wire and pin.For each wire GR finds a lists of channels which are to be used as a passageways for that wire. In other words, GR specifies different regions in the routing space through which a wire should be routed.Detailed routing (DR)DR completes point-to-point connections between pins on the blocks. GR is converted into exact routing by specifying geometric information such as location and spacing of wires and their layer assignments.It includes channel and switchbox routing.

  • *Compaction & VerificationCompaction Compress the layout from all directions to minimize the total chip area. Advantages:Making chip smaller, wire lengths are reduced.Reduces signal delays.More chip on a small area, so manufacturing cost reduced.

    But should ensure design rules.

    Verification Check the correctness of the layout. Include DRC (Design Rule Checking), circuit extraction (generate a circuit from the layout to compare with the original netlist), performance verification, reliability verification.

  • *Review Physical DesignThe final physical layout of a complicated circuit on a small piece of silicon is generated in a set of steps using CAD tools

    PartitioningBreak the circuit up into smaller segmentsPlace the segments on the chipLayout out thewire paths K-L and F-M AlgorithmsConstructive & K-L Algorithms

  • Physical Design AlgorithmsPartitioning -Fiduccia-Mattheyses(FM)-(Kernighan-Lin)KL, hMetis algorithmsFloor planningSimulated annealing floor planning algorithmsPlacement / PackingSimulated annealingGlobal / detailed routingMaze routing, line-search, Steiner trees, channel routing