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ECE 538 Krish Chakrabarty 1
ECE 538
VLSI System Testing
Krish Chakrabarty
Logic Simulation
ECE 538 Krish Chakrabarty 2
Introduction • Motivation • Types of logic simulation
– Compiled code – Event-driven
• Delay models • Element evaluation • Hazard detection
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ECE 538 Krish Chakrabarty 3
Motivation
• A design verification technique (functional and timing) • Compare results obtained with expected responses
specified by the specification • Use software model
Simulation program
Stimuli and control
Internal model
Results
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Motivation
• Correctness, independent of initial (power-on) state • Insensitive to small variations in component delays • Free of races, oscillations, “illegal” input
combinations, “unsafe” states • Evaluation of design alternatives (what-if scenarios) • Documentation (generation of timing diagrams)
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Logic Simulation • What is simulation? • Design verification • Circuit modeling • True-value simulation algorithms
• Compiled-code simulation • Event-driven simulation
• Summary
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Simulation Defined • Definition: Simulation refers to modeling of a design, its
function and performance. • A software simulator is a computer program; an emulator is a
hardware simulator. • Simulation is used for design verification:
• Validate assumptions • Verify logic • Verify performance (timing)
• Types of simulation: • Logic or switch level • Timing • Circuit • Fault
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Simulation for Verification
True-value simulation
Specification
Design (netlist)
Input stimuli Computed responses
Response analysis
Synthesis
Design changes
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Modeling for Simulation • Modules, blocks or components described by
• Input/output (I/O) function • Delays associated with I/O signals • Examples: binary adder, Boolean gates, FET, resistors and
capacitors
• Interconnects represent • ideal signal carriers, or • ideal electrical conductors
• Netlist: a format (or language) that describes a design as an interconnection of modules. Netlist may use hierarchy.
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Example: A Full-Adder HA; inputs: a, b; outputs: c, f; AND: A1, (a, b), (c); AND: A2, (d, e), (f); OR: O1, (a, b), (d); NOT: N1, (c), (e);
a
b
c
d e
f HA
FA; inputs: A, B, C; outputs: Carry, Sum; HA: HA1, (A, B), (D, E); HA: HA2, (E, C), (F, Sum); OR: O2, (D, F), (Carry);
HA1 HA2
A B C
D E F
Sum
Carry
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Ca
Logic Model of MOS Circuit
Cc Cb
VDD
a
b c
pMOS FETs
nMOS FETs
Ca , Cb and Cc are parasitic capacitances
Dc Da
c a
b
Da and Db are interconnect or propagation delays
Dc is inertial delay of gate
Db
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Options for Inertial Delay (simulation of a NAND gate)
b
a
c (CMOS)
Time units 0 5
c (zero delay)
c (unit delay)
c (multiple delay)
c (minmax delay)
Inpu
ts
Logi
c si
mul
atio
n
min =2, max =5
rise=5, fall=5
Transient region
Unknown (X)
X
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Signal States • Two-states (0, 1) can be used for purely combinational logic
with zero-delay. • Three-states (0, 1, X) are essential for timing hazards and
for sequential logic initialization. • Four-states (0, 1, X, Z) are essential for MOS devices. See
example below. • Analog signals are used for exact timing of digital logic and
for analog circuits.
0 0
Z (hold previous value)
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Modeling Levels Circuit description
Programming language-like HDL
Connectivity of Boolean gates, flip-flops and transistors
Transistor size and connectivity, node capacitances
Transistor technology data, connectivity, node capacitances
Tech. Data, active/ passive component connectivity
Signal values
0, 1
0, 1, X and Z
0, 1 and X
Analog voltage
Analog voltage, current
Timing
Clock boundary
Zero-delay unit-delay, multiple- delay
Zero-delay
Fine-grain timing
Continuous time
Modeling level
Function, behavior, RTL
Logic
Switch
Timing
Circuit
Application
Architectural and functional verification
Logic verification and test
Logic verification
Timing verification
Digital timing and analog circuit verification
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True-Value Simulation Algorithms
• Compiled-code simulation (oblivious simulation) • Applicable to zero-delay combinational logic • Also used for cycle-accurate synchronous sequential circuits
for logic verification • Efficient for highly active circuits, but inefficient for low-
activity circuits • High-level (e.g., C language) models can be used
• Event-driven simulation (exclusive simulation of activity) • Only gates or modules with input events are evaluated (event
means a signal change) • Delays can be accurately simulated for timing verification • Efficient for low-activity circuits • Can be extended for fault simulation
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Types of Simulation (Contd.) • Compiled-code (oblivious)
– The circuit is described in a programming language and an executable model is generated
– Circuit operation ≡ program execution – Fast and efficient but inflexible; practical only for small circuits
• Event-driven – Exclusive simulation of activity – Circuit is a data structure, simulation program is same for all circuits – Flexible, but requires event list management (overhead)
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Compiled-Code Algorithm
• Step 1: Levelize combinational logic and encode in a compilable programming language
• Step 2: Initialize internal state variables (flip-flops) • Step 3: For each input vector
– Set primary input variables – Repeat (until steady-state or max. iterations)
• Execute compiled code – Report or save computed variables
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Compiled-Code Simulation
D C
Q B
A
E
F LDA B AND Q INV STA E OR A STA F STA Q
Simulation program • Delays can be modeled by explicitly adding them to the software model
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Event-Driven Simulation Advance simulation time
Determine current events
Update values
Propagate events
Evaluate activated elements
Schedule resulting events
Done No more events
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Event-Driven Simulation
B
A
E F
2
2
C
D Z
0
1 → 0 at t = 0
1 0
0
1
Event Time F = 1 t = 2
t = 0
Snapshot of event list
Event Time G = 1 t = 4 Z = 1 t = 4
t = 2 Event Time Y = 1 t = 7
t = 4
3
2
Y
G
0
0
0
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Event-Driven Algorithm (Example)
2
2
4
2
a =1
b =1
c =1 0
d = 0
e =1
f =0
g =1
Time, t 0 4 8
g
t = 0
1
2
3
4
5
6
7
8
Scheduled events
c = 0
d = 1, e = 0
g = 0
f = 1
g = 1
Activity list
d, e
f, g
g
Tim
e st
ack
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Time Wheel (Circular Stack)
t=0
1
2
3
4
5
6
7
max Current time pointer Event link-list
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Efficiency of Event-driven Simulator
• Simulates events (value changes) only • Speed up over compiled-code can be ten times or
more; in large logic circuits about 0.1 to 10% gates become active for an input change
Large logic block without
activity
Steady 0
0 to 1 event
Steady 0 (no event)
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Delay Models • Transport delay (pure delay)
– Single delay value for each gate
• Rise/fall times – Two delay values for each gate output
• Ambiguity delay – Min and max delay values for each gate – Ambiguity region becomes enlarged towards primary outputs
• Inertial delay – Filter out narrow pulses (spikes and glitches)
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Element Evaluation • Simulation speed depends on fast elements (gates) that can be
evaluated • Truth tables
– O(1) evaluation but O(2N) storage – Decision step needed (which truth table?)
• Zoom table of size tS combines t individual truth tables, S is size of largest truth table
Type 0 Type 1
Type t-1
type values index
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Input Scanning evaluate (G,c,i) begin u_values = FALSE; for every input value of G begin if v = c then return c ⊕ i if v = u then u_values = TRUE end if u_values return u return c ⊕ i end
O(1) storage, O(N) evaluation
• Controlling value c • Inversion value i
c X X c ⊕ i X c X c ⊕ i X X c c ⊕ i c c c c ⊕ i
c i AND 0 0 OR 1 0 NAND 0 1 NOR 1 1
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Input Counting • Maintain two counters c_count and u_count for every gate
– c_count: number of inputs with c values – u_count: number of inputs with u values
• These counters must be updated
evaluate (G,c,i) begin if c_count > 0 then return c ⊕ i if u_count > 0 then return u return c ⊕ i end
• O(1) storage • O(1) evaluation
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Hazard Detection
B A
C
0 → 1
0
1 0 Static hazard: 0 → 1 → 0 Dynamic hazard: 0 → 1 → 0 → 1
• Simulator should detect hazards (analyze transient behavior of signals) • 3-valued logic simulation:
B A
C
0X1
000
1X0 0X0
Static hazard detected
• How many logic values are necessary? • More the better, but…more complexity
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Summary • Logic or true-value simulators are essential tools for
design verification. • Verification vectors and expected responses are
generated (often manually) from specifications. • A logic simulator can be implemented using either
compiled-code or event-driven method. • Per vector complexity of a logic simulator is
approximately linear in circuit size. • Modeling level determines the evaluation procedures
used in the simulator.