VLSI Test Symposium, 2011 Nuno Alves, Yiwen Shi, and R. Iris Bahar School of Engineering, Brown University, Providence, RI Jennifer Dworak Department of Computer Science & Engineering, Southern Methodist University, Dallas, TX Kundan Nepal Electrical Engineering Department, Bucknell University, Lewisburg, PA Outline Background & Previous Work Two-site logic implications Multi-site (residual) implications Experimental results Conclusions Outline Background & Previous Work Two-site logic implications Multi-site (residual) implications Experimental results Conclusions Background & Previous Work Online error detection aims to monitor circuit behavior at run time and detect deviations from its normal operating behavior while the device is in operation. Redundancy in time e.g. re-executing in a redundant thread Logic duplication or Triple Modular Redundancy Codes e.g. Parity, Berger, Bose Lin Pre-computed test vectors and their expected responses (stored in hardware) High-level functional assertions 4 Outline Background & Previous Work Two-site logic implications Multi-site (residual) implications Experimental results Conclusions Two-site Logic Implications 6 n5 = 1 n8 = 0 n1 n2 n3 n4 n5 n6 n7 n Implications within a logic block describe expected relationships between values at circuit sites. Two-site Logic Implications 7 n1 n2 n3 n4 n5 n6 n7 n8 ERROR n5 = 1 n8 = 0 Violation of an expected implication indicates the presence of an error. sa1 Limitation of Simple Two-site Implications Each implication can only cover a limited area of the circuit. 8 P Q Direct Path P=0 Q=0 Faults along the path may be detected P Q P Q P=1 Q=1 Faults along reconverging paths may be detected Reconvergent Fanout P Q Divergent Fanout P Q Q=0 P=0 Faults along paths to common ancestors may be detected Checking Functions G = H i OP H j where OP {AND, OR, XOR} 9 A B C ERROR siteA AND siteB siteC [by I. Pomeranz and S. M. Reddy VDC1996, DFT2004] Comparison of Simple Implications & Checking Functions in error detection probability 10 Simple Implication Identification site A and B possible values observed values in the input space potential simple implication: A=1 -> B=0 (B=1 -> A=0) Simple Implication Identification site A and B possible values potential simple implication: ??? observed values in the input space Outline Background & Previous Work Two-site logic implications Multi-site (residual) implications Experimental results Conclusions Residual Implication Identification site A and B potential residual implication: P=0 -> (A=1 -> B=1) possible values P=0P=1 Split the input space into two pieces by a residual pivot site P observed values in the input space Implementation of the Checker Logic using Residual Implication siteA = 1 -> (siteB = 0 -> siteC = 0) 15 A B C ERROR Simple Implication Selection 16 Identify potential implications w/ simulation Identify potential implications w/ simulation Verify implications w/ a SAT solver Compress implications Select best subset for target error detection and overhead End Start Residual Implication Selection 17 Identify potential residual implications w/ simulation Verify implications w/ a SAT solver Compress implications Select best subset for target error detection and overhead End Start Determine optimized splitting points We select the splitting sites to be those sites whose associated faults are propagated the most and whose errors are not often detected by any simple implications Outline Background & Previous Work Introduction to logic implications Multi-site (residual) implications Experimental results Conclusions Probability of Detection for the Various Subsets of Implications 19 Hardware Overhead (%) Simple Implication Checking Function Simple + Residual Implication Combined Distribution of the Types of Relationships Making Up the Checker Logic When All Three Types Are Combined 20 Simple ImpResidual ImpChecking Func Hardware Overhead (%) Optimized with fewer redundancy Residual Implications on Synthesized/Optimized Circuits Residual implications appear to be especially useful for circuits that have gone through some optimization procedure. 21 Un-optimized Optimized for Area Optimized for Delay Improvement in P(Detection) for resynthesized ISCAS85 circuits using simple + residual imp vs. simple imp Conclusions Introduced residual implications Presented an algorithm for finding and choosing a set of residual implications to be incorporated into the checker logic for online error detection. Showed that significant improvement in error detection is possible Especially in the case of the ITC99 benchmarks studied. Proposed hybrid checker logic (residual implications + checking functions) With only a 10% area overhead, we were able to detect more than 50% of the errors in the unoptimized ISCAS85 benchmarks, and almost 40% of the errors in the ITC99 benchmarks.