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Chapter 8

CMOS Testing

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functionality tests or logic verification

second set of tests is run on the first batch of chips

manufacturing tests

Testing a die (chip) can occur at the

Wafer level

Packaged chip level

Board level

System level

Field level

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Logic Verification

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Manufacturing Tests

Typical defects include:

Layer-to-layer shorts (e.g., metal-to-metal)

Discontinuous wires (e.g., metal thins when crossing verticaltopology jumps)

Missing or damaged vias Shorts through the thin gate oxide to the substrate or well

These in turn lead to particular circuit maladies, including:

Nodes shorted to power or ground

Nodes shorted to each other

Inputs floating/outputs disconnected

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Manufacturing Test Principles:

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Stuck-at Faults

Short-circuit and Open-circuit Faults

Fault Models

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Stuck-at Faults

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Short-circuit Faults

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Open-circuit Faults

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Observability

Controllability

Fault Coverage Automatic Test Pattern Generation

(ATPG)

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Delay Fault Testing

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Design for Testability

Adhoc testing

Scan-based approaches

Built-in self-test (BIST)

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Partitioning large sequential circuits

Adding test points

Adding multiplexers Providing for easy state reset

Adhoc testing

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Scan Design:

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Parallel Scan:

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Partial Scan:

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Shift Register Latch

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Circuit Design of Scannable Elements:

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Built-in Self-Test (BIST)

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Built-in Self-Test (BIST):Pseudo random sequence generator:

LFSR(Linear Feedback Shift Register)CFSR(Complete Feedback Shift Register)

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BILBO

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IDDQ Testing

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Design for Manufacturability

Increase the spacing between wires wherepossible

Increase the number of vias at wireintersections beyond one if possible

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Redundancy

Power

Process Spread Yield Analysis

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Boundary Scan

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The Test Access Port (TAP)

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The TAP Controller

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Instruction Register

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Test Data Registers

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Boundary Scan Register

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Bypass Register

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TDO Driver