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Synchronization ofcomplex systems

Jordi Cortadella

Universitat Politecnica de Catalunya

Barcelona, Spain

Thanks to A. Chakraborty, T. Chelcea,

M. Greenstreet and S. Nowick

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Multiple clock domains

CLK

f1/f0

f2/f0

f3/f0

CLK

(f0)

CLK1

CLK2

CLK3

CLK0

Single clock

(Mesochronous)Rational clock frequencies

Independent clocks

(plesiochronous

if frequencies

closely match)

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The problem: metastability

D Q

T

D Q

?

D

Q

RR setup hold

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Classical synchronous solution

Wff

e

D

rt

MTBF

2

D Q D Q D Q D Q

T

R

Mean Time Between Failures

f: frequency of the clock

fD: frequency of the data

tr: resolve time availableW: metastability window

: resolve time constant

# FFs MTBF

1 FF 15 min

2 FF 9 days

3 FF 23 years

Example

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How to live with metastability ?

Metastability cannot be avoided, it must be tolerated.

Having a decent MTBF ( years) may result in atangible impact in latency

Purely asynchronous systems can be designedfailure-free

Synchronous and mixed synchronous-asynchronoussystems need mechanisms with impact in latency

But latency can be hidden in many cases

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Different approaches

Pausible Clocks (Yun & Donohue 1996)

Predict metastability-free transmission windows for domains with

related clocks (Chakraborty & Greenstreet 2003)

Use the waiting time in FIFOs to resolve metastability

(Chelcea & Nowick 2001)

And others

The term Globally Asynchronous, Locally Synchronous is typicallyused for these systems (Chapiro 1984)

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Mutual exclusion element

req1

req2

ack1

ack2

0

0

1

1

0

0

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Metastability

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Mutual exclusion element

req1

req2

ack2

ack1

0

0

1

1

0

0

An asynchronous data latch with MSresolver can be built similarly

Metastability

resolver

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A pausible clock generator

delay

[1, 2]

Environment

MUTEX

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Pausible clocks

delay

[1, 2]

ME

CLK

Cntr

MUTEXFF

Req

Ack

Yun & Dooply, IEEE Trans. VLSI, Dec. 1999

Moore et al., ASYNC 2002

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STARI (Self-Timed At Receivers Input)

Both clocks are generated from the same sourceThe FIFO compensates for skew betweentransmitter and receiver

M. Greenstreet, 1993

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A Minimalist Interface

FIFO reduces to latch-X and a latch controller

x can always be generated in such a way as toreliably transfer data from input to output

Chakraborty & Greenstreet, 2002

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A Minimalist Interface: 3 scenarios

Latch-X setup & hold

Latch-R setup & hold

x Permitted

The scenario is chosen

at initialization

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A Minimalist Interface: latch controller

The controller detects which transition arrives first (from T and R)

and generates X accordingly

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A Minimalist Interface: rational clocks

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A Minimalist Interface: arbitrary clocks

Assumption: clocks are stableEach domain estimates the others frequency

Residual error corrected using stuff bits

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Mixed-Timing Interfaces

AsynchronousDomain

Synchronous

Domain 1

SynchronousDomain 2

Async-Sync FIFO

Async-SyncFI

FO

Sync-A

syncFIFO

Mixed-Clock FIFOs

Chelcea & Nowick, 2001

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Mixed-Clock FIFO: Block Level

full

req_put

data_put

CLK_put

req_get

valid_get

empty

data_get

CLK_getMixed-Clock

FIFO

synchronousput inteface

synchronousget interface

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Mixed-Clock FIFO: Block Level

full

req_put

data_put

CLK_put

req_get

valid_get

empty

data_get

CLK_getMixed-Clock

FIFO

Bus for data items

Controls get operations

Initiates get operations

Bus for data items

synchronousput inteface

synchronousget interface

Initiates put operations

Controls put operations

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full

req_put

data_put

CLK_put

req_get

valid_get

empty

data_get

CLK_getMixed-Clock

FIFO

synchronousput inteface

synchronousget interface

Indicates when FIFO empty

Indicates when FIFO fullIndicates data items validity

(always 1 in this design)

Mixed-Clock FIFO: Block Level

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Mixed-Clock FIFO: Architecture

cell cell cell cell cell

Get

Contro

ller

Empty Detector

Full DetectorPut

Controller

full

req_put

data_put

CLK_put

CLK_getdata_get

req_get

valid_get

empty

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REG

Mixed-Clock FIFO: Cell Implementation

En

En

f_ie_i

ptok_out ptok_in

gtok_ingtok_out

CLK_get en_get valid data_get

CLK_put en_put req_put data_put

SR

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REG

Mixed-Clock FIFO: Cell Implementation

En

En

f_ie_i

ptok_out ptok_in

gtok_ingtok_out

CLK_get data_get

CLK_put en_put data_put

SR

GET INTERFACE

PUT INTERFACE

en_get valid

req_put

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Synchronization: summary

Resolving metastability implies latency

Latency can be often hidden (FIFOs, Chelcea & Nowick)

Clock frequencies can be estimated and clock edgespredicted under the assumption of stable clocks(Chakraborty & Greenstreet)

Pausible clocks are also possible (Yun & Donohue 1996)

But still the nicest solutions are totally asynchronous As presented by Fulcrum Microsystems in the last lecture