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KKS: Outstanding Challenges in Testing Nanotechnology Based Integrated CircuitsKKS: Outstanding Challenges in Testing Nanotechnology Based Integrated Circuits 11

Outstanding Challenges in TestingOutstanding Challenges in Testing

Nanotechnology DevicesNanotechnology Devices

Kewal K. SalujaKewal K. SalujaDepartment of Electrical and Computer EngineeringDepartment of Electrical and Computer Engineering

University of Wisconsin-MadisonUniversity of Wisconsin-Madison


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22KKS: Outstanding Challenges in Testing Nanotechnology Based Integrated CircuitsKKS: Outstanding Challenges in Testing Nanotechnology Based Integrated Circuits

Cost of Integrated CircuitsCost of Integrated Circuits

Cost per IC = +Cost per IC = +

Variable cost per ICVariable cost per IC

Fixed cost to produce the design:Fixed cost to produce the design: One time costOne time cost

Design cost (= Design + Design Verification + Debugging)Design cost (= Design + Design Verification + Debugging)

Test generation costTest generation costFabrication costFabrication costIn-house (fabrication equipment) or external contractIn-house (fabrication equipment) or external contract

Mask making, number of metal layers, technology and materialsMask making, number of metal layers, technology and materials

Variable cost per IC:Variable cost per IC: Recurring costRecurring cost

AssemblyAssembly and packagingand packaging

Test application costTest application cost (DFT, test equipment, test generation)(DFT, test equipment, test generation)

Cost of testingCost of testing willwill EXCEEDEXCEED the cost of design/manufacturingthe cost of design/manufacturing

Fixed costFixed cost

volumevolume


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Microprocessor Cost per Transistor:Microprocessor Cost per Transistor:Cost of testingCost of testing willwill EXCEEDEXCEED thethe cost of design/manufacturingcost of design/manufacturing

((Source: ITR-Semiconductor, 2001)Source: ITR-Semiconductor, 2001)


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Test Application CostTest Application Cost

Test Application CostTest Application Cost ==

No. of Vectors ~= (No. of Gates)No. of Vectors ~= (No. of Gates),, = 0.7 ~ 0.9= 0.7 ~ 0.9

No. of FFs ~= (No. of Gates)No. of FFs ~= (No. of Gates),, = 1.0 ~ 1.0+= 1.0 ~ 1.0+

No. of Pins ~= (No. of Gates)No. of Pins ~= (No. of Gates),, = 0.5 or less= 0.5 or less (ITRS 2001)(ITRS 2001)

Frequency of tester: expected to be almost constant for eachFrequency of tester: expected to be almost constant for eachdecadedecade (ITRS2001)(ITRS2001)

Test Application TimeTest Application Time ~= (No. of Gates)~= (No. of Gates)++--,, ++-- = 1.1 ~ 1.3= 1.1 ~ 1.3

Rate of Test Application Time ChangeRate of Test Application Time Change No. of Gates are doubled for every 18 months (Moores law)No. of Gates are doubled for every 18 months (Moores law)

No. of Tests are doubled when No. of Gates are 1.87X or 1.70XNo. of Tests are doubled when No. of Gates are 1.87X or 1.70X=>=> No. of Tests are doubled for every 13 to 16 monthsNo. of Tests are doubled for every 13 to 16 months

No. of Vectors No. of FFsNo. of Vectors No. of FFs

No. of PinsNo. of Pins Frequency of tester Frequency of tester


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Increase in Gate Count vs. Test Application TimeIncrease in Gate Count vs. Test Application Time(1997-2007(1997-2007))

0

100

200

300

400

500

600

700

1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007

Gate Count (Doubles 18)

TAT (Doubles 13)

TAT (Doubles 16)


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Overview of General DifficultiesOverview of General DifficultiesPresent and near future testing problems (Present and near future testing problems (2015)2015)

Test generation andTest generation and fault simulation for traditional and non traditionalfault simulation for traditional and non traditionalfault models for a single corefault models for a single core

Test generation and test application costTest generation and test application cost (test data volume)(test data volume)

Reduction of test application powerReduction of test application power

Thermal constraint testingThermal constraint testing

Fault diagnosis for volume productionFault diagnosis for volume production

Test generation, DFT, BIST and test application problems forTest generation, DFT, BIST and test application problems for

multicore ICsmulticore ICs

Future testing problems (>2015)Future testing problems (>2015)

DFT and standardization challengesDFT and standardization challenges

Operational life failuresOperational life failures

Esoteric technologiesEsoteric technologies


7/2877KKS: Outstanding Challenges in Testing Nanotechnology Based Integrated CircuitsKKS: Outstanding Challenges in Testing Nanotechnology Based Integrated Circuits

Signal Integrity ProblemsSignal Integrity Problems

Noise faults caused by parametric variations:Noise faults caused by parametric variations:

Must be properly modeled to levels of abstraction higher than theMust be properly modeled to levels of abstraction higher than the

electrical, circuit, and transistor levels for the purposes of faultelectrical, circuit, and transistor levels for the purposes of fault

simulation, ATPG, and BISTsimulation, ATPG, and BIST

signal integrity verification problems are becoming test problems.signal integrity verification problems are becoming test problems.

Crosstalk-induced delay and pulsesCrosstalk-induced delay and pulses

Distributed delay variationsDistributed delay variations

Excessive voltage drop and/or swing on power netsExcessive voltage drop and/or swing on power nets

Substrate and thermal noisesSubstrate and thermal noises

Process variations (pvt process, voltage, tempProcess variations (pvt process, voltage, temp

problems)problems)



Crosstalk FaultsCrosstalk Faults

Coupling between nets posts a serious problem inCoupling between nets posts a serious problem in

high-speed, deep-submicron VLSI circuits.high-speed, deep-submicron VLSI circuits.

Two types of coupling effectsTwo types of coupling effects Crosstalk-induced delayCrosstalk-induced delay - signal transition rate of a line- signal transition rate of a line

altered by simultaneous transitions on other linesaltered by simultaneous transitions on other linesSpeed-up: same directionSpeed-up: same direction

Slow-down: opposite directionSlow-down: opposite direction

Crosstalk-induced pulseCrosstalk-induced pulse - transition on an aggressor line- transition on an aggressor line

induces temporary signal value change on a victim lineinduces temporary signal value change on a victim linePulse on the victim linePulse on the victim line

If victim is a clock line, spurious pulse can cause flip-flops to captureIf victim is a clock line, spurious pulse can cause flip-flops to capture

incorrect logic valuesincorrect logic values



Crosstalk-Induced Delay

Crosstalk speedupCrosstalk slow-down

Victim-line

Aggressor-line

Victim-line

Aggressor-line

Time

victim

Time

aggressor



Crosstalk-Induced PulseCrosstalk-Induced Pulse

DQ

coupling

Data in

CLK

(victim)

Aggressor

T

Data out

capture

capture

Data in



Testing Crosstalk FaultsTesting Crosstalk Faults

Large combination of aggressor-victim pairsLarge combination of aggressor-victim pairs

even in relatively small circuiteven in relatively small circuit

Conventional method of testing crosstalkConventional method of testing crosstalk

faultsfaults Determine aggressor-victim fault-pair candidates via layoutDetermine aggressor-victim fault-pair candidates via layout

information (parasitic capacitances, locality, etc)information (parasitic capacitances, locality, etc)

Simulate each fault at electrical-level (SPICE and the like)Simulate each fault at electrical-level (SPICE and the like)

LimitationsLimitations

Low-level simulation very time-consumingLow-level simulation very time-consumingCoverage possibly limited by time constraintCoverage possibly limited by time constraint

Inability to incorporate common fault simulation techniquesInability to incorporate common fault simulation techniques

Concurrently simulating faults, fault-dropping, etcConcurrently simulating faults, fault-dropping, etc



Crosstalk Fault SimulationCrosstalk Fault Simulation

Logic-level crosstalk fault simulation potentiallyLogic-level crosstalk fault simulation potentiallyrequires much less computational resources and timerequires much less computational resources and time More faults can be simulatedMore faults can be simulated

Can be integrated into conventional schemeCan be integrated into conventional scheme Logic-level fault simulation to filter out undetectable faultsLogic-level fault simulation to filter out undetectable faultsReduce fault candidate pool to a manageable sizeReduce fault candidate pool to a manageable size

Layout information, can further reduce the candidates in this poolLayout information, can further reduce the candidates in this pool

Electrical-level simulation for remaining faults (as a verification)Electrical-level simulation for remaining faults (as a verification)

Drastically reduce simulation timeDrastically reduce simulation time Same or better accuracySame or better accuracy



Operational-Life FaultsOperational-Life Faults

Certain classes of faults are hard to identify during normalCertain classes of faults are hard to identify during normalmanufacturing test processmanufacturing test process

Result of dielectric, conductor, metallization failuresResult of dielectric, conductor, metallization failures

Responsible for failures during a devices operational lifeResponsible for failures during a devices operational life

Soft (transient) faults Soft (transient) faults soft errors due to cosmic rayssoft errors due to cosmic rays

Device degradation (NBTI)Device degradation (NBTI)

Hard (permanent) faultsHard (permanent) faults

Hard faults should beHard faults should be detecteddetectedDevices should be able toDevices should be able to toleratetolerate both soft and hardboth soft and hard

faultsfaults



Test data volume: Output compactionTest data volume: Output compaction

Scan design tested by Automated Test Equipment.Scan design tested by Automated Test Equipment.

Objectives: reduce test application time and test volumeObjectives: reduce test application time and test volume

stored on the ATE.stored on the ATE.

Co

mpac

tor

Inputs:Test stimuli

Outputs:Test response



Model: block compactorModel: block compactor

n

d

d

n.d m.dm

Inputdata block Output

data block

Linearcompactor



Linear compactorsLinear compactors

Compactors implemented with xor trees.Compactors implemented with xor trees.

m.doutputs

n.dinputs

in 1in 2

in 3in 4in 5in 6in 7

in 8

out1

out2

out3

out4

Row of weight 3

Row of weight 1



Single weight compactorsSingle weight compactors

Construction: every row is non-zero, differentConstruction: every row is non-zero, different

and with identical, odd weight.and with identical, odd weight.

Property in theProperty in the

absence of X values:absence of X values:

One, two, or any oddOne, two, or any odd

number of errors arenumber of errors are

guaranteed to beguaranteed to be

detected.detected.

1

10

0

0

0

0

0

0 1 0 1 0


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Main ideaMain idea

Observation: X values are non-uniformlyObservation: X values are non-uniformlydistributed among the scan chains.distributed among the scan chains.

Modified scheme:Modified scheme:

Use matrices with multiple weights.Use matrices with multiple weights.

Assign:Assign:

Low weight to scan chains producing many Xs.Low weight to scan chains producing many Xs.

High weight to scan chains producing few Xs.High weight to scan chains producing few Xs.



Multiple weight compactorsMultiple weight compactors

Construction: every row is non-zero, different and withConstruction: every row is non-zero, different and withodd weight.odd weight.

Property in theProperty in the

absence of X values:absence of X values:

Same as single weight.Same as single weight.

One, two, or any oddOne, two, or any odd

number of errors arenumber of errors are

guaranteed to beguaranteed to bedetected.detected.

1

10

0

0

1

0

0

0 0 0 1 0


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Introduction: Test SchedulingIntroduction: Test Scheduling

ExternalExternal

Test BusTest Bus

Core 1Core 1 Core 2Core 2 Core 3Core 3


BISTBISTBISTBIST

BISTBIST

BISTBIST

Test Scheduling: In order to reduce the test cost, the testingtime must be minimized by carefully scheduling tests for cores at

the system level and the tests must be scheduled without violating

any constraint.


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Background: HistoryBackground: History

Kime and Saluja 82Kime and Saluja 82

Abadir and Breuer 85Abadir and Breuer 85

Craig, Kime and Saluja 88Craig, Kime and Saluja 88

Chou, Saluja and Agrawal 94Chou, Saluja and Agrawal 94

Iyengar and Chakrabarty 02Iyengar and Chakrabarty 02

Zhao and Upadhyaya 05Zhao and Upadhyaya 05

Rosinger and Al-Hashimi 05Rosinger and Al-Hashimi 05

He, Peng and Eles 07He, Peng and Eles 07

Bild, Dick etc. 08Bild, Dick etc. 08

Resource ConstrainedResource Constrained Power ConstrainedPower Constrained Thermal ConstrainedThermal Constrained


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Literature Review: Resource constrained Test schedulingLiterature Review: Resource constrained Test scheduling

GoalGoal: Minimize total test time under: Minimize total test time underresourceresource constraintsconstraints



BISTBIST

BISTBIST

BISTBIST

BISTBIST

t1t1

t2t2

t4t4

t3t3

t5t5

t6t6

XX

XX

Test compatibility graph (TCG)Test compatibility graph (TCG)


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t1t1

t2t2

t4t4

t3t3

t5t5

t6t6

Clique coverClique coverheuristicheuristic AA cliqueclique is a maximal completeis a maximal complete

subgraph of a graph.subgraph of a graph.

Goal: cover all nodes byGoal: cover all nodes by minimumminimumnumber of cliques.number of cliques.

Solution:Solution:

(1,3,5)(1,3,5)

(2,6)(2,6)

(4)(4)

GoalGoal: Minimize total test time under: Minimize total test time underresourceresource constraintsconstraints


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Test SessionTest Session

A subset of the test set such that all the tests in the test session areA subset of the test set such that all the tests in the test session arecompatiblecompatible..

Next test session can startNext test session can start only afteronly afterprevious test session is completed.previous test session is completed.

Test timeTest time

t1t1

t3t3

t5t5

t2t2

t6t6 t4t4

Session 1Session 1 Session 2Session 2 Session 3Session 3

Test timeTest time

t1t1

t3t3

t5t5

t2t2

t6t6 t4t4

Session 1Session 1 Session 2Session 2 Session 3Session 3

Test schedulingTest scheduling

with equal length testswith equal length testsTest schedulingTest scheduling

with unequal length testswith unequal length tests

Test timeTest time

t1t1

t3t3

t5t5

t2t2

t6t6 t4t4

Better solutionBetter solution

For unequal length testsFor unequal length tests


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Literature Review: Power constrained Test schedulingLiterature Review: Power constrained Test scheduling

SolutionsSolutions:: Chou et al. (TCAD97)Chou et al. (TCAD97)

Graph-based heuristicGraph-based heuristic

Iyengar et al. (TCAD02)Iyengar et al. (TCAD02)

Mixed Integer Linear ProgrammingMixed Integer Linear Programming

Zhao et al. (TCAD05)Zhao et al. (TCAD05)

Rectangle packing heuristicRectangle packing heuristic

GoalGoal:: Minimize total test time underMinimize total test time underresourceresource andand powerpowerconstraintsconstraints

t1t1

t2t2

t4t4

t3t3

t5t5

t6t6

22

44

33

22

11

22

PPmaxmax == 55

XX

Source: Zhao et al. TCAD05Source: Zhao et al. TCAD05

Power limitPower limit


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Literature Review: Thermal constrained Test schedulingLiterature Review: Thermal constrained Test scheduling

SolutionsSolutions:: Rosinger et al. (DATE05, TCAD06)Rosinger et al. (DATE05, TCAD06)

Liu et al. (DFT05)Liu et al. (DFT05)

Generate solutions of power constrained test scheduling first, then modified byGenerate solutions of power constrained test scheduling first, then modified by

thermal constraintthermal constraint

He et al. (DFT06, ITC07, ATS08)He et al. (DFT06, ITC07, ATS08)

Test set partitioning and interleavingTest set partitioning and interleaving

Constraint logic programmingConstraint logic programming

Bild et al. (ICCAD08)Bild et al. (ICCAD08)

Simplified thermal modelSimplified thermal modelMILP formulationMILP formulation

Seed-based clustering heuristicSeed-based clustering heuristic

GoalGoal:: Minimize total test time underMinimize total test time underresource, powerresource, powerandand thermalthermal constraintsconstraints


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Test scheduling: Our solutionTest scheduling: Our solution

Thermal-aware test scheduling (ITC09)Thermal-aware test scheduling (ITC09) SuperpositionSuperposition principle to compute thermal profileprinciple to compute thermal profile

SchedulingScheduling algorithmalgorithm

Experimental resultsExperimental results

Partition-based thermal-aware test scheduling (ATS09)Partition-based thermal-aware test scheduling (ATS09)

Power modelPower model TestTest partitionpartition

Experimental resultsExperimental results

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