Voice CODEC for wireless communicationsLow Power 13 bit DAC

Pedro Ribeiro Braga

Dissertacao para obtencao do Grau de Mestre emEngenharia Electrotecnica e de Computadores

JuriPresidente: Prof. Nuno Cavaco Gomes HortaOrientador: Prof. Marcelino Bicho dos SantosCo-Orientador: Profa. Maria Beatriz Mendes Batalha Vieira Vieira BorgesVogal: Prof. Jorge Ribeiro Fernandes

Setembro de 2009

Acknowledgments

I would like to begin by thanking my advisor, Professor Marcelino Santos, and co-Advisor,

Professor Beatriz Borges, for their guidance and insight during this project.

A big thanks goes to the team that worked directly on this Voice CODEC project: Alexandre

Neves, Edgar Albuquerque and Pedro Oliveira. Their help and discussions taught me a lot and

made progress in the work much easier. I also have to thank the people at Inesc-ID and Silicon-

Gate for receiving me and helping through this effort, particularly Jose Proenca, Angelo Monteiro

and Gabriel Santos.

A thanks also goes to all my friends that accompanied me through all ups and downs of college

and life.

My deepest thanks go to my parents and brother for their unconditional support and encour-

agement throughout my whole life.

Finally to express my gratitude for the support and patience of my girlfriend Silvana.

Abstract

Wireless communications are a very large and competitive market. Very high volume produc-

tion means that all gains in consumption and area without degrading performance are important.

Evolution impacts portable devices that will see their autonomy and size/cost, both very important

features for the final costumer, affected by these efficiency improvements.

This work presents a voice DAC designed to be integrated in a CODEC for wireless commu-

nications. The full system encompasses a voice ADC and DAC (both Sigma-Delta converters),

signal conditioning from the ADC input and a driver for the DAC output plus all power management

(supply and references voltages and bias currents).

The work here presented is specially focussed on the DAC, both the digital, interpolator and

sigma-delta modulator, and analogue blocks, reconstruction filter and buffer. The DAC has a

resolution of 13 bit (80dB) and is geared to low power and area since it is intended for portable

devices. A third order 3 bit Sigma-Delta modulator is used with an oversampling ratio (OSR) of

64, giving a sampling frequency of 1MHz for the 16kHz input sampling. A Direct Charge Transfer

(DCT) switched capacitor filter is used for the signal reconstruction. The circuit is designed on

130nm standard CMOS technology with a 3.0V/1.2V supply. This enabled an area of 0.3mm2

and consumption of 400µA.

Keywords

Voice CODEC, Digital to Analogue Converter, Sigma-Delta Modulation, Low-Power, Switched

Capacitor Filter, Direct Charge Transfer.

iii

Resumo

As comunicacoes sem fios sao um mercado grande e competitivo. Com uma producao em

grande volume, onde qualquer ganho em consumo ou area, sem prejudicar a performance, e

muito importante. A evolucao permite que os dispositivos portateis vejam a sua autonomia e

tamanho/custo, ambos parametros muito importantes para o consumidor final, afectados pelos

ganhos em rendimento.

Este trabalho apresenta o projecto de um DAC para voz, que se destina a ser integrado

num CODEC para comunicacoes sem fios. O sistema completo e constituıdo por: ADC e DAC

para voz (ambos conversores Sigma-Delta), condicionamento de sinal para a entrada do ADC e

um driver para a saıda do DAC, alem de todo o controlo de potencia (alimentacao, tensoes de

referencia e correntes de polarizacao).

O trabalho aqui apresentado foca-se no DAC, tanto nos blocos digitais, interpolador e mod-

ulador sigma-delta, como blocos analogicos, filtro de reconstrucao e buffer. O DAC tem uma

resolucao de 13 bit (80dB) com baixa area e potencia uma vez que se destina a dispositivos

portateis. E usado um modulador Sigma-Delta de 3a ordem com 3 bit e um oversampling (OSR)

de 64, ou seja uma frequencia de amostragem de 1MHz para os 16kHz de amostragem da

entrada. A reconstrucao do sinal e feita com um filtro de condensadores comutados com uma

arquitectura do tipo Transferencia Directa de Carga. O circuito foi projectado numa tecnologia

CMOS standard de 130nm com 3.0V/1.2V de alimentacao. A escolha desta tecnologia permitiu

alcancar uma area abaixo dos 0.3mm2 e um consumo de 400µA.

Palavras Chave

CODEC de Voz, Conversor Digital Analogico, Modulacao Sigma-Delta, Baixa Potencia, Filtro

de Condensadores Comutados, Transferencia Directa de Carga.

v

Contents

1 Introduction 1

1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.2 Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.3 Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 State of the Art 5

2.1 Interpolation Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2 Σ∆ Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.3 DAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.3.1 DEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.3.1.A Random Scrambling . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.3.1.B Data Directed Scrambling . . . . . . . . . . . . . . . . . . . . . . . 15

2.3.2 Reconstruction Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.4 Synopsis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3 Voice DAC Design 23

3.1 Architecture Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.2 Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.2.1 Interpolator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.2.2 Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.2.3 DEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.2.4 Direct Charge Transfer DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.2.4.A Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

3.2.4.B Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.3 Synopsis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

4 Simulation Results 39

4.1 Interpolation and Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

4.2 Analogue filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

4.2.1 Switches and Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

vii

Contents

4.2.2 Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

4.3 Synopsis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

5 Layout 53

5.1 DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

5.2 CODEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

6 Conclusions 59

6.1 Summary and Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

6.2 Future work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

A Audio and Voice 67

B Noise 71

C Switched Capacitors 75

D Circuit Schematics 81

viii

List of Figures

1.1 Audio reproduction channel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2.1 Simple diagram of a DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.2 Data converters Bandwidth Resolution tradeoff. . . . . . . . . . . . . . . . . . . . . 6

2.3 Simple diagram of a Σ∆ DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.4 Quantization noise power spectral density for Nyquist rate and oversampled con-

version. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.5 Halfband filter response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.6 Delta, Sigma and Delta-Sigma modulations. . . . . . . . . . . . . . . . . . . . . . . 8

2.7 Quantization noise power spectral density with and without noise shaping. . . . . . 9

2.8 Single bit and Multi bit quantization examples. . . . . . . . . . . . . . . . . . . . . . 10

2.9 A modulator example with dither. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.10 Quantizer types: mid-rise (even number of levels) and mid-thread (odd number of

levels). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.11 Reconstruction filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.12 Anti-Imaging filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.13 Example of 3 bit thermometer encoded DAC. . . . . . . . . . . . . . . . . . . . . . 13

2.14 Example of 3 bit thermometer code. . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.15 Scrambling effect on noise. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.16 Example of 3 bit butterfly network. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.17 Example of a 3 bit Galton tree. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.18 Example of segmented DEM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.19 Example of a noise shaped segmented DEM. . . . . . . . . . . . . . . . . . . . . . 17

2.20 Example of settling time and glitch. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.21 Example of RTZ code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.22 Example of Dual RTZ code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.23 Second order demodulator with single amplifier. . . . . . . . . . . . . . . . . . . . . 19

2.24 Example of a 5 bit DCT analog DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.25 Example of a Class D amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

ix

List of Figures

3.1 SNR limits for binary low pass Σ∆ modulators. . . . . . . . . . . . . . . . . . . . . 24

3.2 SNR vs number of bits vs OSR for a second order modulator. . . . . . . . . . . . . 25

3.3 SNR vs number of bits vs OSR for a third order modulator. . . . . . . . . . . . . . . 26

3.4 Block diagram of a digital modulator. . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.5 Digital Σ∆ modulator architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.6 Simple DCT stage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.7 DCT DAC schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.8 DCT sampling capacitors array. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.9 NMOS switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

3.10 CMOS switch and its equivalent RON . . . . . . . . . . . . . . . . . . . . . . . . . . 34

3.11 Simple amplifier model schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.12 Simple schematic of current mirror OTA. . . . . . . . . . . . . . . . . . . . . . . . . 36

3.13 Switched common mode feedback. . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3.14 OTA mirror schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.15 buffer amplifier schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

4.1 Input and output signals of the modulator. . . . . . . . . . . . . . . . . . . . . . . . 41

4.2 Power Spectral Density of modulator input. . . . . . . . . . . . . . . . . . . . . . . 41

4.3 Power Spectral Density at modulator output. . . . . . . . . . . . . . . . . . . . . . . 42

4.4 DCT DAC schematic, with ideal components. . . . . . . . . . . . . . . . . . . . . . 43

4.5 Ideal DCT output transient analysis and PSD . . . . . . . . . . . . . . . . . . . . . 44

4.6 Continuous CMFB for AC open loop response simulations of the amplifier. . . . . . 46

4.7 AC open loop response of the amplifier in all corners. . . . . . . . . . . . . . . . . 47

4.8 Phase margin and GBW of the amplifier in all corners. . . . . . . . . . . . . . . . . 47

4.9 Output buffer PSD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

4.10 Real DCT output transient analysis and PSD. . . . . . . . . . . . . . . . . . . . . . 49

4.11 DAC output with buffer PSD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

5.1 Layout of the OTA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

5.2 Floor plan of the DCT filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

A.1 Human sound sensitivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

A.2 Example of a Digital/Analogue interface transfer function. . . . . . . . . . . . . . . 69

A.3 SNR versus input amplitude. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

B.1 Circuit elements and their noise models. Note that capacitors and inductors do not

generate noise. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

B.2 Switched capacitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

x

List of Figures

C.1 Basic switched capacitor (a) and its equivalent resistance (b). . . . . . . . . . . . . 76

C.2 Effect of charge injection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

C.3 Clock feedtrough in a sampling circuit. . . . . . . . . . . . . . . . . . . . . . . . . . 77

C.4 CMOS switches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

C.5 Addition of dummy switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

C.6 Example of bottom plate sampling, or delayed phases. . . . . . . . . . . . . . . . . 79

D.1 Schematic of the testbench for a DCT filter with ideal components. . . . . . . . . . 82

D.2 Schematic of an ideal amplifier model with configurable gain and bandwidth . . . . 83

D.3 Schematic of a dummy switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

D.4 Schematic of a CMOS switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

D.5 Schematic of the testbench for dummy and CMOS switches. . . . . . . . . . . . . 85

D.6 Schematic of the testbench for the DCT filter with output buffers. . . . . . . . . . . 86

D.7 Schematic of the DCT filter with output buffers. . . . . . . . . . . . . . . . . . . . . 87

D.8 Schematic of the the sampling capacitor array of the DCT filter. . . . . . . . . . . . 88

D.9 Schematic of the current mirror OTA, main amplifier block. . . . . . . . . . . . . . . 89

D.10 Schematic of the current mirror OTA, half the CMFB block (the half simplifies layout). 90

D.11 Schematic for the test bench to measure the AC open loop response of the OTA. . 91

D.12 Schematic of the output buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

xi

List of Figures

xii

List of Tables

1.1 Voice DAC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

3.1 Modulator specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.2 Digital Σ∆ modulator coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.3 Capacitor values for different SNRs, with a 0.5V pp signal. . . . . . . . . . . . . . . 30

4.1 Comparison between CMOS and dummy switches. Ron is the resistance of the

switch when turned on. Ip is the current peak in the commutations, representing a

measure of how much charge is injected. . . . . . . . . . . . . . . . . . . . . . . . 45

4.2 Corner variables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

xiii

List of Tables

xiv

List of Acronyms

Σ∆ - Sigma-Delta Modulator/Modulation

ADC - Analogue to Digital Converter

CIC - Cascaded Integrator Comb

CMFB - Common Mode FeedBack

CMOS - Complementary Metal Oxide Semiconductor

DAC - Digital to Analogue Converter

DCT - Direct Charge Transfer

DEM - Dynamic Element Matching

DR - Dynamic Range

DWA - Data Wheighted Averaging

ENOB - Efective Number Of Bits

FFT - Fast Fourier Transform

FIR - Finite Impulse Response

FS - Full Scale

GBW - Gain-Bandwith product

IC - Integrated Circuit

LSB - Least Significant Bit

MSB - Most Significant Bit

NTF - Noise Transfer Function

OSR - Oversampling Ratio

PCM - Pulse Code Modulation

PWM - Pulse Width Modulation

RMS - Root Mean Square

SC - Switched Capacitor

SINAD or SNDR - Signal to Noise And Distortion Ratio

SNR - Signal to Noise Ratio

SQNR - Signal to Quantization Noise Ratio

SR - Slew Rate

STF - Signal Transfer Function

xv

List of Acronyms

THD - Total Harmonic Distortion

THD+N - Total Harmonic Distortion plus Noise

xvi

1Introduction

Contents1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.2 Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.3 Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1

1. Introduction

1.1 Motivation

Wireless communications are an incredibly vast area as most of our communications today

are wireless (telephone and internet). Most systems can benefit from complex signal processing

which is much easier in the digital domain through Digital Signal Processors (DSP). However,

since analogue signals are required for input and output, as our voice and hearing is analogue,

there has to be an interface at both input, Analogue to Digital Conversion (ADC), and output,

Digital to Analogue Conversion (DAC), of the signal / voice.

Therefore, this thesis is focused in the design of a complete Voice CODEC for wireless com-

munications. The full circuit comprises the codification of an analogue (voice) signal to digital

and its decodification back to analogue. Portable systems need to be small, with low area and

small batteries to power them. Having this in mind the CODEC should reach the desired perfor-

mance/quality with as few power as possible.

The Voice CODEC was designed at Inesc-ID in collaboration with Silicon Gate.

1.2 Objectives

The main purpose of this work is to contribute for the design and implementation of a complete

Voice CODEC for wireless applications. This includes a recording channel (signal conditioning

and ADC) and the playback channel (DAC and driver) and all the associated power management,

clock generation and interface circuitry. Since the target are portable voice devices, low power is

essential.

This dissertation is focussed on the project of the playback channel which is composed of two

main blocks: a digital to analogue data converter and a power amplifier, as seen in Figure 1.1.

Figure 1.1: Audio reproduction channel.

The audio DAC converts the Pulse Code Modulated (PCM) data from the Decoder to an ana-

logue signal that will feed the amplifier. This conversion needs high quality to meet high fidelity

audio requirements. The power amplifier will enable the analogue audio signal to have the nec-

essary strength to drive the loudspeaker, headphone or line out.

The objective of this work is to design the Voice DAC and to implement it in UMC 130nm

CMOS process.

2

1.3 Outline

The Voice DAC should have a resolution of 13 bit @ 16kHz and comply with the specifica-

tions shown in Table 1.1. The supply voltages are fixed by the target technology, at 3.0V for

the analogue and 1.2V for the digital, these were considered to have a 10% variation. The final

load should be 1kΩ and 20pF (line output) but the DAC will only “see” the driver input with high

impedance (open circuit).

Table 1.1: Voice DAC specificationsParameter Min Typ Max

Analog Supply 2.7V 3.0V 3.6VDigital Supply 1.08V 1.20V 1.32V

Load − 1kΩ and 20pF -Full Scale input range 1.8V 2V 2.2V

SNR 70dB 80dB −THD 60dB 70dB −

Analog Current − − 1mADigital Current − − 3mA

Area − − 0.8mm2

1.3 Outline

This dissertation is organised in six Chapters and four Appendixes.

The second Chapter, State of the Art, presents and discusses current solutions used in the

playback channel of CODECs, evaluating their value in this application.

In the third Chapter, Design of the Voice DAC, a solution is selected demonstrating what

makes it the best for the application. All details and design of the proposed solution are explained.

The fourth Chapter, Simulation Results, explains how performance and parameter measure-

ments of the circuit were obtainned and presents all simulation results.

In the fifth Chapter, Layout, layout concerns are presented as well as their solutions in the

floor plan and routing of the circuits.

The sixth Chapter, Conclusions, summarises all the work and highlights achievements. This

chapter also discusses what could be done in the future to improve this part of the CODEC.

Finally the four Appendixes: Audio and Voice, Noise, Switched Capacitors and the Circuit

Schematics. Audio and Voice explains basic audio concepts and important parameters, dis-

cusses human voice and hearing as well as A-weighting and audio/voice standards. Appendix

Noise explains noise problems in CMOS circuits and presents important tradeoffs. The next Ap-

pendix, Switched Capacitors, explains the most important characteristics of switched capacitor

circuits, implementation problems and their solutions. The last Appendix, Circuit Schematics,

presents schematics of all blocks and their test benches.

3

1. Introduction

4

2State of the Art

Contents2.1 Interpolation Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72.2 Σ∆ Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82.3 DAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112.4 Synopsis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5

2. State of the Art

The basic Digital to Analogue Converter structure is shown in Figure 2.1.

Figure 2.1: Simple diagram of a DAC.

The audio DAC has to have a high resolution, at least 16 bits, to achieve the required high

fidelity audio quality, a little less for voice, 13-14 bits. However, the audio signal bandwidth is

relatively small, 20 − 24kHz. Σ∆ DACs are the most used converters for these applications as

their characteristics fit the requirements for audio signals perfectly [1], as seen in Figure 2.2.

Figure 2.2: Data converters Bandwidth Resolution tradeoff.

In Figure 2.3, the basic structure of a Σ∆ DAC is shown, with the three main blocks being the

interpolation filter, the delta-sigma modulator (DSM) and the DAC interface. The DAC interface

does the sampling of the Σ∆ bitstream followed by a low-pass/reconstruction filter that produces

an analogue signal. This reconstruction filter also returns the signal to the original sampling

frequency (or rhythm), to do so it must also cancel the over sampled signal images, working as a

anti-imaging filter.

Figure 2.3: Simple diagram of a Σ∆ DAC.

Σ∆ data converters achieve their high resolution trough oversampling, in the interpolation filter,

6

2.1 Interpolation Filter

and noise-shaping techniques, in the Σ∆ modulator. These two blocks compose the digital part of

the DAC, the analogue is the DAC interface. Each block is analised and explained in the following

sections.

2.1 Interpolation Filter

The oversampling in the interpolation filter allows the reduction of the noise floor by spreading

the quantization noise over a wider bandwidth, since this does not increase the total noise, the

noise in the signal bandwidth is reduced as represented in Figure 2.4 [2].

Figure 2.4: Quantization noise power spectral density for Nyquist rate and oversampled conver-sion.

An additional advantage of the digital filter is to remove images above half the oversampled

frequency. Since this requires a high order filter, it is usually done in stages to reduce the circuit

complexity. The prefered filters are Finite Impulse Response (FIR) so that a linear phase can be

obtained, and as efficent as possible. Implementations for audio [3] [4] use halfband filters, for a

2x interpolation each, and a final sinc filter, for a higher 4x/8x interpolation. The half band filters

have a frequency response, as seen in Figure 2.5, with a odd symmetry around the midway point,

between zero and the Nyquist frequency (π

2,H(1)

2), hence their name. This symmetry avoids the

use of multiplications as the coefficients are powers of 2, or very close to those, and enables the

use of shifts and sums to preform multiplications. The other interesting feature is the fact that all

even samples, except n = 0, have a null value which severely reduces the calculations.

The sinc filter is implemented with Cascaded Integrator Comb (CIC) filters. CIC filters are

simpler for higher interpolation factors, when compared to the equivalent FIR filter, and enable

simple reconfiguration of the interpolation factor, though their response is more limited. As such

CIC filters are suited to implement the final stages of the interpolation block were high interpolation

is needed but more selective filtering has already been done in the early (FIR) stages [5].

7

2. State of the Art

Figure 2.5: Halfband filter response.

2.2 Σ∆ Modulator

The quantization error can be considered noise, and that is the way it is frequently modelled

[6]. The Σ∆ modulator performs the noise-shaping which provides the signal a low pass transfer

function, Signal Transfer Function. Noise in the Σ∆ modulator is shaped by a high pass Noise

Transfer Function. This modulation can be seen as the combination of a loop filter with a quantizer

(delta) and a compensation for the shaping of the signal (sigma) in a single filter (delta-sigma), as

seen in Figure 2.6. Alternatively, one can see it as the integration (sigma) of the difference (delta)

which is the output signal, and hence the sigma-delta name.

Figure 2.6: Delta, Sigma and Delta-Sigma modulations.

The delta-sigma modulator transfer function, considering both the signal and error [7], shown

in (2.1), can be splited in the Signal Transfer Function (STF), (2.2), and Noise Transfer Function

(NTF), (2.3).

Y = XH(Z)

1 +H(Z)+ E

11 +H(Z)

(2.1)

8

2.2 Σ∆ Modulator

STF =H(Z)

1 +H(Z)(2.2)

NTF =1

1 +H(Z)(2.3)

The noise shaping effects are presented in Figure 2.7, where the inband noise reduction is

clearly visible, the high pass NTF pushes the noise to higher frequencies. The order of the loop

filter/modulator determines how agressive will the noise shaping be.

Figure 2.7: Quantization noise power spectral density with and without noise shaping.

By allowing the signal to pass unaltered, as long as the low pass cut-off frequency is high

enough, and attenuating the noise in the signal/interest band a significant Signal to Noise Ratio

(SNR) increase is achieved. As a consequence, an higher resolution is also obtained, usually

translated to the number of bits trough the equation (2.4).

SNRdB = 6.02×N + 1.76 (2.4)

As seen, the resolution of the DAC can be improved by increasing the oversampling ratio

and/or the modulator order. However, this increase brings some problems in both cases. When

increasing the oversampling the circuits must withstand the higher working/sampling frequency

without significantly degrading the signal. Increasing the modulator order means adding integra-

tors in the loop which makes the circuit more complex, and for orders greater than the second,

stability becomes an issue. One frequently used way to control stability is using damped filter

coefficents in the loop. Alternatively, the modulator can have cascaded loops, this still results in a

complex circuit, but if all the loops are of second or lower order the stability is ensured.

If we take distortion into account, we must use the Signal to Noise And Distortion Ratio

(SINAD) instead of SNR and thus obtain the Effective Number Number Of Bits (ENOB). ENOB is

the realistic measure of the modulator resolution, but for early project/design stages, usually SNR

is used to simplify the initial approach.

Another stability problem arises if overload occurs, which is very common in single bit quan-

tizers. Multi bit quantizers are less prone to overload and are more stable, an important factor

9

2. State of the Art

for modulator orders higher than 2, whose stability is not ensured. Multi bit modulators, however,

are less linear than single bit. This disadvantage is limited using with Dynamic Element Matching

(DEM) by making errors independent from the input signal but at the cost of increased complexity.

The employed algorithms average the errors to reduce their impact, by randomization (distortion

transforms into white noise), rotation (distortion moves out of band) or even mismatch-shaping

(1st/2nd order). DEM is described in detail ahead in section 2.3. Multi bit modulators are also

less sensitive to jitter, because the voltage steps are smaller. The use of more more bits provides

better resolution and can be used/seen as a way to reduce the Over Sampling Ratio (OSR) and

thus alleviate circuit/filtering specifications. Figure 2.8 illustrates both quantisations [8].

Figure 2.8: Single bit and Multi bit quantization examples.

Most quantizers present spikes, above the noise floor in their spectrum, called idle tones,

caused by a small DC or low amplitude tone input. The idle tone amplitude is proportional to

the frequency and amplitude of the input signal, and inversely proportional to the modulators

order. Idle tones energy is low and does not affect SNR but in audio they can produce audible

artefacts for small/weak signals, making them extra audible and thus they need to be addressed.

The solutions can be: the introduction of dither, the use of local feed back or feed forward, multi

bit quantisation and filtering at modulator output. Dither is the simpler. It consists in inserting a

pseudo-random signal in the quantizer input or output to make it more random maintainning the

same average value of the original signal. The dither signal is produced by a Pseudo-Random

Sequence Generator (PRSG), usually implemented through a Linear Feedback Shift Register

(LFSR) circuit [9], and then summed with the quantizer input. The sum can be weighted by a gain

and the dither filtered out of the audio band as done in the third order 5 bit, modulator of Figure

2.9 from [4].

While the white noise introduced by dither increases the noise floor and thus lowers the Dy-

namic Range (DR) in the quantizer, the overall DR is improved. Note that the DAC modulator is

completely digital so the integrators are accumulators, implemented with adders and multipliers,

and the quantization is done with bit truncation. The multi bit quantizers number of levels, or more

precisely whether that number is even or odd, determines its type, mid-rise or mid-thread [7],

respectively, as seen in Figure 2.10.

For audio applications, the mid-thread is preferable, as it has the zero level which is important

10

2.3 DAC Interface

Figure 2.9: A modulator example with dither.

Figure 2.10: Quantizer types: mid-rise (even number of levels) and mid-thread (odd number oflevels).

for the moments of silence. The mid-rise will always introduces noise which will be very audible

for low amplitude signals.

A digital filter at the modulator output, introducing a zero, helps attenuate high frequency noise

and idle tones, it also reduces sensitivity to jitter [4].

2.3 DAC Interface

The DAC interface samples the modulator output bit stream and then uses a low pass/anti-

imaging filter to return the modulator bit stream to the analogue domain a reconstruction filter, as

seen in Figure 2.11, is used.

The images from the sampling are removed by an Anti-Imaging filter, in this case a low pass,

like the one in Figure 2.12 is used.

Both filters can be implemented as single analogue filter. Each quantization level will be sam-

pled by a sample and hold block and all levels are summed to obtain the complete sample value.

This circuit can be either implemented in continuous-time, active RC filters also called current

steer, or in switched capacitor technology. While both are sensitive to noise, in their reference

voltage and power supply, the current steer is also more sensitive to jitter.

For this application, switched capacitor is preferred as it presents a reduced sensibility to clock

11

2. State of the Art

Figure 2.11: Reconstruction filter.

Figure 2.12: Anti-Imaging filter.

12

2.3 DAC Interface

jitter and better component value accuracy (good capacitor matching), using standard CMOS

technology. Switch Capacitor (SC) circuits, however, require large capacitances for high perfor-

mance, due to signal-dependent charge injection and kT/C noise. Large capacitors are harder

to drive, requiring large currents and also much area. Switching frequencies force larger Band

Width (BW) for the amplifiers and care must be taken with their noise as it aliases in the signal

band.

Continuous time circuits, while not having any charge injection and alleviating amplifiers spec-

ifications, suffer with more jitter and inaccurate RC time constants, though here high performance

comes from small resistor rather than large capacitors [7], [8]. All this makes their frequency

response more inaccurate. The Digital/Analogue interface is also more complicated than in SC.

The Digital/Analogue interface must have a resolution of 16-24 bit since its errors are not

shaped. This means that the static and dynamic characteristics must have little error and good

linearity.

Static errors come from gain and offset in the transfer function. Static Non-linearity is usually

measured trough the Differential Non-linearity Error (DNL), for small signal, and the Integral Non-

linearity Error (INL), for strong signals. Achieving a good value of static error is difficult due to

component mismatch, especially with multi bit quantizers/signal. In a binary DAC, the 2N (from N

bits) elements size is scaled as 2i, with i going from 0 to N. As 2N quickly grows so will the ratio

and thus the difficulty of having a good matching. For high resolution converters, the converter is

often implemented as a unit-element DAC. The binary number is decoded to thermometer code

representation and fed to 2N−1 equal unit elements, as seen in Figure 2.13.

Figure 2.13: Example of 3 bit thermometer encoded DAC.

The thermometer code, as shown in the Figure 2.14 example, enables all the levels to be

equally weighted.

Using this approach, means each level can be assigned to any DAC element but any analogue

mismatch between elements can still cause noise and distortion. The solution for this problem is

13

2. State of the Art

Figure 2.14: Example of 3 bit thermometer code.

presented in the next Section.

2.3.1 DEM

In order to solve the analogue mismatch problem in the DAC, Dynamic Element Matching

(DEM) is used, taking advantage of the equal weights to scramble de assignment of the bits to

DAC elements. If done randomly, the selection of bit units will turn the DAC errors into white noise,

but if done in a data directed fashion, it enables the shaping of this noise. Figure 2.15 illustrates

the impact of using DEM [8].

Figure 2.15: Scrambling effect on noise.

14

2.3 DAC Interface

2.3.1.A Random Scrambling

Random Scrambling of the elements can be achieved with a butterfly network, also called

butterfly shuffler as the one in Figure 2.16 [8], with a pseudo random number generator to make

the routing decision at each block. This makes the errors independent from the signal and the

mismatch distortion is turned into white noise. The butterfly network will also cancel tones since

it increases the noise floor.

Figure 2.16: Example of 3 bit butterfly network.

Clock Level Averaging (CLA) is an alternative technique to implement random scrambling

where elements are sequentially selected and permuted at each clock cycle in a periodic fashion.

This approach is still signal independent but just moves the distortion to a higher frequency without

increasing the white noise. The non linearity becomes a periodic signal at fs/N . For typical

process mismatch, around 0.1%, and normal number of bit and OSR these techniques are limited

to resolutions below 16 bit, making them not suitable to this circuit [10].

2.3.1.B Data Directed Scrambling

Data Directed Scrambling enables a highly desirable, even more so in oversampled systems,

mismatch high pass shaping by replacing the random number generator with a algorithm to chose

the elements based on the signal.

Individual Level Averaging (ILA) selects the elements sequentially for any code, so each

element is used with the same probability. For a DC input is the same as CLA.

Data Weighted Averaging (DWA) is less complex than ILA. Depending on the selected code

a cumulative error occurs. The goal is to reduce the error to zero. That will only happen when

all codes have been selected the same number of times. DWA gives a 1st order noise shap-

ing of DAC errors but is susceptible to idle tones, as occurs in 1st order Σ∆ modulators. Some

randomized variations of DWA solve the idle tones by not making the selection in a rotational fash-

ion. While keeping the DWA idea of never choosing the same code until all others are selected.

15

2. State of the Art

These are mainly divided between tone suppressing and tone transferring techniques. Group-

level averaging (GLA), Rotated DWA (RDWA), Bi-directional DWA (BiDWA), Randomized DWA

(RnDWA), Partitioned DWA (P-DWA) and pseudo DWA are all tone suppressing techniques that

can suppress the power of baseband tones but raise the baseband noise floor [8]. Tone transfer-

ring techniques like Incremental DWA (IDWA), partial DWA and the offset technique can transfer

much of the mismatch noise power to tones outside the baseband, achieving lower baseband

noise power and better SNDR performance than those of tone-suppressing techniques. However,

when the input signal has a DC component, tone-transferring techniques may cease to function

properly. There is also advancing DWA (ADWA) which is a flexible technique that can achieve

both tone-suppressing and tone-transferring functions [11]. More complex versions of DWA also

exist that provide 2nd order noise shaping, sometimes called R2DWA, and proposals for arbitrary

order [10].

A very hardware efficient realization of dynamic element matching is the tree structure pro-

posed by Galton [12]. This structure is presented in the example of Figure 2.17 showing the layers

of switching blocks to control each DAC element. Note that the structure of Figure 2.17 can be

used with any number of bits. The switching blocks can generate 1st or 2nd order noise shaped

sequences using structures similar to Σ∆ modulators but without input sequences. Therefore,

the integrator input will be small and with appropriate initial conditions always bounded, As a

consequence, the structure can rely on low bit-width registers and arithmetic.

Figure 2.17: Example of a 3 bit Galton tree.

There is also the vector feedback approach or mismatch-shaping [13] which has very good

16

2.3 DAC Interface

performance for even second order mismatch shaping, but requires complex hardware making it

unattractive for a large number of quantization levels.

For large quantizers, typically above 4-5 bit, the DEM complexity becomes a serious problem

and it is usually resolved by segmentation, as shown in Figure 2.18 [8].. However, simply splitting

the DAC in 2 or more smaller ones and applying DEM to each of them will result in mismatch, as

the gain error between each one will not be shaped. To address the mismatch, the splitting must

be done with a noise shaped structure as shown in Figure 2.19 though at cost of more analogue

circuitry [8].

Figure 2.18: Example of segmented DEM.

Figure 2.19: Example of a noise shaped segmented DEM.

A PWM approach with predistortion and DEM is presented in [14] with good results.

Dynamic errors in the DAC come from the settling time to a specified error and glitches. Figure

2.20 represents graphically the settling time. The settling time is here defined as the time (or

percentage of the period) it takes for the DAC value to be within 5% of the desired final value.

Asymmetrical rise and fall times are also a problem as they cause harmonic distortion for high

frequency signals. These errors are evaluated with: SNR, SINAD, SFDR, THD and ENOB, all of

17

2. State of the Art

these parameters are explained in appendix A.

Figure 2.20: Example of settling time and glitch.

Even with good settling time, slow transition times, 0 → 1 or 1 → 0, will lead to Inter Symbol

Interference (ISI). One possible solution to ISI is to use Return To Zero (RTZ), it simply resets the

DAC at every new set of data, as seen in Figure 2.21. This reduces ISI but demands to double

the settling time, as the signal only has half the period to settle, and worsens the jitter effect (2×

more transitions).

Figure 2.21: Example of RTZ code.

Another possibility is to use dual RTZ by doubling the hardware and having each DAC working

in opposite phase, as shown in Figure 2.22 [8].

2.3.2 Reconstruction Filter

The analogue DAC has the sampling blocks feeding their values to a low pass SC filter [4]. The

filter order should equal the modulators order (N) + 1, thus using N+1 amplifiers. While assuring

good filtering of the out of band noise (mostly from quantization) which benefits the output SNR,

this solution has a large analog circuitry that increases in-band noise (1/f and thermal) that

reduces DR. In essence, a large output SNR requires a higher order filter that will reduce both DR

18

2.3 DAC Interface

Figure 2.22: Example of Dual RTZ code.

and THD as well as increase the power consumption. Therefore, ideally, no filter would be used.

In practice, a 1storder filter is used for large DR DACs.

A solution to minimise this problem is presented in [15], a 2ndorder demodulator using a single

amplifier is shown. With this solution only one amplifier is needed to have a biquadratic section.

Such section is shown in Figure 2.23, the DC gain is controlled by the ratio C1/C3 and the poles

by capacitors C2 and C3 for the 1stpole, capacitors C4 and C5 for the 2ndpole.

Figure 2.23: Second order demodulator with single amplifier.

The alternative is the Direct Charge Transfer (DCT) approach that achieves good results only

using 1storder filtering (and thus only one amplifier), as seen in Figure 2.24 [3] [16]. To compen-

sate the 1storder and improve jitter tolerance, a FIR filter is used at the input of the analogue block,

19

2. State of the Art

this is simple as the signal there is a digital word and only sums and delays are needed. Such a

solution enables an implementation with significantly less area and power, wich are vital resources

for portable applications. The DCT topology also eliminates spikes originated by slew-rate limi-

tation. However, it is only suited for multibit modulators as it only provides 1storder, low pass

filtering. For singlebit modulators the bitstream lower harmonics are not sufficiently attenuated.

Figure 2.24: Example of a 5 bit DCT analog DAC.

After the DAC interface, an amplifier is necessary to drive the typical loads for audio and voice:

speakers (4−8Ω and 100pF ), headphones (16−32Ω and 100pF ) and line (7−10kΩ and 1000pF ).

This is usually done with a class AB amplifier for better quality or a class D for high efficiency

(around 90%) at the sacrifice of some quality, mostly linearity [2]. Another option is class G, were

power supply is adjusted to have a class AB amplifier always using its full swing and hence work

at the maximum efficiency (78.5%). In this application, however, the class D would be the most

interesting solution has it can provide good quality for voice and have a very good efficiency thus

enabling significantly longer battery life. Figure 2.25 illustrates the basic, PWM modulated, Class

D amplifier [17]. This block is analysed in [18] [19] [20].

2.4 Synopsis

A review of the state of the art techniques for audio and voice DACs shows that Σ∆ converters

are by far the best suited to the high resolution and low bandwidth specifications. Such a converter

needs aa interpolation filter to provide the necessary oversampling of the input signal. For audio

and voice, the oversampling factor is usually high (64 to 256 times the Nyquist frequency) and

consequently a multistage filter should be used. This filter needs a linear phase response for the

voice/audio application and therefore a FIR is used. The modulator must have at least a second

order structure to meet the resolution specification. The trade off is between extra complexity

and performance plus the need to study the stability for orders higher than 2. This stability can

20

2.4 Synopsis

Figure 2.25: Example of a Class D amplifier.

be controlled by the gains and by using a multi bit structure, that also improves performance.

However, multi bit introduces non linearity which must be reduced by a DEM circuit to scramble

the thermometer code output. Some complexity is added but still in the digital part of the converter

which represents lower back end costs since the layout can be designed automatically. Finally the

analogue output filter that must reconstruct the signal and filter out the high frequencies should

be SC and retain the linear phase in the signal band. A DCT structure was found appropriate for

multi bit modulators.

21

2. State of the Art

22

3Voice DAC Design

Contents3.1 Architecture Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243.2 Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263.3 Synopsis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

23

3. Voice DAC Design

The design of the playback channel for the Voice CODEC is divided in two main blocks: the

digital filter (interpolator and the digital Σ∆ modulator) and the analog output filter. They will also

be treated separately though having in mind that the analogue will load the digital. In both blocks

a top down approach is taken, starting with simple models to evaluate the architecture. Based

on the architecture, the circuit is simulated with ideal blocks where non idealities are introduced,

progressively, moving closer to the real circuit. Then, the final circuit is simulated to assess its

performance for all relevant conditions and variations. The circuit is designed in a single chip slot

(1, 5mm2) of UMC 130nm with 8 metal layers CMOS technology.

As previously shown, the design of the converter depends on three major variables: oversam-

pling, modulator order and number of bits. These variables are not independent, therefore, a top

level simulation was used to achieve initial performance estimate. This was done using Matlab

with the Delta-Sigma toolbox [21] from Richard Schreier. As a next level of accuracy in the DAC

modelling HSpice was used, first with ideal components with non idealities progressively intro-

duced. Using this methodology, the designer can evaluate the impact of each non-idealitie in the

converter starting from the simple top level architecture, to the final real circuit.

3.1 Architecture Selection

Taking the specifications into account, a top level simulation was used to assess which was

the right set of values for OSR, modulator order and number of bits. A first estimate is obtained

based on Figure 3.1 [21], this presents the SNR as a function of the modulator order and OSR.

However, Figure 3.1 data is only valid for single bit modulators. Note that a graphic is used instead

of equations as the dependency is not linear and would demand either an equation for each order

or a more complex and less intuitive equation for all orders. The analysis is made easier and

simpler when done over a graphical representation for the most relevant set of values.

Figure 3.1: SNR limits for binary low pass Σ∆ modulators.

Figure 3.1 shows that increasing the order of the modulator represents significant gains in

24

3.1 Architecture Selection

SNR for the first three orders. Additional increases in the modulators order do not translate

in proportional gains in SNR. Note that both, the first and second order, modulators are always

stable, as previously discussed in Chapter 2. Taking into account power and area costs to achieve

the specified resolution, second or third order modulators seem to strike the better balance of

performance and complexity.

Figures 3.2 and 3.3 present the SNR dependency with both the OSR and the number of bits

for a second and third order modulators, respectively. These figures were obtained with the Delta-

Sigma Matlab toolbox [21].

Figure 3.2: SNR vs number of bits vs OSR for a second order modulator.

To achieve the desired 80dB SNR in the real circuit, the design of the converter must start

targeting a higher maximum SNR to have room for non-idealities in the implementation. Initially a

second order single bit architecture was chosen for its simplicity and inherent stability. This topol-

ogy can achieve a maximum SNR of 99dB by using a OSR of 256, giving a sampling frequency

of 256 × 16kHz = 4.096MHz. This implementation proved to be too difficult on the analogue

filtering as the single bit modulator output had too much low frequency content and imposed a

very selective output filter. Such filter would need much area and power consumption to achieve

the desired performance, as will be explained in more detail along this chapter and in the next,

Chapter 4.

In order to simplify the filter, a multi bit architecture was adopted as it reduces the low frequency

content and hence relaxes the requirements on filter selectivity. The increased performance of

multi bit enables also to lower the OSR and further simplify the output SC filter as it will use a

lower switching frequency. Basically, the idea is to transfer complexity to the digital block and

alleviate the analogue, as the digital is immune to most non-idelaities and easier to implement. To

25

3. Voice DAC Design

Figure 3.3: SNR vs number of bits vs OSR for a third order modulator.

capitalise on this the modulator order was increased to third order, lowering the OSR significantly.

Based on [4] and [16], a third order, 3 bit modulator was chosen for the complexity and OSR

compromise that still ensures the necessary performance. The use of a third order modulator

also enables a easier evolution to higher resolutions, namely audio (100 − 120dB) , in the future

maintaining the same basic architecture. Variations in the OSR and number of bits can tune

the resolution and consumption to each application without a major/complete redesign of the

system/converter. The modulator oversampling will be 64, giving a sampling frequency of 64 ×

16kHz = 1.024MHz. This configuration ensures a theoretical maximum of 104dB SNR which

should give enough room for noise and non idealities. Table 3.1 summarises the second and third

order modulator specifications that were evaluated.

Table 3.1: Modulator specificationsParameter 1st version 2nd versionBandwidth 16kHz 16kHz

Modulator order 2rd 3rd

Number of bits 1 3OSR 256 64

Max. SNR 99.1dB 104dB

3.2 Circuit Design

The digital blocks: interpolation filter and Σ∆ modulator, were specified and their synthesis

and layout was done by the digital design team of Silicon Gate. The digital circuitry consists of

a interpolation filter, Σ∆ modulator and a thermometer codifier with scrambled output codes (in

26

3.2 Circuit Design

order to implement DEM).

The analogue circuit was specified and implemented, design and layout. The analogue circuit

consists of a reconstruction and anti image filter, or simply, a Σ∆ demodulator. The circuit can

either follow a conventional 2ndorder demodulator from [15] for a single bit modulator or a DCT

architecture as seen in [3] and [22], which is suitable for multi bit modulators where the filtering

requirements are more relaxed. The fact that a multi bit stream has a small low frequency content,

as seen previously in Figure 2.8, allows for a higher frequency and less selective filter, enabling a

more linear phase and simpler circuit respectively. In essence there is always a trade off between

the out-of-band noise reduction and increases in power, in-band noise and distortion. In this case

the multi bit solution was chosen and hence a DCT filter was used.

3.2.1 Interpolator

The interpolation filter needs to provide the OSR, in this case the specified 64× up sampling,

and must present a linear phase response. The interpolation is done taking 64 samples for each

input sample (the input sample plus 63 zeros), then applying a low pass filter to smooth the output.

Since the interpolation factor is high (64) using a single stage would require a very steep filter.

Therefore the filter is usually designed in several, more simple/relaxed, stages [5]. A four stage

CIC filter, obtained with Matlab Filter Design and Analysis Tool (FDATool), is used.

3.2.2 Modulator

The modulator is multi bit and 3rd order, thus requiring 3 integrators and a quantizer connected

in a feedback structure. Since the modulator is digital, integrators will be implemented using

accumulators. The digital quantizer truncates the N bit input signal to M output bits. A generic

block diagram of a 3rdorder modulator is shown in Figure 3.4.

Figure 3.4: Block diagram of a digital modulator.

There is an important compromise between the NTF poles placement (as it defines the DR)

and stability trade off as it affects the quantizer saturation and hence the DR inside the modulator

loop. This is usually evaluated through the peak NTF out-of-band gain, also called Hinf . Multi bit

allows better DR and stability at the cost of additional complexity. Dither is used to reduce idle

tones and DEM to improve linearity.

27

3. Voice DAC Design

The design of the modulator closely follows [16] and [4], whose basic structure is shown in

Figure 3.5. These references already provide the coefficients to guarantee the stability of the

modulator, not intrinsic for third or higher order.

Figure 3.5: Digital Σ∆ modulator architecture.

These coefficients have been approximated to the nearest 2´s power to simplify their imple-

mentation as seen in Table 3.2 from [4].

Table 3.2: Digital Σ∆ modulator coefficientsCoefficient exact value approximated value as power of 2 sum

b1 0.1619 2−3 + 2−5 = 0.1562a1 0.1619 2−3 + 2−5 = 0.1562a2 0.5790 2−1 + 2−4 = 0.5625g1 0.001445 2−10 + 2−11 = 0.001468

c1=c2=c3 1 20 = 1

In this case the quantizer will take the 13 bit input, keep 3 MSBs and use them for the output.

The feedback signal uses the output bits as MSBs and the remaining are stuffed with zeros.

The output has 3 bits whose 8 binary combinations are converted to independent levels using

a thermometer code. In this modulator, since we wish to preserve the zero level and retain an

even number of levels, one of the levels is discarded to have a 7 level mid-thread quantisation.

The motivations, as discussed in chapter 2, is the correct quantisation of silence and avoiding

excessive noise for weak signal, which become very audible.

3.2.3 DEM

In order to reduce the multi bit non linearity, DEM is employed on top of the thermometer

code of the modulators output. The non linearity is caused by different gains, from different

capacitors, in the analogue filter, due to their mismatch. The DEM is done with a butterfly shuffler

that implements a random scrambling, as previously presented in Chapter 2. The idea is to

avoid repeating the last used combinations. It is not the most sophisticated algorithm but it is still

effective, especially as there are only 7 levels to scramble. Moreover, this implementation of DEM

provides a low area, which is vital for low cost portable devices.

28

3.2 Circuit Design

3.2.4 Direct Charge Transfer DAC

The schematic of a single ended DCT filter is presented in Figure 3.6. The basic operation

relies in sampling the input signal to C1, by closing φ1 switches, and redistributing that charge to

C2, by closing φ2 switches. Note that φ1 and φ2 are opposite and non overlapped phases.

Figure 3.6: Simple DCT stage.

The transfer function for this DCT is presented in equation (3.1). It shows that the filtering is 1st

order and that the gain is defined by C1 while the cutoff frequency is defined by both capacitors,

C1 and C2.

H(z−1) =C1 × z−1

(C1 + C2)− C2 × z−1(3.1)

For Σ∆ demodulation the input signal will be a sampled reference voltage, with the switches

controlled by phase 1 and the sigma-delta modulator bitstream. Actually, two reference voltages

are used, ideally the power rails, whose sampling is controlled by the multiplication of phase 1

and the bitstream or its complementary.

The idea of the first simulations is to validate the architecture and to design both the amplifier

gain and the bandwidth together with the capacitor values. This way, it is easier to establish the

specification for the amplifier in more realistic conditions before starting its implementation.

The sampling capacitors are designed based on the amount of noise we are willing to tolerate.

As such, we must first determine the variation of the noise with the capacitor value. The dominant

concern here is thermal noise, as seen in Appendix B. The use of two sampling phases doubles

the noise, as does the fully differential architecture [23]. The topology used (DCT, fully differential)

causes four times more noise than the previous circuit from Figure 3.6, as shown in (3.2).

V 2N(T ) =

4× k × TC

[V 2] (3.2)

Since the circuit is using oversampling the noise contribution in the signal band will be as

shown in equation (3.3) [5].

V 2N(T ) =

4× k × TC ×OSR

[V 2] (3.3)

29

3. Voice DAC Design

To assess the maximum tolerable noise it is necessary to look at the desired SNR using

equation (3.4).

SNR = 20× log10(Vsignal[RMS]

Vnoise[RMS]) (3.4)

The calculus of the RMS value of the input signal is also needed. Since a 1kHz sine is used

as input, equation (3.5) yields the RMS value.

Vsignal[RMS] =0.5× Vsignal[pp]√

2(3.5)

The RMS value of noise is obtainned using (3.6).

Vnoise[RMS] =Vsignal[RMS]

10SNRdB

20

(3.6)

Finally, using (3.3) and the noise RMS value, the capacitor value is calculated as shown in

(3.7).

Csampling =4× k × T

V 2N(T ) ×OSR

(3.7)

The feedback capacitor can now be calculated using equation (3.8).

Cfeedback =Fsampling × Csampling

2× π × fcutoff(3.8)

Looking at the specifications shown in Chapter 1.2, the desired SNR is 80dB. It is wise to

leave room for non-idealities, both from the DAC itself and from driver as well, in the SNR used for

the design. To evaluate the effect of leaving that margin in the capacitor size, and therefore area

and consumption to guarantee fast charge/discharge, calculus was done for a SNR of 80, 90 and

100dB with results shown in Table 3.3.

Table 3.3: Capacitor values for different SNRs, with a 0.5V pp signal.SNR [dB] Cs [pF] Cf [pF]

80 0.21 8.2490 2.1 82.4100 21 824

80dB provides no margin and it is ruled out. 100dB demands capacitors that are simply to large

to integrate in such an application, in particular the feedback one. As such the midway solution

is taken, 90dB SNR which with a DAC output voltage of 0.5Vpp give the noise value 5.6µVRMS

. Taking into account (3.7) a 2.1pF sampling capacity is required, and for a cut off frequency

of 16kHz, the feedback capacitor will have 82.4pF . A trade off is struck here using a smaller

feedback capacitor that will raise the cut off frequency allowing more noise but save area and

power for charge and discharge.

30

3.2 Circuit Design

For the single bit second order modulator this proved to be a weak filter as its response is first

order and hence has very poor selectivity. It only begins to properly attenuate at high frequencies,

suiting multi bit modulators whose low frequency content is low. A second order filter was tested

as the ones from [15], already described in Chapter 2. This filter would still not have enough

attenuation to meet the desired 80dB, low frequency noise still degrades the SNR too much. The

solution was to use two sections of second order filters creating a fourth order filter, although each

second order filter only uses one amplifier it still demands twice the amplifiers in a DCT, more area

and specially power. Note that all this had to be done at a OSR of 256, meaning the switching

frequency is 4 times higher than the multi bit solution, further increasing power.

The multi bit modulator not only achieves good performance with the DCT filter but also saves

area and power. All this will be illustrated with simulation results in Chapter 4.

Since the modulator has 7 output levels, 7 sampling capacitor are used. Note that the sampling

capacity is distributed for those 7 capacitors, so each will have 300fF ( 2.1pF7 ). The capacitors were

organised in a array block seen in Figure 3.7 to simplify the top schematic of the complete filter

presented in Figure 3.8. The array is connected by switches to the amplifier, controlled by Φ2, and

to the reference voltages, controlled by Φ1 and the modulator output levels.

Reference voltages Vrefp and Vrefn should be as apart as possible as they define the full scale

of the converter and heavily compromise its dynamic range. If the input goes beyond the reference

voltage the filter will saturate and distort the signal. The quantisation interval/step is defined by

the number of quantisation levels and the voltage references, as equation (3.9) illustrates. That

strong dependency on the references will also affect the quantisation error/noise, as its power is

42/12 [23].

4 =Vrefp − Vrefn

number of levels(3.9)

The power rails can not be used directly for reference voltages because margins must be

preserved for the devices polarisation (Vth), on the other hand saturation of the amplifiers must

be avoided.

The VCM should not have any offset since it would cause a DC signal which creates idle tones

in the modulator output. Such offset would also give different swings for signals above or below

VCM , causing distortion.

Even order harmonics are suppressed with a fully differential architecture, since their effects

cancel out when subtracting both branches signals to obtain the differential one.

The amplifiers GBW should be at least 5 times the sampling frequency to reach settling in

75% of the switching period [4]. This GBW guarantees enough speed to avoid distortion in the

reconstruction of the signal. Also important is the SC filter accuracy which is controlled with the

amplifiers DC gain. One additional important parameter for the amplifier is its output voltage

swing, which in this case is determined by 4, i.e. the reference voltages already determine the

31

3. Voice DAC Design

Figure 3.7: DCT DAC schematic.

32

3.2 Circuit Design

Figure 3.8: DCT sampling capacitors array.

33

3. Voice DAC Design

voltage swing value required.

3.2.4.A Switches

The switches, ideally, should provide a infinite resistance when off, in order not to inject any

charge in the capacitors, and null resistance when on, to reduce the thermal noise that will be

sampled. In order to implement the switch in a CMOS technology NMOS or PMOS devices can

be used. Figure 3.9 [24]. shows an example of a NMOS switch

Figure 3.9: NMOS switch.

RON is 6= 0, usually some hundreds Ω, and it will vary with VGS . Moreover, that dependency

is not linear. In order to reduce the RON dependency on VGS , a CMOS switch, also known as

transmission gate, employing a PMOS and a NMOS device provides a more constant and low

RON , as illustrated in Figure 3.10 [24].

Figure 3.10: CMOS switch and its equivalent RON .

On the other hand, ROFF 6= ∞, usually in the tens of MΩ. As a consequence the channel

capacity will inject charge to the capacitor, corrupting the sample. The parasitic capacitances add

charge injection due to clock feed trough. However, the injected charge is much smaller than the

charge coming from the channel since the capacitance of the channel is also bigger than CGD

or CGS . Both problems are discussed in detail in Appendix C where the bottom plate sampling

and special switches, CMOS and dummy, are explained. Bottom plate sampling will be used

to avoid input dependant charge injection that distorts samples differently according to the input

signal. Input independent charge injection only generates an offset that is cancelled by the fully

differential architecture.

34

3.2 Circuit Design

The CMOS solution has more charge injection than a dummy but presents a lower RON with

a more linear variation which is favoured here since having a low distortion of the signal is crucial

to achieve the desired performance.

3.2.4.B Amplifier

The requirements for the OTA are mainly the output swing, DC gain and the GBW. As noted

earlier, the output swing is fixed by the reference voltages. DC gain and GBW, which account for

the accuracy and speed of the amplifier must high enough to allow the SC to work properly. As

referred earlier, the settling must occur within 75% of the switching/clock period. The amplifiers

GBW should at least 5 times the sampling frequency, in this case 5 × 1MHz = 5MHz, to guar-

antee the necessary speed. DC gain must ensure the settling accuracy but it is limited by the

current consumption, specially important in battery powered applications as this one. This was

tuned with a simple model of the amplifier, as shown in Figure 3.11, based on three parameters:

DC gain, GBW and output swing. After the simulations a gain of 100dB was found to be the

minimum suitable value.

Figure 3.11: Simple amplifier model schematic.

The amplifier used in the DCT filter is a fully differential current mirror OTA. This circuit was

originally developed for the ADC in this CODEC that was based in [25] and whose basic schematic

is shown in Figure 3.12 together with the SC Common Mode Feedback (CMFB) of Figure 3.13.

Since the amplifier used in the ADC has a GBW of 20MHz (5 × 4MHz which is its sampling

frequency, OSR of 256) it has no problems handling the DAC filter. The swing is equal to that

used in the ADC, as the reference voltages that define it are also the same.

35

3. Voice DAC Design

Figure 3.12: Simple schematic of current mirror OTA.

Figure 3.13: Switched common mode feedback.

36

3.2 Circuit Design

The switched CMFB has a good power efficiency. The two pre-charged capacitor C1 and C2

sense the output common mode voltage and shift the voltage to a proper level in node CMFB.

Capacitor C3 and C4 periodically recharge the sensing capacitor to provide a constant voltage in

the sensing capacitor.

The current mirror OTA, used as a single stage, simplifies achieving the settling time, but

makes it harder to have a high gain. One solution is to have more than one stage but this compli-

cates the settling with more zeros and poles and must have compensation to avoid instability. A

midway solution is used with the use of cascodes as the circuit is low power but has a 3V supply

so it has room for transistor stacking.

The schematic of the amplifier is shown in Figure 3.14. The five left branches produce all

cascado and bias currents and mirror them to the amplifier. All transistors were designed for a

200mV overdrive voltage, also important is that their dimensions (W/L) and number of fingers

were designed to facilitate the layout matching. The differential pair uses a 28µA current (4× the

input 7µA). This OTA was simulated in transient time analysis and AC open loop, not only in

typical conditions but corners as well, the results are presented in Chapter 4.

Figure 3.14: OTA mirror schematic.

The actual amplifier for the DAC has two extra capacitors, between each output and the bias

net in their cascode. These proved necessary to meet the specifications for some extreme oper-

ation conditions (corners) as the load in this filter has a larger capacity to charge/discharge and it

still uses the same bias current, 7µA. The amplifier enables the reuse from both integrators in the

ADC.

The filter output must have a buffer stage to drive the chip pads. A non inverting topology is

used for each output as it does not demand much current from the filter. Such topology enables

the use of a simple single ended amplifier, Figure 3.15 show the schematic of this amplifier.

Finally all biasing nets have power down transistors to reduce consumption when the circuit is

37

3. Voice DAC Design

Figure 3.15: buffer amplifier schematic.

turned off. Power down mode is controlled by a enable input pin. It is very important to ensure

low power operation, crucial in battery powered applications

3.3 Synopsis

For each DAC block the tradeoffs and design of the circuit were presented. A comparison

was made between a initial second order single bit approach and the final third order, three bit

converter. The change was due to the first converter requirement of a very selective analogue

output filter. The solution was to pass the extra complexity to the digital block and thus alleviate

the analogue filter. The interpolator was done using a simple CIC filter with 4 sections to accom-

modate the large up-sampling factor/OSR. The modulator was chosen as an easily upgradable

design while keeping area and power low, this was done with using third order but a low OSR. The

added complexity was small when compared with the reduction in power due to the lower clock

frequency. The multi bit structure allows extra stability and performance at a low price in power

and area, essentially more sampling capacitors in the output filter. The output filter uses a DCT

topology which perfectly suits low power multi bit DACs and needs a single amplifier, reused from

the ADC. A simple buffer is used at the output to drive the pads.

38

4Simulation Results

Contents4.1 Interpolation and Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404.2 Analogue filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424.3 Synopsis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

39

4. Simulation Results

Simulation of the DAC followed the same approach and was part of the the design methodol-

ogy, starting from an higher level of abstraction and increasingly getting closer to the real com-

ponents. Before integration into the system, each block is first tested on its own. The simulation

stimulus of each block is obtained from the simulated output of the previous one.

The full system test signal, and hence the first block as well, is usually a 1kHz sine wave [3]

[4] [16] [22]. The signal is related to the threshold of hearing, the reference sound intensity (0dB)

is 10−16W/cm2 for a sound at 1kHz [26]. In the laboratory a 997Hz test signal is often used. The

idea behind this test signal is to use the closest prime number and thus eliminates most tones.

The amplitude is usually set at 80%FS to ensure no overload/saturation occurs, but it is also

common to see 0dBFS and −60dBFS signals used. The sampling window for audio systems is

usually the Blackman-Harris as it provides the sharpest attenuation characteristic. Voice has a

small interest band, 16kHz compared with the much larger sampling frequency, fs/2 = 0.5MHz,

and therefore the Blackman-Harris window eliminates more errors outside the signal band. When

performing a simulation it is also important to have a significant number of periods of the signal so

that the FFT calculus produces meaningful results. In the digital blocks 100 periods were used as

those simulations were fast, but for the analogue circuit only 25 periods are used as the simulation

effort is very high. The main cause for the slow analogue simulations are the necessary HSpice

options set for high precision and very low tolerance since otherwise it is impossible to measure

the smaller than −120dB (or 1ppm) variations needed for this converters evaluation.

4.1 Interpolation and Modulation

The interpolation filter should have a 1kHz sine wave in PCM at the input sampled at 16kHz

and provide the same PCM sine sampled at 1MHz at the output. Some small attenuation is

expected as there is no perfect filter with zero losses.

The modulator receives the PCM sine and produces a Σ∆ bitstream, with 1 bit (2 levels) or

3 bits (8 levels) for the single and multi bit modulators, respectively. In order to ensure that no

overload occurs, a 0.8FS amplitude sine is used as input signal. As a consequence, instead of

the 80dB SNR expected for a 13 bit signal it will have 78dB.

The modulator was implemented in Verilog and simulated in ModelSim. The resulting input

and output waves are shown, for the multi bit version, in Figure 4.1.

Figure 4.2 shows the input signal PSD which is 0.3dB below the expected, due to numerical

error/precision in the Perl script used in its generation. The output of the modulator is shown in

Figure 4.3 showing that 2.8dB are lost in the modulation process. The reasons for this loss are

the approximated coefficients and some inevitable attenuation since all gains in the modulator are

smaller than 1 in order to ensure its stability. A similar result is obtained for both versions of the

modulator, single and multi bit.

40

4.1 Interpolation and Modulation

Figure 4.1: Input and output signals of the modulator.

Figure 4.2: Power Spectral Density of modulator input.

41

4. Simulation Results

Figure 4.3: Power Spectral Density at modulator output.

The three output bits are converted into a scrambled, through DEM, thermometer code that

will be the input of the analogue filter.

4.2 Analogue filter

The analogue reconstruction filter is done with 2 sampling capacitor arrays, 2 feedback capac-

itors and a fully differential amplifier. The first simulations used ideal capacitors, switches with a

configurable Ron and an amplifier model to evaluate its DC gain, GBW and output swing. This

test bench was the base for the first tuning of these basic parameters that define the response of

the filter.

Figure 4.4 shows the circuit with ideal components and only 1 bit input used for the first Spice

simulations. The amplifier model has a finite gain and limited bandwidth (RC filter) so that the

impact of those parameters can be evaluated.

At this stage, the input signal was the output of the ADC, also implemented with ideal com-

ponents, and a SNR of 100dB. This explains the high SNR in Figure 4.5 which shows the ideal

circuit output in both time and frequency. Note that this simulations showed that the sampling

capacitors could have half the previously calculated capacity with no performance loss.

4.2.1 Switches and Capacitors

The switches choice, between CMOS and dummy (both described in detail in Appendix C),

was based on their analysis by simulating the conditions similar to those experienced on the DCT

filter (as described in Chapter 3). The test bench schematic is presented on Figure D.5. The

42

4.2 Analogue filter

Figure 4.4: DCT DAC schematic, with ideal components.

43

4. Simulation Results

Figure 4.5: Ideal DCT output transient analysis and PSD .

resistance value (with the switch turned on, and turned off), and the current peaks (Ip) caused by

charge injection were measured, producing the results shown in Table 4.1.

For the CMOS switch two variants were tested: the first with the P and N devices with equal

sizes (also equal capacitances and consequently better charge injection cancelation), and the

second with the P devices 3× bigger than the N ones (faster as it is a better match of carrier

mobility between devices).

The dummy switch uses a series resistance to make RON approximately linear. In this ap-

plication, with a period of 1000ns, there is room for the extra delay introduced, τ = RC. With

a series resistance 10 times greater than the dummy RON , τ is less than a fifth of the period

(40kΩ × 1pF = 40ns 1000ns). Therefore, there is enough time for a linear settling ate each

sample, as the RC constant will account for only 4% of the period. The area required for the

resistors is not critical when compared to the capacitors, since only a single resistor is needed for

each sampling branch. Moreover, the alternative of using bootstrapping would mean always more

area than the resistor and more power, quite undesirable in a battery powered application.

Simulation results confirm that the dummy switch injects less charge than the CMOS switch,

about 30% as seen in the Ip values from Table 4.1. On the other hand, the dummy switch Ron

is more than 4× higher than the CMOS resistance. However, simulation of the DCT filter with

both switches did not reveal any measurable advantage of the dummy switches over the CMOS

44

4.2 Analogue filter

Table 4.1: Comparison between CMOS and dummy switches. Ron is the resistance of the switchwhen turned on. Ip is the current peak in the commutations, representing a measure of how muchcharge is injected.

Switch Ron [kΩ] Ip [mA]CMOS (3P:1N) 0.272 1.79CMOS (1P:1N) 0.695 1.49

Dummy 3.505 1.28

switches. Since CMOS switches are more linear, smaller and consume less, they were chosen

for this application as they represent the best performance/area/power compromise.

The next step was the introduction of the real capacitors, Metal Over Metal Capacitors (MOM-

CAP), and CMOS switches to reassess the performance with the complete component models

(from the foundry design kit). MOMCAPs were chosen for their good area/capacity ratio and lower

parasitic capacitances. Simulations confirmed that the sampling capacitors could have half the

capacity (and size) without any performance loss. The feedback capacitors were also reduced

because with multi bit input there are less low frequency harmonics to filter out and thus the cut

off can be raised, saving area in these capacitors and current in their charge / discharge. The

final values for the capacitors are Cs = 150fF (each of the 7 array of sampling capacitors) and

Cfb = 21pF (feedback capacitor).

4.2.2 Amplifier

Based on the DC gain, GBW and output swing obtained from the high level modelled amplifier

simulations, the amplifier was designed and tested in transient and AC open loop responses. Sim-

ulations were done not only for the typical values but also for the extreme/corners of: fabrication

process for MOS and capacitors, bias currents, supply voltage and temperature (in a total of 64

different combinations), as shown in Table 4.2.

Table 4.2: Corner variables.Variable VariationProcess slow and fast for both N and P devices

Capacitors 10%Bias currents 20%

Supply voltage 10%Temperature from −40oC to 125oC

The AC open loop analysis was done using a capacitor in each feedback loop, Figure D.11

presents the test bench, whose capacity the sum o the sampling and feedback capacitors in the

DCT filter. Note that the CMFB was substituted for a continuous time equivalent, shown in Figure

4.6, to create a DC path allowing the ac open loop analysis. In Figure 4.7 the magnitude and

phase response of the amplifier are shown for all the 64 corners ran. Figure 4.8 presents the

measure of the amplifiers Phase Margin, with respect to −180 degrees, and the GBW for the

45

4. Simulation Results

same 64 corners.

Figure 4.6: Continuous CMFB for AC open loop response simulations of the amplifier.

The Transient analysis was done using the DCT filter circuit but reducing the sampling array

to a single capacitor with the total sum of capacities. However, proved to slow a simulation to be

ran for 64 corners. Considering that apart from two compensations capacitors, this is the same

amplifier as the ADC were a transient analysis was ran successfully the amplifier was used directly

in the final filter and a typical transient was ran.

The filter amplifier curent consumption is 100µA, which translates to 300µW when the supply

voltage is 3.0V .

The output buffer used was tested in a similar fashion as the filter amplifier. The designed gain

of 6dB was achieved with a bandwidth of 200kHz. Beyond the primary function of providing the

strength required for driving the chip pads capacitance, it also further filters high frequency noise

because of the limited bandwidth, effectively working as a low pass filter. The PSD response

presented in Figure 4.9 shows that the buffer not only has a high SNR (almost doubling from

the signal SNR), but also attenuates high frequency signals. The low distortion and noise of the

buffers are paid in its power consumption of 300µA.

The input FIR to the SC filter, already discussed in Chapter 2, based on [3], was tested and

presented similar performance. Since it requires considerable area, double the sampling ca-

pacitors, and demands more power from the amplifier, to charge the extra capacity, the simpler

structure was kept.

Finally, with low level models that include all the parasitic effects for the target technology, the

performance of the complete DAC was evaluated. The performance of the fourth order filter, for

the single bit converter, and the DCT, for the multi bit converter is similar. Therefore, only the multi

46

4.2 Analogue filter

Figure 4.7: AC open loop response of the amplifier in all corners.

Figure 4.8: Phase margin and GBW of the amplifier in all corners.

47

4. Simulation Results

Figure 4.9: Output buffer PSD.

48

4.3 Synopsis

bit data is presented. Power and area are the differentiating factors and are discussed ahead.

Figure 4.10 shows the DCT filter transient analysis and its power spectral density. The output

SNR, measured at the buffers output can be seen in Figure 4.11, is 70.4dB. Since the filter input

(which is the modulator output) had 74.9dB, the loss in the analogue circuit (DCT filter and output

buffers) is only 4.5dB.

Figure 4.10: Real DCT output transient analysis and PSD.

The dominant power consumption in the analogue filter is the amplifier(100µA) as voltage ref-

erences use about 350nA each and Vcm uses less than 2nA. This also means the analogue filter

for the single bit architecture, that needs a fourth order filter to achieve the desired performance,

doubles the consumption when compared to the 3 bit version as it uses two amplifiers instead

of the single needed for DCT. The overall analogue power is, however, dominated by the output

buffer than needs 300µA, three times more than the filter.

4.3 Synopsis

The multi bit converters were simulated in ModelSim (digital blocks) and HSpice (analogue).

While their performance is similar, the single bit needs more area and power. A 0.8FS input was

used, feeding 78dB to the DAC. The total signal loss in the DAC is of almost 7.3dB (2.8dB in

the digital section and 4.5dB in the analogue); essentially two bits of the 13 are lost. The multi

bit achieves this performance using less area, a 4× slower clock and half the amplifiers for the

analogue filter. These two latter reductions mean 4× less power for the digital block and half the

power for the analogue. Finally a simple output buffer is used to enable the signal to drive the chip

pads. The power consumption of the analogue blocks is mainly determined by this output buffer.

49

4. Simulation Results

Figure 4.11: DAC output with buffer PSD.

50

5Layout

Contents5.1 DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545.2 CODEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

51

5. Layout

Upon finishing the full circuit simulations, the layout of all components was designed. Floor

plan and routing must consider all the parasitic and non-idealities from the fabrication process

and interference between blocks. This is true for the DAC itself as well as its integration in the full

CODEC with: ADC, clock and phase generators, current bias, voltage references and supply.

On top of that, common cares in assuring good layout practices to improve the yield are used

(Design for Manufacture). Avoiding minimum distances, taking into account parameter tolerances

ensures safety against the process variations. Large traces were used to lower their impedance

and avoid voltage drops. More than one via were used at each connection between layers lower-

ing impedance and improving reliability. Separate digital and analogue grounds were used, only

shorted outside the chip to separate noise in both grounds. Guard rings were added wherever

possible not only bias the substrate, but also to prevent latch-up and to shield noise.

5.1 DAC

The DAC is a mixed signal circuit so extra care as to be taken to separate the digital an

analogue blocks, as the digital blocks will introduce a lot of noise to which the analogue is very

sensitive. The separation is particularly difficult as the stimulus for the analogue block are digital:

clock, switch phases and the input signal as well.

Reference voltages Vrefn and Vrefp are directly sampled to the capacitor as the bitstream

varies, i.e. any noise in them is added to the samples and is delivered to the output completely

unfiltered. The circuit does not present immunity to noise from reference voltages.

Since the filter and amplifier are fully differential, a symmetric (or butterfly) layout is used so

that each branch, n and p, are matched, i.e. booth “see” the same parasites and are affected by

the same interference. All disturbances occurs in both branches and are cancelled since the ac-

tual output signal is the difference between both branches. Large transistors in the amplifier were

divided in fingers in order to facilitate their matching, either in interdigitized form, or in the differ-

ential pair with a common centroid structure (the later is better but creates some area overhead

and complicates the routing). Such techniques allow a more even spread of fabrication variations,

promoting a better match of nearby devices.

Figure 5.1 presents the amplifier layout. The structure used separates clearly the N and P

devices of the main amplifier, with the differential pair to keep all sensitive signals together. The

bias network is relegated to one extreme as its layout is less critical. The central line is in effect

the symmetry axis of the amplifier dividing the two branches. Power rails are placed at the sides

so they can easily connect wherever needed and present equal capacitances for both branches.

The OTAs CMFB circuit is also divided in two, but is introduced directly in the layout of the

DCT filter. The idea is to place its capacitors close to the filters to optimise area and improve their

shielding from interference from commutations.

52

5.1 DAC

Figure 5.1: Layout of the OTA.

53

5. Layout

Dummy capacitors were used to compensate for the faster etching in large unprotected areas.

Guard rings are placed around each capacitor to minimise noise. Capacitors layout were designed

to minimise their mismatch by interdigitizing them .

All digital and switching signals plus the clock phases are kept together as much as possible

to form “noisy zones”. These zones should be as far part as possible from the more sensitive

signals (input or output), biasing currents and reference voltages and thus creating “quiet zones”.

The clock phases in particular can cause much interference and so were isolated with metal all

round them, creating a “tunnel” with metal traces above and below and vias on the sides. Note

that all metal is shorted and connected to ground. In essence, assuring signal integrity across

the chip. The same principle holds true for capacitors from different sub circuits, in this case the

sampling and feedback capacitors of the SC filter and the CMFB ones.

Figure 5.2 presents the complete DAC floor plan, the connections were left out to improve

readability. The central zone is the “quiet” one, with all the most sensitive components: OTA,

output buffers (the empty space in front of the OTA) and capacitors.In the extremes we have the

“noisy” zones with the switches, and in the top one the phase generator.

The DAC has a estimated area below 0.3mm2 without pads, as it needs 10 pads (some are

shared with the ADC) the total area is below 0.5mm2.

5.2 CODEC

The CODEC must follow all the above rules in the interconnects between the ADC, DAC, clock

and reference generators and all the input and output pads. All the digital blocks from the ADC

and DAC were kept together to isolate the rest of the circuit from the commutation noise. Since

the two converters operate with sampling frequencies, their clock generators are different and are

close to the respective SC circuit. Care must also be taken to avoid having the analogue circuits

and signals near the digital paths and pads. Analogue pads should be connected with as short a

path as possible to keep their impedance low.

The full CODEC area is estimated at about 0.5mm2 without pads, the figure grows to 1mm2

with the total 15 pads.

54

5.2 CODEC

Figure 5.2: Floor plan of the DCT filter.

55

5. Layout

56

6Conclusions

Contents6.1 Summary and Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 606.2 Future work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

57

6. Conclusions

A brief summary of the project and the most important achievements are presented.Future

improvements to the DAC and CODEC, to improve efficiency and / or performance are also dis-

cussed.

6.1 Summary and Conclusions

The design of a low power 13 bit DAC for a Voice CODEC was the objective of this work. The

desired resolution of 70dB was met and exceeded. The estimated area of the DAC, below 0.3mm2,

is within the initially specified (0.8mm2 for the complete CODEC), and the current consumption

is also within the specifications, using less than half the total (CODEC) current budget for the

analogue blocks (0.4 < 0.5mA).

At first a simple single bit DAC architecture was tested but proved to be too demanding on

the analogue output filter, meaning either the performance was not achieved or a large area and

power would be needed. The final DAC architecture was based in a know state of the art audio

DAC architecture that was geared to a lower resolution and power consumption. In the digital

blocks the power was reduced by lowering the OSR, which lowers the power consumption of the

whole converter as all transitions work at a lower frequency. The OSR reduction also reduces the

digital interpolator area, complexity and power. Moreover, the specifications for the analogue filter

are relaxed in speed by the lower switching frequency. Moreover, the DEM was simplified since

for this level of performance the third order modulator can have only 3 bits. The scrambling of

the output levels is required, to overcome the multi bot non linearity due to capacitor mismatch.

However, scrambling does not have to be very sophisticated, which would add complex processing

that would drive area and power consumption up.

In the analogue blocks, the optimisations came from studying the better amplifier and switch

techniques to introduce in the know architecture and tune it to the desired specs. The amplifier

choice is not the typical AB OTA for SC which guarantees more swing, but also need more area,

compensation and consumes more power. Simulations showed that, for the desired 13 bit res-

olution, the current mirror OTA has enough performance with a simpler design and lower power

consumption. CMOS switches, with equal N and P device size, were found to be the best com-

promise between charge injection cancelation, area and power. The base audio architecture has

a FIR filter to smooth the DCT filter that was not found to significantly improve the performance

of the converter. As for the DCT filter itself, simulations revealed that the sampling capacitors

could be made about half their theoretical value without impacting performance. The feedback

capacitor was also reduced due to the little low frequency harmonic content of the multi bit signal.

Therefore the cut off frequency was raised, reducing the capacitor (saving area and power) for

the same output resolution. A simple output buffer is used to enable the driving of the chip pads,

this solution was used due to time limitations for the project. An output driver will be addressed

58

6.2 Future work

as future work.

The work was done within the development of a full Voice CODEC which is effectively a de-

velopment platform for Σ∆ signal / audio converters at Inesc-ID / Silicon Gate. The basic project

flow for Σ∆ signal converters was built and a first prototype sent to fabrication.

6.2 Future work

The most obvious future improvements would be in the efficiency of both digital multi rate

filters, interpolator and decimator, by using multiple stages (half-bands and a final CIC). This

would improve their performance and efficiency as discussed in Chapter 2.

The Voice CODEC that was designed has the potential to evolve to audio quality, meaning a

SNR of more than 96dB, as the base architecture used was from such grade circuits. The ADC is

upgradable to third order where it would reach audio resolution. The DAC can achieve the extra

performance through more output bits (probably 5 would achieve audio resolution without increas-

ing the output filter significantly). The previous improvements, together with a more sophisticated

DEM algorithm, should ensure higher SNR. The DCT amplifier may use a OTA with greater out-

put swing (a class AB OTA would be the better choice). Another option is to keep the resolution

and further optimise the amplifiers reducing their power consumption. Charge Transfer Amplifiers

(CTA), see [27] and [28], could achieve this as they are essentially a passive amplifier and hence

have no static consumption. In both cases the analogue block power should be reduced with the

use of low voltage transistors.

Finally, to complete the system a proper load driver is necessary. A class D amplifier would be

the best suited as it can offer good performance with very high efficiency, as already mentioned

in Chapter 2.

59

6. Conclusions

60

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64

AAudio and Voice

65

A. Audio and Voice

The basics of audio measurement parameters are explained in this appendix.

Figure A.1, from [26], shows the sensitivity of the human hearing to sound. This provides the

basis for the A-wheighted filter response that mimics the human sensitivity to sound.

Figure A.1: Human sound sensitivity.

The most used metrics for quality in audio circuits are defined below, [25].

DNL - Differential Non-linearity Error, measures the error/deviation in the quantization step,

i.e. the difference between 2 adjacent samples and the ideal quantization step, one LSB.

INL - Integral Non-linearity Error, measures the deviation of the transfer function from the ideal

interpolating line, or more commonly the endpoint fit line for correction of gain and offset errors.

This can be obtainned from the sum of all the DNLs, this value should be below 0.5LSB.

Figure A.2 shows an example of a Digital/Analogue interface transfer function with DNL and

INL indications [6].

SNR - Signal to Noise Ratio, is the converter ratio between the input signal power and the

output noise power. This noise power includes both the quantization and circuit noise.

SINAD or SNDR - Signal to Noise and Distortion Ratio, is the converter ratio between the input

signal power and the sum of the output noise and distortion powers.

Overload - is a drop, typically −3dB, from peak SNR (SNRp).

DR - Dynamic Range, is the ratio between the maximum input signal power that does not

significantly degrade the performance, avoiding overload, and the minimum detectable power,

which translates to SNR = 0dB.

SFDR - Spurious-Free Dynamic Range, is the ratio between the maximum input signal power

that does not significantly degrade the performance, avoiding overload, and the greatest spurious

66

Figure A.2: Example of a Digital/Analogue interface transfer function.

in the bandwidth of interest, regardless of being an harmonic or not.

ENOB - Effective Number Number Of Bits, obtainned trough the equation (A.1).

ENOBbit =SINADdB − 1.76

6.02. (A.1)

In figure A.3 a typical SNR graph illustrates the measures/parameters that can be obtained

from it [25].

Figure A.3: SNR versus input amplitude.

THD - Total Harmonic Distortion, is the ratio between the fundamental and sum of the rest of

the harmonics, usually the first 6, at the output.

67

A. Audio and Voice

THD+N - Total Harmonic Distortion plus Noise, is the ratio between the fundamental and sum

of the rest of the harmonics, usually the first 6, plus the noise both at the converter output.

68

BNoise

69

B. Noise

In this appendix the inherent noise in CMOS circuits will be discussed, interference noise will

be left out as it is dealt with in chapter 5. CMOS technology has two main sources sources of

noise: thermal noise and flicker noise.

Thermal or white noise - is the noise due to the thermal excitation over the charge carriers

in any electronic device or conductor. It is proportional to the absolute value of temperature but

independent of the current. Its spectral distribution is uniform which makes it also know as white

noise. This noise limits the dynamic range of any electronic circuit. The thermal noise power

spectral density is shown in (B.1), where k is the Boltzmann constant (k = 1.38×10−23[J/K]) and

R is the resistance of the conductor/device [23].

SN(T ) = 4× k × T ×R [V 2/Hz] (B.1)

Flicker or 1/f noise - is the noise caused by imperfections in the electronic devices that cause

an interruption or perturbation on the current flow. This effect is inversely proportional to the

operation frequency, hence the 1/f name. The flicker noise power spectral density is shown in

(B.2), where K is a technology parameter constant [23].

SN(f) =K

f[V 2/Hz] (B.2)

In CMOS technology noise comes essentially from resistors and transistors. Capacitors do

not introduce noise by themselves, however, when used in switched capacitors they do sample

the noise from the switch (from RON ).

Resistors only introduce thermal noise, to have the actual noise value equation (B.1) must be

integrated in the interest/signal band (B) as done in (B.3) to model a voltage source in series with

the resistor. To reduce noise in a resistor its resistance value has to be reduced or use a lower

operating temperature.

V 2N(T ) = 4× k × T ×R×B [V 2] (B.3)

MOS transistors introduce both thermal and flicker noise. The flicker noise in the transistor

is modelled as a voltage source in the gate. The voltage value can be obtained trough (B.4),

where K is a constant dependant on the device/technology, W and L are the width and length of

the transistor and COX is the capacity per area unit. From that equation one can see more area

will buy less noise, a very important trade off in the design of any circuit. Also apparent is the

dependence from frequency and the fact that a larger bandwidth guarantees less noise, the idea

behind the use of oversampled circuits.

V 2g(f) =

∫ B

0

K

W × L× COX × fdf [V 2] (B.4)

70

Thermal noise in transistors can be also modelled as voltage source ate the gate, effectively

allowing to model both noises in one source. This is valid since the circuit will be operating at a

moderate frequency, for high frequencies it should be modelled as a current source in parallel with

the channel. The thermal noise voltage value is calculated with (B.5), where gm is the transistor

transconductance in the linear/saturation zone (non homogeneous channel).

V 2g(f) =

∫ B

0

83× k × T × 1

gmdf [V 2] (B.5)

A summary of the noise models for CMOS is presented in figure B.1 from [23].

Figure B.1: Circuit elements and their noise models. Note that capacitors and inductors do notgenerate noise.

Switched capacitors, like the one in figure B.2, will only introduce thermal noise sampled from

the transistor RON , but its band will be limited by the capacitor. Thus the thermal noise spectral

density must be integrated in that band (B = 1/(2× π ×R× C)), as done in equation (B.6). This

equation shows that larger capacities have less noise, an extremely important aspect to take in

account when designing a switched capacitor circuit.

71

B. Noise

Figure B.2: Switched capacitor.

V 2N(T ) =

∫ B

0

4× k × T ×R df = 4× k × T ×R× 12× π ×R× C

× π

2=kT

C[V 2] (B.6)

Since the noised is sampled from the switch RON if the capacitor is sampled by 2 phases the

noise will double, also important to note is that in a fully differential circuit the noise doubles again

as there are twice as much capacitors.

Finally it is worth noting that the noise can also be modelled as a current, here voltage was

used as specifications are also presented in voltage.

72

CSwitched Capacitors

73

C. Switched Capacitors

The most important characteristics of switched capacitor circuits are explained in this ap-

pendix. Implementation problems and their solutions are also discussed.

Figure C.1 shows the basic switch capacitor block [23], where 2 switches transfer the charge

in the capacitor, C1 from V1 to V2 using 2 non-overlap clock phases, φ1 and φ2.

Figure C.1: Basic switched capacitor (a) and its equivalent resistance (b).

Averaging the charge transfer over a clock period one can obtain its rate, or average current,

as shown in (C.1).

Iavg =C1 × (V1 − V2)

T(C.1)

Having a current and voltage difference equates to a equivalent resistance, as can be seen in

(C.2).

Ieq =V1 − V2

Req(C.2)

Such resistance will vary with the capacitor value and sampling/switching frequency as (C.3)

illustrates. Note that this enables a resistance tuning by varying the frequency, allowing the design

of simple tuneable amplifiers and/or filters.

Req =T

C1=

1fs × C1

(C.3)

In filter applications switched capacitor circuits reduce sensibility to clock jitter compared to

their active RC counterparts. SC also provide better component accuracy, specially good since

all this is done in a completely standard CMOS technology. However for high performance circuits

that do not tolerate much noise capacitors must be large to avoid both thermal noise and signal

dependent charge injection and/or clock feedtrough.

Clock jitter is a variation in the sampling edge of the clock signal. This causes error in switches

that are proportional to the signal amplitude [2].

Charge injection - is the injection of charge from the channel of the switching device when

it is turned off. The charge will be distributed to both the drain and source according to the

impedances. If the voltage at the channel is a fixed value is will simply cause an offset in the sam-

ple, but if it depends on the input signal the sample will be distorted/corrupted. This is illustrated

in figure C.2 [24].

74

Figure C.2: Effect of charge injection.

Clock feedtrough - similar to charge injection but here the charge comes from the gate ca-

pacitance when there is a transition in the switching phase/gate signal. As can be seen in figure

C.3 [24].

Figure C.3: Clock feedtrough in a sampling circuit.

In both cases the problem arises from capacitances that are proportional to the switch/transistor

size. Although it is interesting to have larger transistors to reduce RON this will cause more charge

injection. To address this problem special switches, CMOS switch or an additional dummy switch,

are employed.

• CMOS switch, as the one in figure D.4 [24], reduces charge injection as the charge coming

from NMOS is inverse to the PMOS. However they do not cancel out completely as the chan-

nels are not perfectly matched, and the existing matching occurs for one input level/value.

Clock feedtrough cancelling is also incomplete as the CGD is different for PMOS and NMOS.

Figure C.4: CMOS switches.

• Dummy switch, as shown in figure D.3 [24], adds a device with the drain and source shorted,

the dummy switch. That device M2 uses a opposite switching phase to the the switch M1.

When M1 turn off it will inject charge to the capacitor CH , but then M2 will turn on and

absorb the injected charge to create its own channel.

If we consider that the injected charge from M1 is divided equally to the source and drain,

75

C. Switched Capacitors

Figure C.5: Addition of dummy switch.

then the devices dimensions should follow (C.4) to ensure the absorption of the injected

charge.

(WL)M2 =(WL)M1

2(C.4)

The dummy switch resistance can be made more linear by bootstrapping and/or adding a

series linear resistor. The bootstrapping consists in applying a higher voltage to the transistor gate

making RON more linear, for the same device dimensions. To do so, a clock multiplier generates

the signal to be applied to the device gate, controlling the amplitude so as not to destroy the

device. Also important is the fact that this will significantly increase complexity and power of the

circuit, and add area as well. The addition of a series linear resistor, like a polysilicon resistor, with

the dummy, with a bigger value than the RON makes the overall resistance approximately linear.

Thermal noise is not changed as it is only dependent on the capacitor (kT/C). However gain

errors may occur and the capacitor charge/discharge will be slower as the time constant, τ = RC,

increases. Another concern in introducing the series resistance is area since the resistor value

will be high.

The bottom plate sampling technique, implemented with delayed switching phases, prevents

signal dependent charge injection. It consists in using the delayed phases for the switches that

are directly connected to the input signal, as shown in Figure C.6 [2].

If no delayed phases are used, i.e. the switches turn off at the same time, the switches con-

nected to the entry will drain their channels (signal dependent) charge to the sampling capacitor.

By keeping the switches connected to the input a little longer the capacitor will have the other

terminal at high impedance, since the switch at that end is already off. By doing so the charge is

drain to the input and not to the sampling capacitor. Therefore their charge injection is done with

a fixed and known voltage, either ground or common mode. Thus the charge injections are input

independent, i.e. only produce an offset but no gain error in the sampling circuit.

A fully differential architecture, since you only work with the difference between 2 signals,

cancels all offsets present in both off them automatically. The same argument also explains the

cancelling of any even harmonics.

76

Figure C.6: Example of bottom plate sampling, or delayed phases.

77

C. Switched Capacitors

78

DCircuit Schematics

79

D. Circuit Schematics

Figure D.1: Schematic of the testbench for a DCT filter with ideal components.

80

Figure D.2: Schematic of an ideal amplifier model with configurable gain and bandwidth

81

D. Circuit Schematics

Figure D.3: Schematic of a dummy switch.

Figure D.4: Schematic of a CMOS switch.

82

Figure D.5: Schematic of the testbench for dummy and CMOS switches.

83

D. Circuit Schematics

Figure D.6: Schematic of the testbench for the DCT filter with output buffers.

84

Figure D.7: Schematic of the DCT filter with output buffers.

85

D. Circuit Schematics

Figure D.8: Schematic of the the sampling capacitor array of the DCT filter.

86

Figure D.9: Schematic of the current mirror OTA, main amplifier block.

87

D. Circuit Schematics

Figure D.10: Schematic of the current mirror OTA, half the CMFB block (the half simplifies layout).

88

Figure D.11: Schematic for the test bench to measure the AC open loop response of the OTA.

89

D. Circuit Schematics

Figure D.12: Schematic of the output buffer.

90