1

4-1

Internet Engineering

Dr. Jarosław SugierDigital Circuits Design

Part 4: ASIC & Programmable

Logic

4-2

0

UO

UI

0=UI1

UO

UI

UI2, 3,4…

U1 U2 U3 …

UO1 2

1. Parameters of a digital circuit

1.1 DC characteristics

Voltage transfer characteristic

4-3

Input / output voltage levels

0

UO

UI

UILmax

UIHmin

UOLmax

UOHmin

UCC

Out

NMH

UOLmax

UOHmin

In

UILmax

UIHmin

NML

4-4

Current-voltage characteristics (I-V plots)

(A) Bipolar devices, e.g. TTL LS

IN:

OUT:

4-5

(B) CMOS devices

– Spartan-II (FPGA)

– XC9500XL (CPLD)

4-6

1.2 AC parameters

(A) Comb. gate

(B) Synchr. flip-flop

UO

UI

tpLH

tpHL

IN

Clk

tS

tH

Q

tCQ

2

4-7

An example: estimate max. operating frequency

D Q

tCQ = 3.5 ns tSU = 2.0 ns tH = 1.0 ns

D QtpLH = 2.0 nstpHL = 1.5 ns

4-8

Standard Cell ASIC

2. Application Specific Integrated Circuits (ASIC)

4-9

+VDD

I1

IN

T1

+VDD

TK

+VDD

F1

+VDD

FM

In

Out

AND

array

OR

array

PLD transistor array

3. Programmable Logic Devices (PLD)

4-10

. . . . . .

. . .

T1 TK

prog.conections

prog.conections

I1 I2 IN . . .

. . . . . .

. . .

F1 FM

. . . . . .

. . .

T1 TK

prog. conections

prog. conections

I1 I2 IN . . .

. . .

F1

. . .

FM

. . .

I1

IN

TK

FM

T1 T2 T3

F1

. . .

F2 . . .

⇓⇓⇓⇓

⇒⇒⇒⇒

4-11

PAL(Programmable Array Logic)

PLE(Programmable Logic Element)

PLA(Programmable Logic Array)

AND array: Progr. Const. Progr.

OR array: Const. Progr. Progr.

4-12

T0

F0

F1

F2

F3

T1 T2 T7

I0

I1

I2

. . .

3.1 Simple PLD

PLE

⇔⇔⇔⇔ ⇔⇔⇔⇔

O0

O1

O2

O3

OE (output enable)

IN OUT

OE

OE = 1 ⇒ OUT = IN (0/1)

OE = 0 ⇒ OUT = Z (HighZ)

3

4-13

PAL16L8

0 3 4 7 8 11 12 15 1 6 19 20 23 24 27 28 31

0

7

0 3 4 7 8 1 1 1 2 1 5 1 6 19 20 23 24 27 28 31

8

1 5

16

2 3

24

3 1

3 2

3 9

4 0

4 7

4 8

5 5

5 6

6 3

I0

I1

I3

I4

I5

I6

I7

I8

I2

O8

I/ O7

I / O6

I/O5

I/O4

I/O3

I / O2

O1

1 1 I 9

N D

VCC1

2

3

4

5

6

7

8

9

1 2

1 3

1 4

1 6

1 7

1 8

1 9

15

2 0

16L8- 5 (-4)

1 0

16 L8

4-14

0 3 4 7 8 11 1 2 1 5 1 6 19 20 23 24 27 2 8 31

0

7

8

15

1 6

23

2 4

I 0

I 1

I 3

I2

O 8

I/O7

I /O6

VC C 1

2

3

4

17

18

19

20

16L8- 5 (-4)1 6L 8

4-15

PAL16R8

0 3 4 7 8 11 12 15 16 19 20 23 24 27 28 31

0

7

0 3 4 7 8 1 1 1 2 1 5 1 6 1 9 2 0 23 24 27 28 31

8

15

16

23

24

3 1

3 2

3 9

4 0

4 7

4 8

5 5

5 6

6 3

16R8-5 (-4)

2

3

4

5

6

7

8

9

1

18D Q

Q

19

17

16

15

14

13

12

11

O8

O7

O6

O5

O4

O3

O2

O1

OE

V

CLK

I1

I2

I3

I4

I5

I6

I7

I8

D Q

QV

D Q

QV

D Q

QV

D Q

QV

D Q

QV

D Q

QV

D Q

QV

G N D

VCC

1 0

20

16R8 ( 4)

4-16

0 3 4 7 8 11 12 15 16 19 20 23 24 27 28 31

0

7

8

15

16

23

24

16R8-5 (-4)

2

3

4

1

18D Q

Q

19

17

O8

O7

O6

V

CLK

I1

I2

I3

D Q

QV

D Q

QV

VCC20

16R8 ( 4)

4-17

PALCE22V10 and PALCE22V10Z Families

0

1

9

SP

AR0 3 4 7 8 11 12 15 16 19 20 23 24 27 28 31 32 35 36 39 40 43

10

20

21

0 3 4 7 8 1 1 1 2 1 5 1 6 1 9 2 0 2 3 2 4 2 7 28 31 32 35 36 39 40 43

CLK/I0 1

(2)

2

(3)I1

3

(4)I2

4

( 5 )I3

5

( 6 )

I4

6

( 7 )

I5

7

( 9 )

I6

8

( 1 0 )

I7

9

( 1 1 )I8

1 0

( 1 2 )I9

1 1

( 1 3 )

I 1 0

1 2

( 1 4 )

G N D

24

(28) VCC

(16)

I1311

34

33

48

4 9

6 5

6 6

8 2

8 3

9 7

9 8

1 1 0

1 1 1

1 2 1

1 2 2

1 3 0

1 3 1

I/O923

(27)

8I/O22

(26)

I/O21

(25)7

I/O20

(24)

6

5I/O19

(23)

4I/O18

(21)

I/O17

(20)

3

I/O16

(19)

2

I/O15

(18)

1

I/O14

(17)

0

D

SP

ARQ

0

1

1 0

1 1

0 0

0 1

D

SP

ARQ

0

1

1 0

1 1

0 0

0 1

D

SP

ARQ

0

1

1 0

1 1

0 0

0 1

D

SP

ARQ

0

1

1 0

1 1

0 0

0 1

D

SP

ARQ

0

1

1 0

1 1

0 0

0 1

D

SP

ARQ

0

1

1 0

1 1

0 0

0 1

D

SP

ARQ

0

1

1 0

1 1

0 0

0 1

D

SP

ARQ

0

1

1 0

1 1

0 0

0 1

D

SP

ARQ

0

1

1 0

1 1

0 0

0 1

D

SP

ARQ

0

1

1 0

1 1

0 0

0 1

Q

Q

Q

Q

Q

Q

Q

Q

Q

Q

16564E-006

PALCE22V10

4-18

4

4-19

3.2 Complex PLD

Glo

ba

l in

terc

onn

ect m

atr

ix

PA

L

I/O I/O I/O

MC

MC

MC

PA

L

I/O I/O I/O

MC

MC

MC

PA

L

I/O MC

MC

MC

I/O I/O

PA

L

I/O MC

MC

MC

I/O I/O

4-20

XC9500XL Family (Xilinx)

4-21 4-22

4-23 4-24

5

4-25 4-26

Another user-prog. devices:Field Programmable Gate Arrays (FPGA)

4-27

4. Economics of ASICFixed costs

FPGA G.A. S.C.

Training (days) 2 5 5

$400 / day $800 $2,000 $2,000

Hardware $10,000 $10,000 $10,000

Software $1,000 $20,000 $40,000

Design (10k gates)

gates / day 500 200 200

days 20 50 50

$400 / day $8,000 $20,000 $20,000

Production test design 0 5 days 5 days

0 $2,000 $2,000

NRE 0 $30,000 $70,000

masks 0 (3÷4) $10,000 (15+)$50,000

simulation 0 $10,000 $10,000

test 0 $10,000 $10,000

Second source (5days) (5days) (5days)

$2,000 $2,000 $2,000

Total $21,800 $86,000 $146,000 4-28

Unit costs

FPGA G.A. S.C. unit

Wafer size 6 6 6 inches

Wafer cost 1,400 1,300 1,500 $

Design size 10k 10k 10k gates

Density 10k 20k 25k gates/cm2

Utilization 60% 85% 100%

Die size 1.67 0.59 0.40 cm2

Die / wafer 88 248 365

Defect density 1.10 0.90 1.00 cm-2

Yield 65% 72% 80%

Die cost 25 7 5 $

Profit margin 60% 45% 50%

Price / gate 0.39 0.10 0.08 cents

Part cost 39 10 8 $

4-29

„Time to market”:

Comparison:

4-30

5. Technologies of User-Programmable Devices

Fuses

6

4-31

Antifuses

Actel: PLICE (Programmable Low-Impedance Circuit Element)

QuickLogic: ViaLink

4-32

n+ Source n+ Drain

P-Type Silicon

VPP

VD < VPP

floating gate access gate

thin gate oxide

Fig. Altera

EPROM

FAMOS: Floating gate Avalanche injection MOS transistor

4-33

n+ Source n+ Drain

EEPROM

FLOTOX: Floating gate Thin Oxide MOS transistor

4-34

IC1

TDI TDOTCK TMS

IC2

TDI TDOTCK TMS

IC3

TDI TDOTCK TMS

TMS

TDI

TCK

TDO

JTAG Standard(Joint Test Action Group)

Device chain

4-35

Boundary Scan logic

4-36

State diagram for the TAP controller