Wafer Level Packaging Platforms for Rapidly Growing Mobile Market

Steve Anderson

Sr Director, Product Technology Marketing STATS ChipPAC

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Comprehensive platform of wafer level technology solutions for the rapidly growing mobile market enabling new lithography nodes and shift to 3D

Fan-in wafer level packaging – FIWLP Fan-out wafer level packaging – FOWLP Integrated passive devices – IPD 2.5/3D Integration options – from embedded solutions through TSV Summary

Development of Cost Effective Wafer Level Platforms & Technologies

Agenda

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Smartphones and Tablets are Today’s Key Growth Drivers

Smartphone and Tablet growth driving demand for advanced packaging technologies served by the flexible Wafer Level Packaging platforms

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Mobile Demand Drives High Growth for WLP Solutions

Mobile Convergence is a major driver for Wafer Level Packaging driving increased embedding and 3D integration

Source: Yole

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Mobile Convergence Driving High Performance, Cost Effective Packaging

1. Smartphone/Tablet Demand/Price Outlook

3. Processor Architecture 4. Integration – AP/BB, Connectivity, PM, RF etc Gartner, iSuppli, Others

2010 2011 2012 2013 2014 2015

Linley Group

2. Power per unit Performance

Gartner

2xnm

114nm

2xnm

Application Processo

r Baseband DRAM

NAND Flash

RFIC

PA

PMIC

Audio/Video Codec

WiFi BT/FM

GPS NFC

E-compass

Gyroscope

Accelerometer

Touch screen Controller

Sensors

Other Controllers

Graphics Processor

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Mobile Convergence is Driving Device Integration

Year YoY % Semi Industry’s Growth Themes

Smartphone Next 3 years CAGR >21%

2012

2014

0%

8.9%

Tablet PC Next 3 years CAGR >24%

‘ Digitization’ & ‘Cloud’

‘4G LTE’ & ‘Mobile Infotainment’

$318B

$368B

Sources: Gartner DQ, NVR & JPM

Impact to Hardware Convergence Theme

Continuous quest for: • High speed • High bandwidth • Low power • Lower cost • Smaller form-factor • Greater thermal performance • Faster time-to-market

Si-level

Wafer-level

Package-level

• Integration of dissimilar ICs without off-chip penalty • Small form factor (thickness) • Power consumption

• Die shrinkage by advanced silicon • Small form factor (thickness) • Performance & cost

• Fast time to market • Small form factor • Performance at low cost

2013 6.3%

$338B

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Integration Requirements are Driving Silicon Platform Growth

Cost Lowest cost solution, proven

reliable BOM

Performance Excellent mechanical, electrical &

thermal performance

Si-level

Wafer-level

Package-level

• Integration of dissimilar ICs without off-chip penalty • Small form factor (thickness) • Power consumption

• Die shrinkage by advanced silicon • Small form factor (thickness) • Performance & cost

• Fast time to market • Small form factor • Performance at low cost

Si-level

Wafer-level

Package-level

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Silicon Platform Growth Drives High Density and 3D Packaging

WLP and 2.5/3D Technology Development • Fan-In WLP

• Fan-Out WLP

• IPD

• TSV/2.5/3D

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Silicon Integration Business Model Approaches for 2.5/3D

• Customers have alternative Business Models to address support of 2.5/3D solutions:

Captive 3D Model Collaborative 3D Model

Standard Foundry/OSAT Model

• End-to-end manufacturing controlled by the Foundry

• Integrated process that attaches silicon chips to wafer through Chip-on- Wafer (CoW) bonding then attaches to substrate (CoWoS) for final package

• Includes wafer fabrication, TSV, micro bump, backside processes and assembly

Foundry Front-end-of-line

(FEOL)

Mid-end-of-line (MEOL)

Back-end-of-line (BEOL)

Foundry Front-end-of-line

(FEOL)

Back-end-of-line (BEOL)

• Collaborative open ecosystem between Foundry and OSAT

• Foundry TSV process seamlessly integrated with BEOL wafer thinning, backside integration, fine pitch copper pillar bump and precision chip-to-chip 3D stacking

• Proven and reliable 3D TSV solution

Foundry Front-end-of-line

(FEOL)

OSAT Back-end-of-line

(BEOL)

• Cost effective business model between Foundry and OSAT

• Fan-out Wafer Level Packaging (FOWLP) enables 3D interconnect without the use of TSV

• 2.5D/3D solutions using established supply chain and proven manufacturing processes

OR

3D TSV die stacking 3D SiP eWLB

OSAT Mid-end-of-line

(MEOL)

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Wafer Level Packaging -> Powerful Platform for Silicon Integration

Interconnect line length () Operating frequencies () Package Speed () Parasitics

Electrical Performance Pitches ()

No standards Small chips/ high no. of I/Os

I/O Density Wafer Level

Packages

• Batch processing • High parallelism • Improved test concepts

• Smallest package heights • Minimum lateral area

• Min line length • Multilayer RDL • Reduced no. of • interconnects

• Integrated passives in RDL • SiP/ 3D capability

• Improved chip to board coupling

• Min pitches

Power consumption () Package Density ()

Thermal Performance

Integrated Passives (R, L, C) System in Package 3D

Functionality (Integration)

Dimensions Package height () Lateral dimensions ()

Packaging cost Test cost Panel size

Cost

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Wafer Level Packaging -> Performance and Cost Tradeoffs

• Different performance improvement schemes have different power sensitivities • Application Processor performance evolution may be generally viewed as driven by

three individual vectors - Frequency, Memory Bandwidth and # Processing Cores • 2.5/3DIntegration promises a power-efficient trajectory for improving performance by

reducing parasitics and increasing bandwidth while reducing package size and weight

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Solder ball

Cu-RDL

Si Chip

EMC

UBM

RDL (Al,Cu)

Si Chip

Solder ball

Fan-in Conventional WLP Fan-out WLP – footprint larger than die

Fan-out WLP Solutions Evolving in Addition to Fan-in WLP

Comparison between Fan-in vs Fan-out WLP • Fan-out WLP enables embedded and multi-die

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Fan-out WLP Solutions Enable Performance and Integration

Thinner single die and multi-chip packages

Enhanced routability and scaling (<10/10um LS, multi-layer RDL)

Ultra-fine ball and pad pitch (300um/50um)

Excellent electrical and thermal performance

Compliance with advanced Si nodes

Inherent 3D integration - single and double sided, embedded IPD and SMT

Scalability to a larger panel production

Multi-environment co-design with silicon, package, PCB

A step forward in scalable heterogeneous integration with improved electrical performance in a thin, robust, cost effective package

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Fan-out WLP Platform Expands Embedded 2.5/3D Applications

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Fan Out WLP Enables IPD Integration for Performance

IPD Coils/Inductors on RDL Plated Cu RDL IPD FO Embedding

Higher level of integration and performance increase with optimized design

FO embedding with IPD and Inductors

IPD, SMD/discrete embedding

EMC

IPD embedding

0201 MLCC

RDL Passivation Layers

IPD Chip for Capacitors

Mold Material

Bump for eWLB Package

CMOS PA Chip

Inductors in RDL Layers

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Co-Design Approach is Key for Optimizing WLP Solutions & Cost

Design Range*

# Designs Today (% of

population)

Optimum Package Portfolio (for lowest cost) Typical Device/ Product

Today’s Solutions

Potential Solutions (for lowest cost)

2013/14

Potential Solutions (for lowest cost)

2015+

FR* < 1 20% Fan-in

Fan-in

Wafer-Level Fan-in/Fan-out

(45-60%)

PM, Analog, Connectivity

FR* ~ 1 - 2.2 35 % fcFBGA Fan-out

Base Band/ Application Processor,

Connectivity FR* ~ 2.2 - 5 40% fcFBGA

Flip Chip (35 - 50%)

FR* > 5 < 10% fcBGA fcBGA

AP (Tablet), Infra Devices Wafer-Level 2.5/3D

(<10%) FO 2.5D

* FR= Fan-out Ratio, defined as ratio of I/O density exiting die to I/O density exiting package (approx equals ratio of pkg to die area )

• IC designs can be mapped into optimum package solutions based on “Fan-out Ratio” (FR) • Wafer-level Packaging is expected to provide the lowest cost solution for more products long term

Proper Co-design is critical for optimizing the body size and footprint while also ensuring the best performance and cost scaling – possible transitions:

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Mobile Data Performance is Driving Higher Bandwidth Dichotomy

• System power becomes unmanageable with faster Memory given parasitic loads today • Large increases in bandwidth have to be used as an alternative to boost performance -

enabled by the very high I/O with short interconnect paths - made possible by 3D/2.5D TSV integration

Pwr => frequency x parasitic loading x bandwidth; Bandwidth => frequency x data bus width

* Courtesy of Bryan Black, AMD

Influence of Memory Speed & Bandwidth on System Power & Performance*

Processor integration with Memory; high band width with low parasitics achieved through 2.5D or 3D interconnect

Processor Memory Memory

2.5D 3D

Processor

Key new 2.5/3D interconnect technology in development is addressing high bandwidth and performance imperatives – test challenges remain

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2.5/3D Silicon Integration Enables Finer Pitches, Line/Spaces

Key new 2.5/3D interconnect technology in development is addressing vertical interconnects, finer bump pitches, and finer line/spacing on RDL/Substrates

• Through Silicon Vias (TSV) and thin die and improved wafer handling • Thermo-compression Bonding (TCB) and NCP (non-conductive paste) • Micro-bumps and Copper bumping technologies

3D IC TSV with top Die (40/50um bump pitch)

40um pad pitch with Ni/Au pad finish

Chip-to-Substrate

Chip-to-Chip

40/80um and 50um pitch Cu column on Substrate

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Cu Column Temp. Bond

Via Expose, UBM

Debond

Cu Col Bumping Bond to Carrier Thin, CMP, Insulate, UBM

Debond

Dicing FC Attach-1 FC Attach-2 BGA Processes

BEOL MEOL

1 2 3 4

2.5D

3D

Test Integration poses additional challenges for testing both more complex embedded capabilities as well as vertical interconnections with high speed and bandwidth requirements

• 2.5D/3D TSV test steps are not well defined and still under discussion • Looking into the process flow and analyzing where are the possible test insertion points

Integrating test platforms is a key requirement as panel sizes increase and vertical packaging interconnections must be verified and memory bandwidth tested

Integrating Test for WLP, 3D, Panel – MEOL / BEOL Assembly

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Wafer Level Packaging Transitioning to Key Product Segments

Application/ Baseband Processor

wbPoP wbPiP

FBGA-SD

FBGA-SD

eWLB

fcBGA (Tablet)

FC- SiP FBGA-SD or SS

fcPoP-MLP

fcPoP – bare die

fcPiP

FBGA-SD

eWLB-SiP

Fan-out (eWLB)-PoP

3D TSV

eWLB

eWLB

fcFBGA FBGA

FBGA

FBGA

WLCSP

WLCSP

WLCSP

FBGA WLCSP Leaded

Leaded

Leaded FBGA WLCSP

Leaded

PoP/FBGA- 3D TSV

fcCuBE

PAST CURRENT FUTURE

Wafer level Fan-out & TSV technologies for next generation mobile requirements

fcPoP MLP exp die (fcCuBE)

WLCSP

FC- SiP WLCSP

FBGA

FBGA WLCSP Leaded

WLCSP

fcFBGA FBGA WLCSP

Interface & Sensors

Connectivity

Power Management

Memory

Radio Frequency

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Summary – WLP Platforms Provide Integration and Performance

The market for mobile devices such as smartphones is rapidly growing and driving demand for more compact semiconductor packages with increased performance and packaging complexity. Wafer level technology effectively accommodates new lithography nodes and provides a

strong packaging platform to address the industry’s shift to 2.5D and 3D integration. Wafer Level Packaging providing higher bandwidth, ultra high density, embedded

capabilities, and improved thermal dissipation in a small, thin package format Wafer level technology options are being addressed as alternatives for small flip chip and

large QFN packages Higher memory bandwidth is driving packaging trends for higher density requiring new

wafer level technology and interconnections solutions for 2.5D and 3D integration The importance of managing a tight co-design process and silicon optimization in an

increasingly cost sensitive market is key and providing a range of solutions that are cost effective and scalable

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