1

3BA5, 18th Lecture, M. Manzke,Page: 1

Wallace Tree MultiplierExample from Lecture (11)

CSA 1 CSA 2

CSA 3 CSA 4

CSA 5

CSA 6

X Register

Y

Y0

Y1

Y7

8 X 56 AND Array

X0X1X55

P0P1P2P3P4P5P6P7

CLA

Z

←1←2←3←4←5←6←7

3BA5, 18th Lecture, M. Manzke,Page: 2

AND Array (4-bit)

M1

M2

M3

M4

xy

3BA5, 18th Lecture, M. Manzke,Page: 3

PipelinedWallace Tree Multiplier

Latch

AND Array

X

Latch

y

Latch

M4

Latch

M3

Latch

M2

Latch

M18 8 8 8

44

CSA

Latch LatchLatch

C S←1

CSA

Latch Latch

C S←1

CLA 3BA5, 18th Lecture, M. Manzke,Page: 4

Instruction Pipelines and Arithmetic Pipelines

Can be static or dynamic.Static: Must be drained before a different operation is performedDynamic: Can perform more than one operation at the same time

e.g. multiplication and addition

Latch Stage 1 Latch Stage 2 Latch Stage 3

Three stage dynamic pipeline

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3BA5, 18th Lecture, M. Manzke,Page: 5

Instruction Pipelines

The von Newmann architecture execates an instruction cycle which may be decomposed into these stages:

IF = Instruction fetch from cache or memoryID = Instruction decodeOF = Operand fetch from register, cache or memoryEX = Apply operator to operand(s)WB = Write back the results to register, cache or memory

3BA5, 18th Lecture, M. Manzke,Page: 6

Stages of an Instruction Pipeline

Latch

IF

Latch

ID

Latch

OF

Latch

EX

Latch

WB

Stage 1

Stage 2

Stage 3

Stage 4

Stage 5

RegiestersMemoryCaches

i4

i3

i2

i1

1 2 3 4 5 6 7 8

IF ID OF EX WBIF ID OF EX WB

IF ID OF EX WBIF ID OF EX WB

Cycles

3BA5, 18th Lecture, M. Manzke,Page: 7

Pipelined Computer

3BA5, 18th Lecture, M. Manzke,Page: 8

Instruction Pipe HazardsIF and ID

IF - Instruction FetchAn on-chip cache adjacent to the IF stage

which maintains block prefetching ensures a constant supply of instructions

Until a branch is taken.Thus branches are classified as control hazards.

ID - Instruction DecodingNo hazards and complete we know:

What functional unit is requieredWhere the operand(s) resideWhere the results must go

3

3BA5, 18th Lecture, M. Manzke,Page: 9

Instruction Pipe HazardsOF – Structural Hazards

OF – Operand FetchTwo classes of hazards may delay the

issue of the instruction to the EX stageStructural hazardsNo funtional circuit availableeg i1 R3 ← R1 ÷ R2

i2 R6 ← R4 ÷ R5

Delay i2 – EX until i1 - WB

3BA5, 18th Lecture, M. Manzke,Page: 10

Instruction Pipe HazardsOF – Data Hazards

Data hazard (data dependency) Instructions which refer to results or locations which are associated with preseding but incomplete instructions

We must preserve the function prescribed by the program