weak sram cell fault model and a dft technique
DESCRIPTION
Weak SRAM Cell Fault Model and a DFT Technique. Outline. Background and motivation SRAM issues: noise, SNM, weak cells SRAM SNM sensitivity analysis vs. process variation vs. non-catastrophic defect resistance vs. operating conditions Programmable weak SRAM cell fault model - PowerPoint PPT PresentationTRANSCRIPT
Weak SRAM Cell Fault ModelWeak SRAM Cell Fault Model andand
a DFT Techniquea DFT TechniqueMohammad Sharifkhani,
with special thanks to
Andrei PavlovUniversity of Waterloo
2
OutlineOutline
Background and motivationSRAM issues: noise, SNM, weak cells
SRAM SNM sensitivity analysisvs. process variationvs. non-catastrophic defect resistancevs. operating conditions
Programmable weak SRAM cell fault model
DFT for weak cell detectionDetection conceptImplementation
Conclusions
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Static
Process offsets and mismatches
Operating conditions variations
Dynamic
Cross-talk
Ripples in power rails
-particles
Most of dynamic sources are quasi-static
Noise SourcesNoise Sources
4
D
D
D
D
y
x
v
u
SNM
450
What is SNM?What is SNM?
2SNMD
Seevinck et al, JSSC’87
SNM = max static noise, which can be tolerated by an SRAM cell without changing its logical state
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Vnode A
Vnode B
SNMtyp
VDD
VDD
Vgood
What is a weak SRAM cell?What is a weak SRAM cell?BLBBL
WL
driver-1 driver-2
load-2load-1
access-1 access-2
A BLet’s consider a standard
6T SRAM cell:
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Vnode A
Vnode B
SNMtyp
SNMweak
VDD
VDD
Vweak
Vgood
What is a weak SRAM cell?What is a weak SRAM cell?
Weak cell = a cell with inadequate SNM that can be easily flipped
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Why Test Weak SRAM Cells?Why Test Weak SRAM Cells?
Because weak SRAM cells:
Prone to stability faults
Manifest reliability problems
Can signify defects, which…
Escape regular march tests
8
What Does SNM Depend On?What Does SNM Depend On?Process variation (mismatch / offset):
VTH spreadLEFF, WEFF spread
Resistance of non-catastrophic defects:RBREAK
RBRIDGE
Operation conditions:VBL
VDD
VWL
T0C
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Static Noise MarginStatic Noise Marginas a Function of Process Variation as a Function of Process Variation
all results for 0.13um technology, all results for 0.13um technology, read-accessed cellread-accessed cell,,
i.e. V i.e. VWLWL=V=VBLBL=V=VDDDD
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SNM vs. VSNM vs. VTHTH (Single Transistor) (Single Transistor)
Typical process
corner
SNM=100% @ zero
VTH deviation
Driver strongest
impact, load
weakest impact
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SNM vs. VSNM vs. VTH TH (Single Transistor)(Single Transistor)
Typical + slow
process corners
For slow:
SNM>100% @ zero
VTH deviation
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SNM vs. VSNM vs. VTH TH (Single Transistor)(Single Transistor)
Typical + slow +
fast process
corners
For fast:
SNM<100% @
zero VTH deviation
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SNM vs. VSNM vs. VTH TH (Multiple Transistors)(Multiple Transistors)
Typical process
corner
One VTH changes,
while some other
are biased
Strong SNM
decline for some
VTH combinations
(at max asymmetry)
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SNM vs. LSNM vs. Leffeff and W and Weff eff (Single Transistor)(Single Transistor)
SNM=100% for
typical geometry
Geometry
variations – weak
impact on SNM
(max 7%)
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Static Noise MarginStatic Noise Marginas a Function of Non-Catastrophic as a Function of Non-Catastrophic
Defect ResistanceDefect Resistance
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SNM vs. Break ResistanceSNM vs. Break Resistance
Rbreak SNM
SNM vs. gate
breaks weak
dependence
SNM vs. driver
breaks strong
dependence
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SNM vs. Bridge ResistanceSNM vs. Bridge Resistance
Rbridge SNM
SNM vs. Rbridge
uniform
dependence
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Static Noise MarginStatic Noise Marginas a Function of Operation as a Function of Operation
Conditions Conditions
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SNM vs. Bit Line VoltageSNM vs. Bit Line Voltage
Typical process
If VBL>0.8V
SNM=100%
If VBL<0.35V
SNM=0% - hard
failure ( normal write)
If 0.35V<VBL>0.8V
SNM linearly
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SNM vs. Bit Line VoltageSNM vs. Bit Line Voltage
Typical + slow
process corners
VBL>0.8V
SNM>100%
VBL<0.35V
SNM=0% - hard
failure (or normal
write)
0.35V<VBL>0.8V
SNM linearly
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SNM vs. Bit Line VoltageSNM vs. Bit Line Voltage
Typical + slow + fast
process corners
VBL>0.8V
SNM<100%
VBL<0.35V
SNM=0% - hard
failure (or normal
write)
0.35V<VBL>0.8V
SNM linearly
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SNM vs. Global VSNM vs. Global VDDDD
Typical + slow +
fast process
corners (extreme
cases)
SNM linearly
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SNM vs. Local VSNM vs. Local VDDDD
Local resistive
break in local VDD
Typical + slow +
fast process
corners (extreme
cases)
@VDD_LOCAL<0.8V
SNM=0
@VDD_LOCAL>0.8V
SNM linearly
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SNM vs. Word Line VoltageSNM vs. Word Line Voltage
Typical process
Read-accessed
SRAM cell (SNM
deviation @VWL=VDD0%)
@VWL <VTH_ACCESS
SNM=max
@VWL >VTH_ACCESS
SNM linearly
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SNM vs. Word Line VoltageSNM vs. Word Line Voltage
Typical + slow
process corners
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SNM vs. Word Line VoltageSNM vs. Word Line Voltage
Typical + slow +
fast process
corners
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SNM vs. TemperatureSNM vs. Temperature
Weak
dependence
10% max (fast )
2.5% min (slow)
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Proposed Weak Cell Fault Model Proposed Weak Cell Fault Model and a Programmable DFT and a Programmable DFT
TechniqueTechnique
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Weak cell fault modelWeak cell fault model
SNM vs. node-
node R
@Rnode-node
[50k,500k] –
linear
dependence
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BLBBLWL
node A node B
node A node B
Weak cell fault modelWeak cell fault model
• Resistor between
nodes A and B
• Which is equivalent to
• Negative feedback for
inverters of an SRAM
cell
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Vnode A
Vnode B
SNMtyp
SNMweak
VDD
VDD
Vweak
Vgood
Programmable detection conceptProgrammable detection concept
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Vnode A
Vnode B
SNMtyp
SNMweak
VDD
VDD
Vweak
Vgood
VTEST
Programmable detection conceptProgrammable detection concept
@ VTEST:
•weak cell flips
•good cell does not flip
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Vnode B
R = 0 10.5
Vnode A
node voltage R
Proposed DFT conceptProposed DFT concept
R number of cells with state "0" in a set of cellsn
n
• Changing of ratio R
brings nodes to
different potentials
• Weak cell will flip and
will be detected
• Good cell will retain
data
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write 0/1 ratio R
Ø prechargeØ enable n WLsØ short BLsØ disable n WLsØ release BLs
read n cells back
invert ratio R
more 0/1 ratiosto test?
select next 0/1 ratio
FINISH
yes
no
START
Proposed DFT AlgorithmProposed DFT Algorithm
1. Write background
ratio of zeroes and
ones
2. Normal precharge
3. Enable n word
lines
4. Right after that
short bit lines
5. Release word lines
6. Release bit lines
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WD
Word Line decoder
WD logic
WD
WLn
WL3
WL2WL1
Proposed DFT ImplementationProposed DFT Implementation
1. Write background
ratio of zeroes and
ones
2. Normal precharge
3. Enable n word lines
4. Right after that short
bit lines
5. Release word lines
6. Release bit lines
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Proposed DFT Simulation ResultsProposed DFT Simulation Results
• Rweak=200k
(~65% SNM)
• Five “0”,
three ”1”
• Weak cell is
detected!
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Proposed DFT Simulation ResultsProposed DFT Simulation Results
• Rweak=200k
(~65% SNM)
• Three “0”,
five ”1”
• Weak cell is
not detected
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Proposed DFT detection capabilityProposed DFT detection capability
• Rweak=100k-
500k
• Five “0”,
three ”1”
• Weak cell
flips for
Rweak<200k
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ConclusionsConclusions
Weak SRAM cells can escape march tests
need DFT
Cell stability is sensitive to process and
operation disturbances
Weak cell fault model is essential in developing
test techniques
Proposed DFT efficiently detects weak SRAM
cells, i.e. cells with inadequate SNM