UNIT I

BINARY SYSTEMS

1. DIGITAL SYSTEMS,BINARY NUMBERS & NUMBER BASE CONVERSION

A digital system can understand positional number system only where there are a few symbols called digits and these symbols represent different values depending on the position they occupy in the number.

A value of each digit in a number can be determined using

The digit

The position of the digit in the number

The base of the number system (where base is defined as the total number of digits available in the number system).

The term digital refers to the fact that the signal is limited to only a few possible values. In general, digits signals are represented by only two possible voltages on a wire - 0 volts (which we called "binary 0", or just "0") and 5 volts (which we call "binary 1", or just "1"). We sometimes call these values "low" and "high", or "false" and "true".Definition:

A digital system is an interconnection of digital modules and it is system that manipulates discrete elements of information that is represented internally in the binary form.

Characteristics of digital system:1. Digital systems manipulate elements of information2. Discrete elements are nothing but the digits such as 10 decimal digits ,26 letters of alphbets 3. Digital systems use physical quantities called signals to represent discrete elements.4. In digital systems, the signals have two discrete values & there fore said to be binary.5. A signal in digital system represents one binary digit ,called a bit, the bit has a value either

0 or 1.6. Discrete elements of information are represented with group of bits called binary codes.

Advantages of digital system:1. Dramatic cost reductions in digital devices have come about because of advances in digital

integrated circuit technology.2. Equipment built with digital integrated circuits can perform at a speed of hundreds of

millions of operations per second .3. Digital sysems can be made to operate with extreme reliability by using error correcting

codes.

Decimal Number System

The number system that we use in our day-to-day life is the decimal number system. Decimal number system has base 10 as it uses 10 digits from 0 to 9. In decimal number system, the successive positions to the left of the decimal point represent units, tens, hundreds, thousands and so on.

Each position represents a specific power of the base (10). For example, the decimal number 1234 consists of the digit 4 in the units position, 3 in the tens position, 2 in the hundreds position, and 1 in the thousands position, and its value can be written as

(1×1000) + (2×100) + (3×10) + (4×l)

(1×103) + (2×102) + (3×101) + (4×l00)

1000 + 200 + 30 + 1

1234

Number System & Description

1 Binary Number System Base 2. Digits used: 0, 1

2 Octal Number System Base 8. Digits used: 0 to 7

3 Hexadecimal Number System Base 16. Digits used: 0 to 9, Letters used: A- F

Binary Number System

Characteristics

Uses two digits, 0 and 1.

Also called base 2 number system

Each position in a binary number represents a 0 power of the base (2). Example: 20

Last position in a binary number represents an x power of the base (2). Example: 2x where x represents the last position - 1.

Example

Binary Number: 101012

Calculating Decimal Equivalent −

Step Binary Number Decimal Number

Step 1 101012 ((1 × 24) + (0 × 23) + (1 × 22) + (0 × 21) + (1 × 20))10

Step 2 101012 (16 + 0 + 4 + 0 + 1)10

Step 3 101012 2110

Note: 101012 is normally written as 10101.

Octal Number System

Characteristics

Uses eight digits, 0,1,2,3,4,5,6,7.

Also called base 8 number system

Each position in an octal number represents a 0 power of the base (8). Example: 80

Last position in an octal number represents an x power of the base (8). Example: 8x where x represents the last position - 1.

ExampleOctal Number − 125708

Calculating Decimal Equivalent −

Step Octal Number Decimal Number

Step 1 125708 ((1 × 84) + (2 × 83) + (5 × 82) + (7 × 81) + (0 × 80))10

Step 2 125708 (4096 + 1024 + 320 + 56 + 0)10

Step 3 125708 549610

Note: 125708 is normally written as 12570.

Hexadecimal Number System

Characteristics

Uses 10 digits and 6 letters, 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F.

Letters represents numbers starting from 10. A = 10, B = 11, C = 12, D = 13, E = 14, F = 15.

Also called base 16 number system.

Each position in a hexadecimal number represents a 0 power of the base (16). Example 160.

Last position in a hexadecimal number represents an x power of the base (16). Example 16x where x represents the last position - 1.

Example −Hexadecimal Number: 19FDE16

Calculating Decimal Equivalent −

Step Binary Number Decimal Number

Step 1 19FDE16 ((1 × 164) + (9 × 163) + (F × 162) + (D × 161) + (E × 160))10

Step 2 19FDE16 ((1 × 164) + (9 × 163) + (15 × 162) + (13 × 161) + (14 × 160))10

Step 3 19FDE16 (65536 + 36864 + 3840 + 208 + 14)10

Step 4 19FDE16 10646210

Note − 19FDE16 is normally written as 19FDE.

Number Base Conversions

There are many methods or techniques which can be used to convert numbers from one base to another. We'll demonstrate here the following −

Decimal to Other Base System Other Base System to Decimal Other Base System to Non-Decimal Shortcut method − Binary to Octal Shortcut method − Octal to Binary Shortcut method − Binary to Hexadecimal Shortcut method − Hexadecimal to Binary

Decimal to Other Base System

Two methods. 1) For integer part using successive division method.

2) For fractional part using successive multiplication method.

Decimal to binary

Example −Decimal Number: 2910

Calculating Binary Equivalent −Step Operation Result RemainderStep 1 29 / 2 14 1Step 2 14 / 2 7 0Step 3 7 / 2 3 1Step 4 3 / 2 1 1Step 5 1 / 2 0 1As mentioned in Steps 2 and 4, the remainders have to be arranged in the reverse order so that the first remainder becomes the Least Significant Digit (LSD) and the last remainder becomes the Most Significant Digit (MSD). Decimal Number − 2910 = Binary Number − 111012.

Decimal to octal

Octal to decimal conversion:

Ex: convert 4057.068 to octal

=4x83+0x82+5x81+7x80+0x8-1+6x8-2

=2048+0+40+7+0+0.093

=2095.093710

Decimal to hexadecimal

Other Base System to Decimal SystemSteps

Step 1 − Determine the column (positional) value of each digit (this depends on the position of the digit and the base of the number system).

Step 2 − Multiply the obtained column values (in Step 1) by the digits in the corresponding columns.

Step 3 − Sum the products calculated in Step 2. The total is the equivalent value in decimal.

Example Binary Number − 111012

Calculating Decimal Equivalent −

Step Binary Number Decimal Number

Step 1 111012 ((1 × 24) + (1 × 23) + (1 × 22) + (0 × 21) + (1 × 20))10

Step 2 111012 (16 + 8 + 4 + 0 + 1)10

Step 3 111012 2910

Binary Number − 111012 = Decimal Number − 2910

Hexadecimal to Decimal conversion:

Ex: 5C716 to decimal

(5x162)+(C x161)+ (7 x160)

=1280+192+7.

=14710

Other Base System to Non-Decimal SystemSteps

Step 1 − Convert the original number to a decimal number (base 10).

Step 2 − Convert the decimal number so obtained to the new base number.

ExampleOctal Number − 258

Calculating Binary Equivalent −

Step 1 − Convert to DecimalStep Octal Number Decimal Number

Step 1 258 ((2 × 81) + (5 × 80))10

Step 2 258 (16 + 5 )10

Step 3 258 2110

Octal Number − 258 = Decimal Number − 2110

Step 2 − Convert Decimal to BinaryStep Operation Result Remainder

Step 1 21 / 2 10 1

Step 2 10 / 2 5 0

Step 3 5 / 2 2 1

Step 4 2 / 2 1 0

Step 5 1 / 2 0 1

Decimal Number − 2110 = Binary Number − 101012

Octal Number − 258 = Binary Number – 1010

Binary to Octal conversion:

Starting from the binary pt. make groups of 3 bits each, on either side of the binary pt, & replace each 3 bit binary group by the equivalent octal digit.

Hexadecimal to binary:

Replace each hex digit by its 4-bit binary group.Ex: 4BAC10 to binary

Convert 110101.1010102 to octal Group of 3110 101 .

6 5 .

101 010

5 2

=65.528

4 B A C0100 1011 1010 1100

=01001011101011002

Shortcut method - Binary to OctalSteps

Step 1 − Divide the binary digits into groups of three (starting from the right).

Step 2 − Convert each group of three binary digits to one octal digit.

ExampleBinary Number − 101012

Calculating Octal Equivalent −

Step Binary Number Octal Number

Step 1 101012 010 101

Step 2 101012 28 58

Step 3 101012 258

Binary Number − 101012 = Octal Number − 258

Shortcut method - Octal to BinarySteps

Step 1 − Convert each octal digit to a 3 digit binary number (the octal digits may be treated as decimal for this conversion).

Step 2 − Combine all the resulting binary groups (of 3 digits each) into a single binary number.

ExampleOctal Number − 258

Calculating Binary Equivalent −

Step Octal Number Binary Number

Step 1 258 210 510

Step 2 258 0102 1012

Step 3 258 0101012

Octal Number − 258 = Binary Number − 101012

Shortcut method - Binary to HexadecimalSteps

Step 1 − Divide the binary digits into groups of four (starting from the right).

Step 2 − Convert each group of four binary digits to one hexadecimal symbol.

ExampleBinary Number − 101012

Calculating hexadecimal Equivalent −

Step Binary Number Hexadecimal Number

Step 1 101012 0001 0101

Step 2 101012 110 510

Step 3 101012 1516

Binary Number − 101012 = Hexadecimal Number − 1516

Shortcut method - Hexadecimal to BinarySteps

Step 1 − Convert each hexadecimal digit to a 4 digit binary number (the hexadecimal digits may be treated as decimal for this conversion).

Step 2 − Combine all the resulting binary groups (of 4 digits each) into a single binary number.

ExampleHexadecimal Number − 1516

Calculating Binary Equivalent −

Step Hexadecimal Number Binary Number

Step 1 1516 110 510

Step 2 1516 00012 01012

Step 3 1516 000101012

Hexadecimal Number − 1516 = Binary Number − 101012

QUESTIONS:

1. Convert the decimal number 250.5 to base 3, base5, base4, base7, base8 & base16.2. Convert the binary 1110001.110 to decimal, octal, & hexadecimal.3. Convert the hexadecimal 2AC5.D to decimal, octal & binary.4. Convert the octal 623.77 to decimal, binary & hexadecimal.5. List the first 16 numbers in base 12. Use the letters A and B to represent two digits.6. Convert the following (i)(BC)16= ( )10 (ii)(2314)8= ( )10 (iii) (1000011)2 = ( )10 (iv) (647)10=( )16

7. Convert the following to Decimal and then to Hexadecimal. ( i) 12348 (ii) 110011112.8. Convert the following numbers with indicated bases to decimal:(12121)3, (4312)5, (198A)12.

9. Determine the value of base x if (211)x=(152)8.

10. Convert the given decimal number 234 to binary, quaternary, octal, hexadecimal11. What weight does the digit have in each of the following decimal number a)1530 b)1.059 c) 3259 d)567.912. convert 1000110111110111012 to hexadecimal13. convert A92H to octal 2.COMPLEMENTS & SIGNED BINARY NUMBERS

Complements

Complements are used in the digital computers in order to simplify the subtraction operation and for the logical manipulations. For each radix-r system (radix r represents base of number system) there are two types of complements.

S.N.

Complement Description

1 Radix ComplementThe radix complement is referred to as the r's complement

2 Diminished Radix ComplementThe diminished radix complement is referred to as the (r-1)'s complement

Binary system complements

As the binary system has base r = 2. So the two types of complements for the binary system are 2's complement and 1's complement.

1's complementThe 1's complement of a number is found by changing all 1's to 0's and all 0's to 1's. This is called as taking complement or 1's complement. Example of 1's Complement is as follows.

2's complementThe 2's complement of binary number is obtained by adding 1 to the Least Significant Bit (LSB) of 1's complement of the number.

2's complement = 1's complement + 1

Example of 2's Complement is as follows.

Binary arithmetic is essential part of all the digital computers and many other digital system.

9’s & 10’s Complements:

It is the Subtraction of decimal no.s can be accomplished by the 9‘s & 10‘s compliment methods similar to the 1‘s & 2‘s compliment methods of binary . the 9‘s compliment of a decimal no. is obtained by subtracting each digit of that decimal no. from 9. The 10‘s compliment of a decimal no is obtained by adding a 1 to its 9‘s compliment.

Example: 9‘s compliment of 3465 and 782.54 is 9999 999.99-3465 -782.54---------- -----------6534 217.45------------------ --------------------

10‘s complement of 4069 is9999

- 4069---------- 5930

+1---------- 5931-----------

UNSIGNED BINARY NUMBERS

Binary Addition

It is a key for binary subtraction, multiplication, division. There are four rules of binary addition.

In fourth case, a binary addition is creating a sum of (1 + 1 = 10) i.e. 0 is written in the given column and a carry of 1 over to the next column.

Example − Addition

Binary SubtractionSubtraction and Borrow, these two words will be used very frequently for the binary subtraction.

There are four rules of binary subtraction.

Example − Subtraction

Advantage of 2,s complement:A-B=A+2, s complement

Binary MultiplicationBinary multiplication is similar to decimal multiplication. It is simpler than decimal multiplication

because only 0s and 1s are involved. There are four rules of binary multiplication.

Example − Multiplication

Binary DivisionBinary division is similar to decimal division. It is called as the long division procedure.

Example − Division

SIGNED BINARY NUMBERS:

There are three ways of representing signed binary numbers.

1. signed-magnitude representation

2. signed 1’s complement representation

3. signed 2’s complement representation

1. signed-magnitude representation: In this representation the most significant bit indicates the sign, if it is 0 that represents +ve number & if it is 1 that represents –ve number and remaining bits represents magnitude .

2. signed 1’s complement representation: In this representation the most significant bit indicates the sign, if it is 0 that represents +ve number & if it is 1 that represents –ve number and the magnitude represents in1’s complement form.

1. signed 2’s complement representation: In this representation the most significant bit indicates the sign, if it is 0 that represents +ve number & if it is 1 that represents –ve number and the magnitude represents in2’s complement form.

QUESTION

1. Obtain the 1,s complement and 2,s complement of the following binary numbersi) 101010001 ii) 00001001 iii) 1000111110

2. Obtain the 9,s complement and 10,s complement of the following numbers3. i) 13579 ii) 90090 iii) 000004. Find the 10,s complement of 9355. Perform the subtraction with the following decimal numbers using (1) 10,s complement

And (2) 9,s complement. a)5250-321 b)753-864 c)3570-2100Convert the following to binary and then to gray code.

6. (a) (1111)16 (b) (BC54)16 (c) (237)8 (d) (164)10 (e) (323)87. Subtraction by using 10’s complement for the given 3456 - 245.8. Subtraction by using 2’s complement for the given 111001-1010.

3. BINARY CODES

Binary codes

In the coding, when numbers, letters or words are represented by a specific group of symbols, it is said that the number, letter or word is being encoded. The group of symbols is called as a code. The digital data is represented, stored and transmitted as group of binary bits. This group is also called as binary code. The binary code is represented by the number as well as alphanumeric letter.

Advantages of Binary Code

Following is the list of advantages that binary code offers.

Binary codes are suitable for the computer applications.

Binary codes are suitable for the digital communications.

Binary codes make the analysis and designing of digital circuits if we use the binary codes.

Since only 0 & 1 are being used, implementation becomes easy.

Classification of binary codes

The codes are broadly categorized into following four categories.

Weighted Codes Non-Weighted Codes Binary Coded Decimal Code Alphanumeric Codes Error Detecting Codes Error Correcting Codes

Weighted CodesWeighted binary codes are those binary codes which obey the positional weight principle. Each

position of the number represents a specific weight. Several systems of the codes are used to express the decimal digits 0 through 9. In these codes each decimal digit is represented by a group of four bits.

Non-Weighted Codes

In this type of binary codes, the positional weights are not assigned. The examples of non-weighted codes are Excess-3 code and Gray code.

Excess-3 code

The Excess-3 code is also called as XS-3 code. It is non-weighted code used to express decimal numbers. The Excess-3 code words are derived from the 8421 BCD code words adding (0011)2 or (3)10 to each code word in 8421. The excess-3 codes are obtained as follows −

Example

Excess-3 Addition:Add the xs-3 no.s by adding the 4 bit groups in each column starting from the LSD. If

there is no carry starting from the addition of any of the 4-bit groups , subtract 0011 from the sum term of those groups ( because when 2 decimal digits are added in xs-3 & there is no carry , result in xs-6). If there is a carry out, add 0011 to the sum term of those groups( because when there is a carry, the invalid states are skipped and the result is normal binary).

Excess -3 (XS-3) Subtraction:

Subtract the xs-3 no.s by subtracting each 4 bit group of the subtrahend from the

corresponding 4 bit group of the minuend starting form the LSD .if there is no borrow from the next 4-bit group add 0011 to the difference term of such groups (because when decimal digits are subtracted in xs-3 & there is no borrow , result is normal binary). I f there is a borrow , subtract 0011 from the differenceterm(b coz taking a borrow is equivalent to adding six invalid states , result is in xs-6)

Gray Code

It is the non-weighted code and it is not arithmetic codes. That means there are no specific weights assigned to the bit position. It has a very special feature that, only one bit will change each time the decimal number is incremented as shown in fig. As only one bit changes at a time, the gray code is called as a unit distance code. The gray code is a cyclic code. Gray code cannot be used for arithmetic operation.

Application of Gray code Gray code is popularly used in the shaft position encoders.

A shaft position encoder produces a code word which represents the angular position of the shaft.

Binary to Gray conversion:

N bit binary no is rep by Bn Bn-1 ------- B1 Gray code equivalent is by Gn

Gn-1 ------- G1

Bn,, Gn are the MSB‘s then the gray code bits are obtaind from the binary code as

Gn=Bn Gn-1=Bn Bn-1

Gn-2=Bn- 1 Bn-

----------- G1=B2 B1

ĺEX-or symbol

Procedure: ex-or the bits of the binary no with those of the binary no shifted one position to the right . The LSB of the shifted no. is discarded & the MSB of the gray code no.is the same as the MSB of the original binaryno.Gray to Binary Conversion:

If an n bit gray no. is rep by Gn Gn-1 ------- G1its binary equivalent by Bn Bn-1 ------- B1 then the binary bits are obtained from gray bits as

Bn= Gn Bn-1=Bn Gn-1 Bn-2= Gn-2 ----------- B1 G1

=B2

To convert no. in any system into given no. first convert it into binary & then binary to gray. To convert gray no into binary no & convert binary no into require no system.

Ex: 10110010(gray) = 110111002= DC16=3348=22010 EX:1101

Gray: 1 1 0 1

Binary:1 0 0 1

Binary Coded Decimal (BCD) codeIn this code each decimal digit is represented by a 4-bit binary number. BCD is a way to express

each of the decimal digits with a binary code. In the BCD, with four bits we can represent sixteen numbers (0000 to 1111). But in BCD code only first ten of these are used (0000 to 1001). The remaining six code combinations i.e. 1010 to 1111 are invalid in BCD.

Advantages of BCD Codes

It is very similar to decimal system.

We need to remember binary equivalent of decimal numbers 0 to 9 only.

Disadvantages of BCD Codes

The addition and subtraction of BCD have different rules.

The BCD arithmetic is little more complicated.

BCD needs more number of bits than binary to represent the decimal number. So BCD is less efficient than binary.

8421 BCD code (Natural BCD code):

Each decimal digit 0 through 9 is coded by a 4 bit binary no. called natural binary codes. Because of the 8,4,2,1 weights attached to it. It is a weighted code & also sequential . it is useful for mathematical operations. The advantage of this code is its case of conversion to & from decimal. It is less efficient than the pure binary, it require more bits.Ex: 14ĺ1110 in binary But as 0001 0100 in 8421 ode.The disadvantage of the BCD code is that, arithmetic operations are more complex than they are in pure binary. There are 6 illegal combinations 1010, 1011, 1100,1101,1110,1111 in these codes; they are not part of the 8421 BCD code system. The disadvantage of 8421 code is, the rules of binary addition 8421 no, but only to the individual 4 bit groups.

BCD Addition:

It is individually adding the corresponding digits of the decimal no,s expressed in 4 bit binary groups starting from the LSD . If there is no carry & the sum term is not an illegal code , no correction is needed .If there is a carry out of one group to the next group or if the sum term is an illegal code then 610(0100) is added to the sum term of that group & the resulting carry is added to the next group.

Ex: Perform decimal additions in 8421 code (a)25+13

In BCD 25= 0010 0101In BCD +13 =+0001 0011

38 0011 1000No carry , no illegal code .This is the corrected sum (b). 679.6 + 536.8

679.6 = 0110 0111 1001 .0110 in BCD+536.8 = +0101 0011 0010 .1000 in BCD _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

1216.4 1011 1010 0110 . 1110 illegal codes+0110 + 0011 +0110 . + 0110 add 0110 to each

(1)0001 (1)0000 (1)0101 . (1)0100 propagate carry/

+1/

+1/

+1/

+1

0001 0010 0001 0110 . 0100

1 2 1 6 . 4

BCD Subtraction:Performed by subtracting the digits of each 4 bit group of the subtrahend the digits

from the corresponding 4- bit group of the minuend in binary starting from the LSD . if there is no borrow from the next group , then 610(0110)is subtracted from the difference term of this group.

(a)38-15

In BCD 38= 0011 1000In BCD -15 = -0001 0101

23 0010 0011No borrow, so correct difference.

Alphanumeric codes

A binary digit or bit can represent only two symbols as it has only two states '0' or '1'. But this is not enough for communication between two computers because there we need many more symbols for communication. These symbols are required to represent 26 alphabets with capital and small letters, numbers from 0 to 9, punctuation marks and other symbols.

The alphanumeric codes are the codes that represent numbers and alphabetic characters. Mostly such codes also represent other characters such as symbol and various instructions necessary for conveying information. An alphanumeric code should at least represent 10 digits and 26 letters of alphabet i.e. total 36 items. The following three alphanumeric codes are very commonly used for the data representation.

American Standard Code for Information Interchange (ASCII). Extended Binary Coded Decimal Interchange Code (EBCDIC). Five bit Bardot Code.ASCII code is a 7-bit code whereas EBCDIC is an 8-bit code. ASCII code is more commonly used worldwide while EBCDIC is used primarily in large IBM computers.

Error Codes

There are binary code techniques available to detect and correct data during data transmission.

ERROR DETECTING CODES:

When binary data is transmitted & processed, it is susceptible to noise that can alter or distort its contents. The 1‘s may get changed to 0‘s & 1‘s .because digital systems must be accurate to the digit, error can pose a problem. Several schemes have been devised to detect the occurrence of a single bit error in a binary word, so that whenever such an error occurs the concerned binary word can be corrected & retransmitted.

Parity: The simplest techniques for detecting errors is that of adding an extra bit known as parity bit to each word being transmitted. Two types of parity: Odd parity, even parity for odd parity, the parity bit is set to a ‗0‘or a ‗1‘a t the transmitter such that the total no. of 1 bit in the word including the parity bit is an odd no.For even parity, the parity bit is set to a ‗0‘or a ‗1‘at the transmitter such that the parity bit is an even no.

Decimal 8421 code Odd parity Even parity0 0000 1 01 0001 0 12 0010 0 13 0011 1 04 0100 0 15 0100 1 06 0110 1 07 0111 0 18 1000 0 19 1001 1 0

When the digit data is received . a parity checking circuit generates an error signal if the total no of 1‘s is even in an odd parity system or odd in an even parity system. This parity check can always detect a single bit error but cannot detect 2 or more errors with in the same word.Odd parity is used more often than even parity does not detect the situation. Where all 0‘s are created by a short ckt or some other fault condition.

Ex: Even parity scheme(a) 10101010 ( b) 11110110 (c) 10111001

Ans:(a) No. of 1‘s in the word is even is 4 so there is no error(b) No. of 1‘s in the word is even is 6 so there is no error(c) No. of 1‘s in the word is odd is 5 so there is error

Ex: odd parity(a)10110111 (b) 10011010 (c)11101010

Ans:(a) No. of 1‘s in the word is even is 6 so word has error(b) No. of 1‘s in the word is even is 4 so word has error(c) No. of 1‘s in the word is odd is 5 so there is no error

BOOLEAN ALGEBRA & LOGIC GATES

5.BASIC DEFINITIONS, AXIOMATIC DEFINITION OF BOOLEAN ALGEBRA, BASIC PROPERTIES OF BOOLEAN ALGEBRA

Boolean Algebra is used to analyze and simplify the digital (logic) circuits. It uses only the binary numbers i.e. 0 and 1. It is also called as Binary Algebra or logical Algebra. Boolean algebra was invented by George Boole in 1854.

Rule in Boolean Algebra Following are the important rules used in Boolean algebra.

Variable used can have only two values. Binary 1 for HIGH and Binary 0 for LOW.

Complement of a variable is represented by an overbar (-). Thus, complement of variable B is represented as . Thus if B = 0 then = 1 and B = 1 then = 0.

ORing of the variables is represented by a plus (+) sign between them. For example ORing of A, B, C is represented as A + B + C.

Logical ANDing of the two or more variable is represented by writing a dot between them such as A.B.C. Sometime the dot may be omitted like ABC.

Boolean Laws There are six types of Boolean Laws.

Commutative law Any binary operation which satisfies the following expression is referred to as commutative operation.

Commutative law states that changing the sequence of the variables does not have any effect on the output of a logic circuit.

Associative law This law states that the order in which the logic operations are performed is irrelevant as their effect is the same.

Distributive lawDistributive law states the following condition.

AND lawThese laws use the AND operation. Therefore they are called as AND laws.

OR law These laws use the OR operation. Therefore they are called as OR laws.

INVERSION lawThis law uses the NOT operation. The inversion law states that double inversion of a

variable results in the original variable itself.

AXIOMS Definition of Boolean Algebra:

Axioms or Postulates are a set of logical expressions i.e, without proof. & also we can build a set of useful theorems. Each axiom can be interpreted as the outcome of an operation performed by a logic gate.

AND OR NOT0.0=0 0+0=0 1=00.1=0 0+1=1 0=11.0=0 1+0=11.1=1 1+1=1

Complementation Laws:

Law3:If A=0 then =1 Law4:If A=1 then =0Law5: =A(double complementation law) AND laws:Law 1: A.0=0(Null law) Law 2:A.1=A(Identity law) Law 3:A.A=ALaw 4:A. =0 OR laws:Law 1: A+0=A(Null law) Law 2:A+1=1Law 3:A+A=A Law 4:A+ =0

Commutative laws:

allow change in position of AND or OR variables.

2 commutative laws Law 1: A+B=B+A Law 2: A.B=B.A

Associative laws:

This allows grouping of variables. It has 2 laws.

Law 1: (A+B)+C=A+(B+C) =A OR B ORed with C

This law can be extended to any no. of variables (A+B+C)+D=(A+B+C)+D=(A+B)+(C+D)

=

A B A+B = B A B+A0 0 0 0 0 00 1 1 0 1 11 0 1 1 0 11 1 1 1 1 1

A.B B.A0 00 00 01 1

A B C A+B (A+B)+C0 0 0 0 00 0 1 0 10 1 0 1 10 1 1 1 11 0 0 1 11 0 1 1 11 1 0 1 11 1 1 1 1

A B C B+C A+(B+C)0 0 0 0 00 0 1 1 10 1 0 1 10 1 1 1 11 0 0 0 11 0 1 1 11 1 0 1 11 1 1 1 1

Law2: (A.B).C=A(B.C)

This law can be extended to any no. of variables (A.B.C).D=(A.B.C).D

=

Distributive Laws:This has 2 lawsLaw 1. A(B+C)=AB+AC

This law applies to single variables. EX:ABC(D+E)=ABCD+ABCE AB(CD+EF)=ABCD+ABEF

=

Law 2 .A+BC=(A+B)(A+C)RHF=(A+B)(A+C)

=AA+AC+BA+BC=A+AC+AB+BC=A(1+C+B)+BC=A.1+BC=A+BC LHF

A B C BC A(BC)0 0 0 0 00 0 1 0 00 1 0 0 00 1 1 1 01 0 0 0 01 0 1 0 01 1 0 0 01 1 1 1 1

A B C AB (AB)C0 0 0 0 00 0 1 0 00 1 0 0 00 1 1 0 01 0 0 0 01 0 1 0 01 1 0 1 01 1 1 1 1

A B C B+C A(B+C)0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 1 01 0 0 0 01 0 1 1 11 1 0 1 11 1 1 1 1

A B C AB AC AB+AC0 0 0 0 0 00 0 1 0 0 00 1 0 0 0 00 1 1 0 0 01 0 0 0 0 01 0 1 0 1 11 1 0 1 0 11 1 1 1 1 1

Properties of Boolean algebra:

 Commutative

Associative

Distributive

 Identity

Complement

DeMorgans Theorem:

This law states that the compliment of a sum of variables is equal to the productof their individual complements

A B C BC A+BC0 0 0 0 00 0 1 0 00 1 0 0 00 1 1 1 11 0 0 0 11 0 1 0 11 1 0 0 11 1 1 1 1

A B C A+B A+C (A+B)(A+C)0 0 0 0 0 0=0

0 1 1 1 00 1 0 1 0 00 1 1 1 1 01 0 0 0 1 01 0 1 1 1 11 1 0 1 1 11 1 1 1 1 1

LHS

RHS

NOR gate Bubbled AND gate

NOR gate= Bubbled AND gate

This can be extended to any variables. (A+B+C+D+)‘=A‘B‘C‘D‘---- Law 2: (AB)‘=A‘+B‘

Complement of the product of variables is equal to the sum of their individual components.

This law also can extend to any no. Of variables. (ABCD---)‘=A‘+B‘+C‘+D‘+------It can be extended to complicated expressions by

1. Complement the entire function2. Change all the ANDs to ORS and all the Ors to ANDS3. Complement each of the individual variables.

A

B A+B (A+B)‘0 0 0 1

0 1 1 01 0 1 01 1 1 0

A B A‘ B‘ A‘B‘

0 0 1 1 1

0 1 1 0 0

1 0 0 1 0

1 1 0 0 0

A

B (AB)‘0 0 1

0 1 11 0 11 1 0

A B A‘ B‘ A‘+B‘

0 0 1 1 1

0 1 1 0 1

1 0 0 1 1

1 1 0 0 0

4. Change all 0s to 1s and 1s to 0s.This procedure is called demorganization or complementation of switching expressions.

QUESTIONS:

1. State Duality theorem. List Boolean laws and their Duals.2. Simplify the following Bo Simplify the following Boolean expressions to minimum no.

of literals.i. ABC+A’B+ABC’ii. (BC’+A’D)(AB’+CD’)iii. x’yz+xziv. xy+x(wz+wz’

3. Obtain the Dual of the following Boolean expressions.i. AB+A(B+C)+B’(B+D)

ii. A+B+A‘B’Ciii. A’B+A’BC’+A’BCD+A’BC’D’Eiv. ABEF+ABE’F’+A’B’EF

4. Boolean functions to minimum number of literals:i. F = ABC + ABC’ + A’Bii. F = (A+B)’ (A’+B’)

5. Simplify the following Boolean expression: (i) F = (A+B)(A’+C)(B+C).(ii) F = A+B+C’+D(E+F)

6. Obtain the truth table of the following Boolean function and express the function as sum of minterms and product of maxterms F = (A+B) (B+C).

7. Simplify the following Boolean functions to minimum number of literals.i. (i)xyz + x’y + xyz’.a. (ii)xz + x’yz.

8.Reduce A'B'C' + A'BC' + A'BC

9. Simplify the following expression Y = (A + B) (A + C’) (B' + C’)

10.Define duality property

11.Find the complement of the functions F1 = x'yz' + x'y'z and F2 = x (y'z' +

i. yz).By applying De-Morgan's theorem.

12.State and prove De-Morgan’s theorem

5.BOOLEAN FUNCTIONS, CANONICAL AND STANDARD FORMS

Boolean functions & their representation:

A function of n Boolean variables denoted by f(x1,x2,x3------xn) is another variable denoted by & takes one of the two possible values 0 & 1.The various way of represent a given function is1. Sum of Product(SOP) form:It is called the Disjunctive Normal Form(DNF) Ex: f(A,B,C)=(A B+B C)2. Product of Sums (POS) form:

It is called the Conjunctive Normal Form(CNF).This is implemented using Consensus theorem.

Ex: f(A,B,C)=( A+ B)(B+C)3. Truth Table form:The function is specified by listing all possible combinations of values assumed by the

variables & the corresponding values of the function.Truth table for f(A,B,C)=(A B+B C)

4. Standard Sum of Products form: Called Disjunctive Canonical form (DCF) & also called Expanded SOP form or Canonical SOP form.

f(A,B,C)=( AB+B C)= AB(C+C’ )+ BC(A+A’ )= ABC+ ABC’ + ABC+A’B C. A Product term contains all the variables of the function either in complemented or

uncomplemented form is called a minterm. A minterm assumes the value 1 only for one combination of the variables. An n variable function can have in all 2n minterms to 1 is the standard sum of products form of the function. Min terms are denoted as m0, m1,m2--

5. Standard Product of Sums form: It is called as Conjunctive Canonical form (CCF). It is also called Expanded POS or Canonical POS.

If A=0 B=0 C=0, term=0Thus function f (A, B, C) =( A+B )(B+C) given by POS f(A,B,C)=( A+B +CC’ )(AA’+B+C )=( A+B +C ) (A +B +C’ )(A+B+C)(A’+B+ C).

A sum term which contains each of the n variables in either complemented form is called a Maxterm. A maxterm assumes the value ‗0‘ only for one combination of the variables. The most there are 2n maxterms. It is represented as M0,M1,M2-----. Here the suffixes are decimal codes.

The CCF of f(A,B,C)=M0.M4.M6.M7f(A,B,C)=πM(0,4,6,7)

Conversion between Canonical form:

The complement of a function expressed as the sum of minterms equals the sum of minterms missing from the original function is expressed by those minterms that make the function equal to 1 for those minterms that make the function equal to 0.Ex: f(A,B,C)=πm(0,2,4,6,7)Complement is Σm(1,3,5).=m1+m3+m5complement of by deMorgans theoremf= ( m 1 + m 3 + m 5 ) = m1.m2 .m5 =M1 M3 M5=πM(1,3,5)Mj , the maxterm with subscript j is a complement of the minterm with the same subscript j and vice versa. To convert one canonical form to another, interchange the symbol Σ and π, and list those numbers missing from the original form.

Boolean Expression & Logic Diagrams:

Boolean expressions can be realized as hardware using logic gates. Conversely, hardware can be translated into Boolean expressions for the analysis of existing circuits.

1. Converting Boolean Expressions to Logic:

To convert, start with the output & work towards the input.

Assume the expression (AB)’+A+(B +C)’ is to be realized using AOI logic. Start with this expression. Since it is three terms, it must be the output of a three-input OR gates. So, draw an OR gate with three inputs as

(AB)‘ is the output of an inverter whose inputs is AB and (B+C)‘ must be the output of an inverter whose input is B+C. so, those two inverters are as

Now AB must be output of a two-input AND gate whose inputs are A and B . And B+C must be the output of a two-input OR gate whose inputs are B and C. so, an AND gate and an OR gate are as

2. Converting Logic to Boolean Expressions:

To convert logic to algebra, start with the input signals and develop the terms of the Boolean expression until the output is reached.

Converting AND/OR/INVERT logic to NAND/NOR logic:

The SOP expression ABC+AB‘+A‘BC can be implemented in AND/ OR logic as

The POS expression (A+B+C)(A+B‘)(A‘+B+C) can be implemented using OR andAND gatesThe expression ABC‘+A‘B[=B(A‘+AC‘) can be implemented in hybrid form as

Hybrid Logic reduces the no. of gate inputs required for realization (from 7 to 6 in this case), but results in multilevel logic. Different inputs pass through number of gates to reach the output. It leads to non-uniform propagation delay between different numbers of gates to give rise to logic race. The SOP and POS realizations give rise two-level logic. The two-level logic provides uniform time delay between input and outputs, because each input signal has to pass through two gates to reach the output. So, it does not suffer from the problem of logic race.

Since NAND logic and MOR logic are universal logic circuits which are first computed and converted to AOI logic may be converted to either NAND logic or NOR logic depending on the choice. The procedure is

1. Draw the circuit in AOI logic2. If NAND hardware is chosen, add a circle at the output of each AND gate and at the inputs to all the AND gates.3. If NOR hardware is chosen, add a circle at the output of each OR gate and at the inputs to all the AND gates4. Add or subtract an inverter on each line that received a circle in steps 2 or 3 so that the polarity of signals on those lines remains unchanged from that of the original diagram5. Replace bubbled OR by NAND and bubbled AND by NOR6. Eliminate double inversions.

QUESTIONS:1. Given the Boolean functions F=xy+xy,+y,z

A) implement it with AND OR, and NOT gates

B) implement it with only OR, and NOT gates

C) implement it with only AND and NOT gates

2. convert the following to the other canonical form

F(x,y,z)=summation(1,3,7)

3. Obtain the truth table of the function F= xy+xy,+y,z

4. Convert the given expression in canonical SOP form Y = AC + AB + BC.

5. Convert the given equation Y=AB+AC’+BC into standard SOP form

6. LOGIC GATES, OTHER LOGIC OPERATIONS, INTEGRATED

CIRCUITS

LOGIC GATES Logic gates are the basic building blocks of any digital system. It is an electronic

circuit having one or more than one input and only one output. The relationship between the input and the output is based on certain logic. Based on this, logic gates are named as AND gate, OR gate, NOT gate etc.

AND GateA circuit which performs an AND operation is shown in figure. It has n input (n >= 2) and one output.

Logic diagram

Truth Table

OR GateA circuit which performs an OR operation is shown in figure. It has n input (n >= 2) and one output.

Logic diagram

Truth Table

NOT GateNOT gate is also known as Inverter. It has one input A and one output Y.

Logic diagram

Truth Table

NAND GateA NOT-AND operation is known as NAND operation. It has n input (n >= 2) and one output.

Logic diagram

Truth Table

NOR Gate

A NOT-OR operation is known as NOR operation. It has n input (n >= 2) and one output.

Logic diagram

Truth Table

XOR GateXOR or Ex-OR gate is a special type of gate. It can be used in the half adder, full adder and subtractor. The exclusive-OR gate is abbreviated as EX-OR gate or sometime as X-OR gate. It has n input (n >= 2) and one output.

Logic diagram

Truth Table

XNOR GateXNOR gate is a special type of gate. It can be used in the half adder, full adder and subtractor. The exclusive-NOR gate is abbreviated as EX-NOR gate or sometime as X-NOR gate. It has n input (n >= 2) and one output.

Logic diagram

Truth Table

Other Logic Operations

Integrated circuits

An integrated circuit is one in which circuit components such as transistors, diodes,resistors, capacitors etc. are automatically part of a small semiconductor chip.

An integrated circuit consists of a number of circuit components (e.g. transistors, diodes, resistors etc.) and their inter connections in a single small package to per- form a complete electronic function. These components are formed and connected within a small chip of semi- conductor material. The following points are worth not- ing about integrated circuits :

Advantages : Integrated circuits possess the following advantages over discrete circuits : Increased reliability due to lesser num- ber of connections. Extremely small size due to the fabrica- tion of various circuit elements

Lesser weight and space requirement due to miniaturized circuit. Low power requirements. Greater ability to operate at extreme values of temperature. Low cost because of simultaneous production of hundreds of alike circuits on a small semi- conductor wafer.The circuit lay out is greatly simplified because integrated circuits are constrained to use minimum number of external connections.Disadvantages : The disadvantages of integrated circuits are :

(i) If any component in an IC goes out of order, the whole IC has to be replaced by the new one.(ii) In an IC, it is neither convenient nor economical to fabricate capacitances exceeding 30 pF. Therefore, for high values of capacitance, discrete components exterior to IC chip are connected.(iii) It is not possible to fabricate inductors and transformers on the surface of semi- conductor chip. Therefore, these components are connected exterior to the semi- conductor chip.(iv) It is not possible to produce high power ICs (greater than 10 W).(v) There is a lack of flexibility in an IC i.e., it is generally not possible to modify the parameters within which an integrated circuit will operate.

QUESTIONS:

1. Draw the logic symbols and truth table of NAND and NOR gates2. What do you understand by universal gate3. What is a Logic gate?4. Draw the logic symbols of EX-NOR and EX-OR gates and its truth table.5. Explain about integrated circuit .

6. Discuss about other logic gates.

UNIT II

GATE LEVEL MINIMIZATION

1.THE MAP METHOD, FOUR VARIABLE K-MAP, FIVE-VARIABLE K-MAP

Introduction to Karnaugh Maps

1. The Karnaugh map (or K-map) is a visual way of detecting redundancy in theSOP.

2. The K-map can be easily used for circuits with 2, 3, or 4 inputs.

3. It consists of an array of cells, each representing a possible combination of inputs.

4. The cells are arranged to that each cell’s input combination differs from adjacent cells by only a single bit.

5. This is called Gray code ordering – it ensures that physical neighbors are the array and are logical neighbors as well. (In other words, neighboring bit patterns are nearly the same, differing by only 1 bit).

Consider the following arrangements of cells:

2-input 3-input

a’@ b’ a’@ b a’@ b’@ c’ a’@ b’@ c a’@ b @ c a’@ b @ c’

00 01 000 001 011 010

a @ b’ a @ b a @ b’@ c’ a @ b’@ c a @ b @ c a @ b @ c’

10 11 100 101 111 110

4-input

a’@b’@c’@d’ a’@b’@c’@d a’@b’@c@d a’@b’@c@d’

0000 0001 0011 0010

a’@b@c’@d’ a’@b@c’@d a’@b@c@d a’@b@c@d’

0100 0101 0111 0110

a@b@c’@d’ a@b@c’@d a@b@c@d a@b@c@d’

1100 1101 1111 1110

a@b’@c’@d’ a@b’@c’@d a@b’@c@d a@b’@c@d’

1000 1001 1011 1010

The cells are arranged as above, but we write them empty, like this:

Note that the numbers are not in binary order, but are arranged so that only a single bit changes between neighbors.This one-bit change applies at the edges, too. So cells in the same row on the left and right edges of the array also only differ by one bit.

Note: The value of a particular cell is found by combining the numbers at the edges of the row and column.

Also, in general, it is easier to order the inputs to a K-map so that they can be read like a binary number. (Show example.)

So, we have this grid. What do we do with it?

• We put 1's in all the cells that represent minterms in the SOP . (In other words, we find the 1's in the truth table output, and put 1's in the cells corresponding to the same inputs.)

If there are two neighboring 1's in the grid, it means that the input bit change between the two cells has no effect on the output, and thus there is redundancy. This leads to a basic strategy.

Basic Strategy:

Group adjacent 1's together in square or rectangular groups of 2, 4, 8, or 16, such that the total number of groups and isolated 1's is minimized, while using as large groups as possible. Groups may overlap, so that a particular cell may be included in more than one group.

(Recall that adjacency wrap s around edges of grid.)

Applying this to the multiplexer example:

Rules for K-Maps

1. Each cell with a 1 must be included in at least one group.

2. Try to form the largest possible groups.

3. Try to end up with as few groups as possible.

4. Groups may be in sizes that are powers of 2: 2 0 = 1, 21 = 2, 22 = 4, 23 = 8, 24 = 16, ...

5. Groups may be square or rectangular only (including wrap-around at the grid edges). No diagonals or zig-zags can be used to form a group.

6. The larger a group is, the more redundant inputs there are:

i. A group of 1 has no redundant inputs.

ii. A group of 2 has 1 redundant input.

iii. A group of 4 has 2 redundant inputs.

iv. A group of 8 has 3 redundant inputs.

v. A group of 16 has 4 redundant inputs.

The following simple examples illustrate rule 6 above.

2-input Example

A B Y

0 0 1

10 1

01 1

11 0

3.Direct from truth table: Y = A’B’ + A’B + AB-input Example

A B C Y

0 0 0 0

0 10 0

1 00 1

1 10 1

0 01 1

0 11 0

1 01 1

1 11 1

Direct from truth table: Y = A’BC’ + A’BC + AB’C’ + ABC’ + ABC

Five variable k-map:

Five variable k-map can have 25 =32 possible combinations of input variable as

A’B’C’D’E’, A’B’C’D’E,--------ABCDE with minterms m0, m1-----m31 respectively in SOP &

A’+B’+C’+D’+E’, A’+B’+C’+D’+E,---------- A+B +C +D +E with maxterms M0,M1, -----------

M31 respectively in POS form. It has 25=32 squares or cells of the k-map are divided into 2

blocks of 16 squares each. The left block represents minterms from m0 to m15 in which A is a 0,

and the right block represents minterms from m16 to m31 in which A is 1.The 5-variable k-map

may contain 2-squares, 4-squares , 8-squares , 16-squares or 32-squares involving these two

blocks. Squares are also considered adjacent in these two blocks, if when superimposing one

block on top of another, the squares coincide with one another.

Grouping s is

Ex: F=Σm(0,1,4,5,6,13,14,15,22,24,25,28,29,30,31) is SOPPOS is F=πM(2,3,7,8,9,10,11,12,16,17,18,19,20,21,23,26,27)

The real minimal expression is the minimal of the SOP and POS forms.The reduction is done as1. There is no isolated 1s2. M12 can go only with m13. Form a 2-square which is read as A‘BCD‘

3. M0 can go with m2,m16 and m18 . so form a 4-square which is read as B‘C‘E‘

4. M20,m21,m17 and m16 form a 4-square which is read as AB‘D‘

5. M2,m3,m18,m19,m10,m11,m26 and m27 form an 8-square which is read as C‘d

6. Write all the product terms in SOP form. So the minimal expression is

Fmin= A‘BCD‘+B‘C‘E‘+AB‘D‘+C‘D(16 inputs)

Product of sum simplification

In the POS k-map ,the reduction is done as:1. There are no isolated 0s

3.4.M85. M286. M307. Sum terms in POS form. So the minimal expression in POS is Fmin= A‘BcD‘+B‘C‘E‘+AB‘D‘+C‘D

Don’t care combinations: For certain input combinations, the value of the output is unspecified either because the input

combinations are invalid or because the precise value of the output is of no consequence. The

combinations for which the value of experiments are not specified are called don‘t care

combinations are invalid or because the precise value of the output is of no consequence. The

combinations for which the value of expressions is not specified are called don‘t care

combinations or Optional Combinations, such expressions stand incompletely specified. The

output is a don‘t care for these invalid combinations.

Ex:In XS-3 code system, the binary states 0000, 0001, 0010,1101,1110,1111 are unspecified. &

never occur called don‘t cares.

A standard SOP expression with don‘t cares can be converted into a standard POS form by

keeping the don‘t cares as they are & writing the missing minterms of the SOP form as the

maxterms of the POS form vice versa.

Don‘t cares denoted by ‗X‘ or ‗φ‘

Ex: f=Σm(1,5,6,12,13,14)+d(2,4)

Or f=π M(0,3,7,9,10,11,15).πd(2,4)

SOP minimal form fmin= BC’+B’D +A’C’D

POS minimal form fmin=(B+D)(A’ +B)(C’ +D’)

Questions

1. What is a karnaugh map? State the limitations of karnaugh map.

2. Minimize the following Boolean function using k-map and realize using NAND Gates

F(A, B, C, D)= Σm(0, 2, 4, 6, 8, 10, 12, 14).

3. Minimize the following Boolean function using k-map and realize F(A, B, C, D)= Σm(0,

2, 7,6, 8, 11, 15, 14).

4. Minimize the following Boolean function using k-map and realize using NAND Gates

(A, B, C, D,E)= Σm(0, 2, 4, 6, 9,11,13,15,17,21,25,27,29,31).

5. Minimize the following Boolean function using k-map and realize using NAND Gates

F(A, B, C)= Σm(0, 2, 4, 6, 1,5,3)

2.Nand and Nor Implementation

The implementation of a logic expression such that each one of the inputs has to pass through only two gates to reach the output is called Two-level implementation. Both SOP , POS forms result in two-level logic Two level implementation can be with AND, OR gates or only NAND or with only NOR gates Boolean expression with only NAND gates requires that the function be in SOP form.Function F= AB+CD(A) AND-OR logic(B) NAND-NAND logic F=AB+CD= AB+CD =AB .CD

AND-OR Logic NAND LogicTwo –level implementation using AND-OR and NAND logic The implementation of the form:F=XY‘+X‘Y+Z using AND-OR logic and NAND- NAND logic is

Two –level implementation using AND-OR and NAND logic

The implementation of Boolean expressions with only NOR gates requires that the function be in the form of POS form.Implementation of the function (A+B)(C‘+D‘)

Two –level implementation using OR-AND and NOR logic

Two –level implementation using OR-AND and NOR logic

TWO LEVEL IMPLEMENTATION, EX-OR FUNCTION

Two level implementation:

The types of gates most often found in IC‘s are NAND and NORSome NAND or NOR gates allow the possibility of wire connection between the outputs of two gates to provide a specific logic function called Wired Logic.The logic function implemented by the circuit

Is calledan AND-OR Invert function.

Similarly NOR outputs of ECL gates can be tied together to form Wired NOR function. The logic function implemented by this circuit is

Is called OR-AND INVERT Function.EX: Open Collector TTL NAND gates, when tied together perform the wired AND logic is called AOI=( AB) .(CD )=AB +CDSimilarly NOR outputs of ECL can tied together to perform a wired NOR function. F=(A +B )+(C + D) =[(A +B ) ( C+D ) ]Non Degenerate forms:Considering 4 types of gates AND, OR, NAND , NOR & assign one type of gate for the first level & one type of gate for the second level. Find 16 possible combinations of two level form. Eight of these are degenerate forms. Because they generate to a single operation. i.e, AND gate in first level & AND gate in second The output is nearly the AND function of all input variables.

The other non degenerate forms produce an implementation in SOP or POS are AND-OR OR-ANDNAND-NAND NOR-NORNOR-OR NAND-NANDOR-NAND AND-NORThe two forms are dual of each other.AND-OR & OR-AND forms are the basic two-level forms. NAND-NAND, NOR_NORAOI Implementation:The two forms Nandi-And and And-Nor perform AOI function.Inversion isand-Nor form resembles the and-Or form done by the bubble in the output of the NOR gate.Its function is F= AB+CD +E

Two-level implementation in AND-NOR and NAND-AND formOAI Implementation:The twoforms OR-NAND and NOR-NOR perform OAI function.OR-NAND form OR-AND form except inversion done by bubble in NAND gate. Function F=[(A +B ) ( C+ D) E]

Summary:

The Exclusive OR (X-OR) gate:It has 2 inputs& only 1 output. It assumes output as 1 when input is not equal called anti-

coincidence gate or inequality detector.

0

Logic Symbol

Proof: Truth Table

The high outputs are generated only when odd number of high inputs is present. This is why x-or function also known as odd function.

The X-OR gate using AND-OR-NOT gates:

X-OR gate as an Inverter:By connecting one of two input terminals to logic 1 & feeding the sequence to be

inverted to other terminal

A B0 0 00 1 11 0 11 1 0

Logic Symbol TTL IC 746 has 4 x-OR gateCMOS IC 74C8C has 4 X-OR gates.X-OR gate using NAND gates only:

X-OR gate using NOR gates only:

QUESTIONS

1. What is two level logic? State its advantages and disadvantages?

2. Implement OR gate using only two input NAND gates

3. Implement the following Boolean equation using only NAND gates Y=AB+CDE+F 3.

4. Simplify the following Boolean expressions using K-map and implement them using

NAND gates F(W,X,Y,Z)= XZ+W’XY’+WXY+W’YZ+WY’Z

5. Implement the following Boolean function using NOR gates

Y=(AB’+A’B)(C+D’ )

4 .QUINE-MCCLUSKEY METHOD OR TABULAR MINIMIZATION METHOD

Quine- Mccluskey Method:

It also known as Tabular method. It is more systematic method of minimizing expressions of even larger number of variables. It is suitable for hand computation as well as computation by machines i.e., programmable. . The procedure is based on repeated application of the combining theorem.PA+P =P (P is set of literals) on all adjacent pairs of terms, yields the set of all PI‘s from which a minimal sum may be selected.Consider expressionΣm(0,1,4,5)= A’B’C’+A’B’ C+AB’C’ +AB’CFirst, second terms & third, fourth terms can be combinedA’B( C+C’ )+ AB(C+C’ )= A’B +ABReduced toB( A’+A )=BThe same result can be obtained by combining m0& m4 & m1&m5 in first step & resulting terms in the second step .Procedure: Decimal Representation Don‘t cares PI chart EPI Dominating Rows & Columns Determination of Minimal expressions in comples cases. Branching Method:

EX:

QUESTIONS1. Simplify the Boolean function by using tabulation method

F(a,b,c,d)=Σm(0,1,2,5,6,7,8,9,10,14)

2. Simplify the following Boolean function using Tabulation method

Y(A,B,C,D) = Σ(1,3,5,8,9,11,15)

UNIT III

COMBINATIONAL LOGIC CIRCUITS:

Combinational circuit is a circuit in which we combine the different gates in the circuit, for example encoder, decoder, multiplexer and demultiplexer. Some of the characteristics of combinational circuits are following −

The output of combinational circuit at any instant of time, depends only on the levels present at input terminals.

The combinational circuit do not use any memory. The previous state of input does not have any effect on the present state of the circuit.

A combinational circuit can have an n number of inputs and m number of outputs.

Block diagram

We're going to elaborate few important combinational circuits as follows.

Half Adder

Half adder is a combinational logic circuit with two inputs and two outputs. The half adder circuit is designed to add two single bit binary number A and B. It is the basic building block for addition of two single bit numbers. This circuit has two outputs carry and sum.

Block diagram

Truth Table

Circuit Diagram

Full Adder

Full adder is developed to overcome the drawback of Half Adder circuit. It can add two one-bit numbers A and B, and carry c. The full adder is a three input and two output combinational circuit.

Block diagram

Truth Table

Circuit Diagram

Half-Subtractors

Half-subtractor is a combination circuit with two inputs and two outputs (difference and borrow). It produces the difference between the two binary bits at the input and also produces an output (Borrow) to indicate if a 1 has been borrowed. In the subtraction (A-B), A is called as Minuend bit and B is called as Subtrahend bit.

Truth Table

Circuit Diagram

Full-Subtractors

The disadvantage of a half subtractor is overcome by full subtractor. The full subtractor is a combinational circuit with three inputs A,B,C and two output D and C'. A is the 'minuend', B is 'subtrahend', C is the 'borrow' produced by the previous stage, D is the difference output and C' is the borrow output.

Truth Table

Circuit Diagram

ANALYSIS PROCEDURE

Carry Look Ahead Adder

In ripple carry adders, the carry propagation time is the major speed limiting factor.

Most other arithmetic operations, e.g. multiplication and division are implemented using several add/subtract steps. Thus, improving the speed of addition will improve the speed of all other arithmetic operations. Accordingly, reducing the carry propagation delay of adders is of great importance. Different logic design approaches have been employed to overcome the carry propagation problem. One widely used approach employs the principle of carry look-ahead solves this problem by calculating the carry signals in advance, based on the input signals. This type of adder circuit is called as carry look-ahead adder (CLA adder). It is based on the fact that a carry signal will be generated in two cases: (1) when both bits Ai and Bi are 1, or (2) when one of the two bits is 1 and the carry-in (carry of the previous stage) is 1. To understand the carry propagation problem, let’s consider the case of adding two n-bit numbers A and B.

The Figure shows the full adder circuit used to add the operand bits in the ith column; namely Ai & Bi and the carry bit coming from the previous column (Ci ).

In this circuit, the 2 internal signals Pi and Gi are given by:

 The output sum and carry can be defined as :

Gi is known as the carry Generate signal since a carry (Ci+1) is generated whenever Gi =1, regardless of the input carry (Ci). Pi is known as the carry propagate signal since whenever Pi =1, the input carry is propagated to the output carry, i.e., Ci+1. = Ci (note that whenever Pi =1, Gi =0). Computing the values of Pi and Gi only depend on the input operand bits (Ai & Bi) as clear from the Figure and equations. Thus, these signals settle to their steady-state value after the propagation through their respective gates. Computed values of all the Pi’s are valid one XOR-gate delay after the operands A and B are made valid. Computed values of all the Gi’s are valid one AND-gate delay after the operands A and B are made valid.

In general, the ith carry output is expressed in the form Ci = Fi (P’s, G’s , C0). In other words, each carry signal is expressed as a direct SOP function of C0 rather than its preceding carry signal. Since the Boolean expression for each output carry is expressed in SOP form, it can be implemented in two-level circuits. The 2-level implementation of the carry signals has a propagation delay of 2 gates, i.e., 2τ. The 4-bit carry look-ahead (CLA) adder consists of 3 levels of logic:

First level: Generates all the P & G signals. Four sets of P & G logic (each consists of an XOR gate and an AND gate). Output signals of this level (P’s & G’s) will be valid after 1τ. Second level: The Carry Look-Ahead (CLA) logic block which consists of four 2-level implementation logic circuits. It generates the carry signals (C1, C2, C3, and C4) as defined by the above expressions. Output signals of this level (C1, C2, C3, and C4) will be valid after 3τ. Third level: Four XOR gates which generate the sum signals (Si) (Si = Pi ⊕ Ci). Output signals of this level (S0, S1, S2, and S3) will be valid after 4τ.

Thus, the 4 Sum signals (S0, S1, S2 & S3) will all be valid after a total delay of 4τ compared to a delay of (2n+1)τ for Ripple Carry adders. For a 4-bit adder (n = 4), the Ripple Carry adder delay is 9τ. 

The disadvantage of the CLA adders is that the carry expressions (and hence logic) become quite complex for more than 4 bits. 

Thus, CLA adders are usually implemented as 4-bit modules that are used to build larger size adders.

Design procedure

The design procedure for combinational logic circuits starts with the problem specification and comprises the following steps:

1. Determine required number of inputs and outputs from the specifications. 2. Derive the truth table for each of the outputs based on their relationships to the input. 3. Simplify the boolean expression for each output. Use Karnaugh Maps or Boolean algebra. 4. Draw a logic diagram that represents the simplified Boolean expression. Verify the design

by analysing or simulating the circuit.

BINARY Adder

If two BCD digits are added then their sum result will not always be in BCD. Consider the two given examples.

In the first example, result is in BCD while in the second example it is not in BCD. Four bits are needed to represent all BCD digits (0 – 9). But with four bits we can represent up to 16 values (0000 through 1111). The extra six values (1010 through 1111) are not valid BCD digits. Whenever the sum result is > 9, it will not be in BCD and will require correction to get a valid BCD result.

Correction is done through the addition of 6 to the result to skip the six invalid values as shown in the truth table by yellow color.Consider the given examples of non-BCD sum result and its correction.

A BCD adder is a circuit that adds two BCD digits in parallel and produces a sum BCD digit and a carry out bit. The maximum sum result of a BCD input adder can be 19. As maximum number in BCD is 9 and may be there will be a carry from previous stage also, so 9 + 9 + 1 = 19 The following truth table shows all the possible sum results when two BCD digits are added.

The logic circuit that checks the necessary BCD correction can be derived by detecting the condition where the resulting binary sum is 01010 through 10011 (decimal 10 through 19). It can be done by considering the shown truth table, in which the function F is true when the digit is not a valid BCD digit. It can be simplified using a 5-variable K-map. But detecting values 1010 through 1111 (decimal 10 through 15) can also be done by using a 4-variable K-map as shown in the figure. 

Values greater than 1111, i.e., from 10000 through 10011 (decimal 16 through 19) can be detected by the carry out (CO) which equals 1 only for these output values. So, F = CO = 1 for these values. Hence, F is true when CO is true OR when (Z3 Z2 + Z3 Z1) is true. Thus, the correction step (adding 0110) is performed if the following function equals 1:

F = CO + Z3 Z2 + Z3 Z1

The circuit of the BCD adder will be as shown in the figure.

The two BCD digits, together with the input carry, are first added in the top 4-bit binary adder to produce the binary sum. The bottom 4-bit binary adder is used to add the correction factor to the binary result of the top binary adder.  Note: 1. When the Output carry is equal to zero, the correction factor equals zero.

2. When the Output carry is equal to one, the correction factor is 0110.

The output carry generated from the bottom binary adder is ignored, since it supplies information already available at the output-carry terminal. A decimal parallel adder that adds n decimal digits needs n BCD adder stages. The output carry from one stage must be connected to the input carry of the next higher-order stage.

Questions .

1.What is half subtractor? Draw the block diagram.

2.Define half adder? Draw the block diagram.

3.Design the full subtractor using half subtractor.

4. Design the full adder using half adders.

5. Draw the basic structure of combinational logic circuit

6. What is half subtractor? Draw the block diagram.

7. Define half adder? Draw the block diagram.

8. Design the full subtractor using half subtractor.

9. Design the full adder using half adders.

10. Design a 4-bit parallel adder using full adders.

11. Sketch 4-bit adder cum subtract using full adder

Binary Multiplier

Multiplication of binary numbers is performed in the same way as with decimal numbers. The multiplicand is multiplied by each bit of the multiplier, starting from the least significant bit. The result of each such multiplication forms a partial product. Successive partial products are shifted one bit to the left. The product is obtained by adding these shifted partial products. Consider an example of multiplication of two numbers, say A and B (2 bits each), C = A x B. The first partial product is formed by multiplying the B1B0 by A0. The multiplication of two bits such as A0 and B0 produces a 1 if both bits are 1; otherwise it produces a 0 like an AND operation. So the partial products can be implemented with AND gates.The second partial product is formed by multiplying the B1B0 by A1 and is shifted one position to the left. 

 The two partial products are added with two half adders (HA). Usually there are more bits in the partial products, and then it will be necessary to use Full Adders. 

The least significant bit of the product does not have to go through an adder, since it is formed by the output of the first AND gate as shown in the Figure. A binary multiplier with more bits can be constructed in a similar manner. Consider another example of multiplying two numbers, say A (3-bit number) and B (4-bit number). Each bit of A (the multiplier) is ANDed with each bit of B (the multicand) as shown in the Figure. 

The binary output in each level of AND gates is added in parallel with the partial product of the previous level to form a new partial product. The last level produces the final product. 

Since J = 3 and K = 4, 12 (J x K) AND gates and two 4-bit ((J - 1) K-bit) adders are needed to produce a product of seven (J + K) bits. Its circuit is shown in the Figure. Note that 0 is applied at the most significant bit of augend of first 4-bit adder because the least significant bit of the product does not have to go through an adder

4-bit Magnitude Comparator

 Decoder

A decoder is a combinational circuit. It has n input and to a maximum m = 2n outputs. Decoder is identical to a demultiplexer without any data input. It performs operations which are exactly opposite to those of an encoder.

Block diagram

Examples of Decoders are following.

Code converters BCD to seven segment decoders Nixie tube decoders Relay actuator

2 to 4 Line Decoder

The block diagram of 2 to 4 line decoder is shown in the fig. A and B are the two inputs where D through D are the four outputs. Truth table explains the operations of a decoder. It shows that each output is 1 for only a specific combination of inputs.

Block diagram

Truth Table

Logic Circuit

in this topic we will try to discuss about Combinational Logic Implementation full adder circuit with a decoder and two OR Gates.

To do this at first we need to review the truth table of Full Adder circuit.

                                  Inputs       a                            b                              c

              Outputs         C              S

       0                            0                             0           0              0

       0                            0                             1           0              1

       0                            1                             0           0              1

       0                            1                             1           1              0

       1                            0                             0           0              1

       1                            0                             1           1              0

       1                            1                             0           1              0

       1                            1                             1           1              1

Truth table of Full Adder Circuit

From the truth table we have been found that S(a,b,c)=sum(1,2,4,7).,C(a,b,c)=sum(3,5,6,7)

As there are three inputs and eight min-terms, so have to use 3 to 8 line decorder. The generates the eight min-terms for a, b, c.

The OR Gate for output S forms the sum of min-terms 1, 2, 4 and 7. The OR Gate output C forms the sum of min-terms 3, 5, 6 and 7. 

Circuit Diagram

A function with a long list of min-terms requires an OR Gate with a large number of inputs. A function F having a list of K min-terms can be expressed in its  complemented form F’ with 2^n-K min-terms. If the number of min-terms in a function is greater than 2^n/2, then F’ can be expressed with fewer min-terms than required for F. In such a case, it is suitable to use a NOR Gate to sum the min-terms of F’. The output of the NOR Gate will generate the normal output F.

The decoder method can be used to implement any combinational circuit. It is necessary to implementing with comparing to all other possible implementations to determine the solution.  

Encoder

Encoder is a combinational circuit which is designed to perform the inverse operation of the decoder. An encoder has n number of input lines and m number of output lines. An encoder produces an m bit binary code corresponding to the digital input number. The encoder accepts an n input digital word and converts it into an m bit another digital word.

Block diagram

Examples of Encoders are following.

Priority encoders Decimal to BCD encoder Octal to binary encoder Hexadecimal to binary encoder

Priority Encoder

This is a special type of encoder. Priority is given to the input lines. If two or more input line are 1 at the same time, then the input line with highest priority will be considered. There are four input D0, D1, D2, D3 and two output Y0, Y1. Out of the four input D3 has the highest priority and D0 has the lowest priority. That means if D3 = 1 then Y1 Y1 = 11 irrespective of the other inputs. Similarly if D3 = 0 and D2 = 1 then Y1 Y0 = 10 irrespective of the other inputs.

Block diagram

Truth Table

Logic Circuit

Multiplexers

Multiplexer is a special type of combinational circuit. There are n-data inputs, one output and m select inputs with 2m = n. It is a digital circuit which selects one of the n data inputs and routes it to the output. The selection of one of the n inputs is done by the selected inputs. Depending on the digital code applied at the selected inputs, one out of n data sources is selected and transmitted to the single output Y. E is called the strobe or enable input which is useful for the cascading. It is generally an active low terminal that means it will perform the required operation when it is low.

Block diagram

Multiplexers come in multiple variations

2 : 1 multiplexer

4 : 1 multiplexer16 : 1 multiplexer32 : 1 multiplexer

Block Diagram

Truth Table

Demultiplexers

A demultiplexer performs the reverse operation of a multiplexer i.e. it receives one input and distributes it over several outputs. It has only one input, n outputs, m select input. At a time only one output line is selected by the select lines and the input is transmitted to the selected output line. A de-multiplexer is equivalent to a single pole multiple way switch as shown in fig.

Demultiplexers come in multiple variations.

1 : 2 demultiplexer 1 : 4 demultiplexer 1 : 16 demultiplexer 1 : 32 demultiplexer

Block diagram

Truth Table

Questions 1. Design & implement BCD to Excess-3 code converter.2. Explain carry look ahead adder circuit with the help of logic diagram.3. Construct a BCD adder-subtractor circuit.4. Implement 4-bit magnitude comparator and write down its design procedure.5. Design & implement full adder using decoder.6. Implement the following Boolean function using 8:1 multiplexer. F(A,B,C,D) = A’BD’+ACD+B’CD+A’C’D.7. What is encoder? Design octal to binary encoder. 1. Draw the basic structure of combinational logic circuit

8.Implement 2-bit by 2-bit multiplier with half adders.9. Design a 4-bit parallel adder using full adders.10. Realize a 2-bit comparator using gates.11. Draw the block diagram of 3x8 decoder with enable.12. How decoder can be converted into a demultiplexer.13. What is an encoder?14. What is priority encoder? Mention its operation.15. What is multiplexer? Draw the block diagram of 4x1 MUX.16. What are the functional differences between serial & parallel adder?17. What is demultiplexer?18. Draw 4-bit by 4-bit multiplier.19. Sketch 4x16 decoder with two 3x8 decoders.20. Draw 32:1 mux using two 16:1 mux and one 2:1 mux.21. Sketch quadruple 2-to-1-line multiplexer.

UNIT IV

SYNCHRONOUS SEQUENTIAL LOGIC

The combinational circuit does not use any memory. Hence the previous state of input does not have any effect on the present state of the circuit. But sequential circuit has memory so output can vary based on input. This type of circuits uses previous input, output, clock and a memory element.

Block diagram

Latches

The bistable element is able to remember or store one bit of information. However, because it

does not have any inputs, we cannot change the information bit that is stored in it. In order to

change the information bit, we need to add inputs to the circuit. The simplest way to add inputs is

to replace the two inverters with two NAND gates. This circuit is called a SR latch. In addition to

the two outputs Q and Q', there are two inputs S' and R' for set and reset respectively. Following

the convention, the prime in S and R denotes that these inputs are active low. The SR latch can be

in one of two states: a set state when Q = 1, or a reset state when Q = 0

SR LATCH

To make the SR latch go to the set state, we simply assert the S' input by setting it to 0. Remember that 0 NAND anything gives a 1, hence Q = 1 and the latch is set. If R' is not asserted (R' = 1), then the output of the bottom NAND gate will give a 0, and so Q' = 0. This situation is shown in Figure 4 (d) at time t0. If we de-assert S' so that S' = R' = 1, the latch will remain at the set state because Q', the second input to the top NAND gate, is 0 which will keep Q = 1 as shown at time t1. At time t2 we reset the latch by making R' = 0. Now, Q' goes to 1 and this will force Q to go to a 0. If we de-assert R' so that again we have S' = R' = 1, this time the latch will remain at the reset state as shown at time t3. Notice the two times (at t1 and t3) when both S' and R' are de-asserted. At t1, Q is at a 1, whereas, at t3, Q is at a 0. When both inputs are de-asserted, the SR latch maintains its previous state. Previous to t1, Q has the value 1, so at t1, Q remains at a 1. Similarly, previous to t3, Q has the value 0, so at t3, Q remains at a 0.

If both S' and R' are asserted, then both Q and Q' are equal to 1 as shown at time t4. If one of the input signals is de-asserted earlier than the other, the latch will end up in the state forced by the signal that was de-asserted later as shown at time t5. At t5, R' is de-asserted first, so the latch goes into the normal set state with Q = 1 and Q' = 0.

A problem exists if both S' and R' are de-asserted at exactly the same time as shown at time t6. If both gates have exactly the same delay then they will both output a 0 at exactly the same time. Feeding the zeros back to the gate input will produce a 1, again at exactly the same time, which again will produce a 0, and so on and on. This oscillating behavior, called the critical race, will continue forever. If the two gates do not have exactly the same delay then the situation is similar to de-asserting one input before the other, and so the latch will go into one state or the other. However, since we do not know which is the faster gate, therefore, we do not know which state the latch will go into. Thus, the latch’s next state is undefined.

Flip Flop

Flip flop is a sequential circuit which generally samples its inputs and changes its outputs only at particular instants of time and not continuously. Flip flop is said to be edge sensitive or edge triggered rather than being level triggered like latches

S-R Flip Flop

It is basically S-R latch using NAND gates with an additional enable input. It is also called as level triggered SR-FF. For this, circuit in output will take place if and only if the enable input (E) is made active. In short this circuit will operate as an S-R latch if E = 1 but there is no change in the output if E = 0.

Block Diagram

Circuit Diagram

Truth Table

Operation

S.N. Condition Operation

S = R = 0 : No change

If S = R = 0 then output of NAND gates 3 and 4 are forced to become 1.

Hence R' and S' both will be equal to 1. Since S' and R' are the input of the basic S-R latch using NAND gates, there will be no change in the state of outputs.

S = 0, R = 1, E = 1

Since S = 0, output of NAND-3 i.e. R' = 1 and E = 1 the output of NAND-4 i.e. S' = 0.

Hence Qn+1 = 0 and Qn+1 bar = 1. This is reset condition.

S = 1, R = 0, E = 1

Output of NAND-3 i.e. R' = 0 and output of NAND-4 i.e. S' = 1.

Hence output of S-R NAND latch is Qn+1 = 1 and Qn+1 bar = 0. This is the reset condition.

S = 1, R = 1, E = 1As S = 1, R = 1 and E = 1, the output of NAND gates 3 and 4 both are 0 i.e. S' = R' = 0

Master Slave JK Flip Flop

Master slave JK FF is a cascade of two S-R FF with feedback from the output of second to input of first. Master is a positive level triggered. But due to the presence of the inverter in the clock line, the slave will respond to the negative level. Hence when the clock = 1 (positive level) the master is active and the slave is inactive. Whereas when clock = 0 (low level) the slave is active and master is inactive.

Circuit Diagram

Truth Table

OperationS.N. Condition Operation

1 J = K = 0 (No change)When clock = 0, the slave becomes active and master is inactive. But since the S and R inputs have not changed, the slave outputs will also remain unchanged. Therefore outputs will not change if J = K =0.

2 J = 0 and K = 1 (Reset) Clock = 1 − Master active, slave inactive. Therefore outputs of the master become Q1 = 0 and Q1 bar = 1. That means S =

0 and R =1.

Clock = 0 − Slave active, master inactive. Therefore outputs of the slave become Q = 0 and Q bar = 1.

Again clock = 1 − Master active, slave inactive. Therefore even with the changed outputs Q = 0 and Q bar = 1 fed back to master, its output will be Q1 = 0 and Q1 bar = 1. That means S = 0 and R = 1.

Hence with clock = 0 and slave becoming active the outputs of slave will remain Q = 0 and Q bar = 1. Thus we get a stable output from the Master slave.

3 J = 1 and K = 0 (Set)

Clock = 1 − Master active, slave inactive. Therefore outputs of the master become Q1 = 1 and Q1 bar = 0. That means S = 1 and R =0.

Clock = 0 − Slave active, master inactive. Therefore outputs of the slave become Q = 1 and Q bar = 0.

Again clock = 1 − then it can be shown that the outputs of the slave are stabilized to Q = 1 and Q bar = 0.

4 J = K = 1 (Toggle)

Clock = 1 − Master active, slave inactive. Outputs of master will toggle. So S and R also will be inverted.

Clock = 0 − Slave active, master inactive. Outputs of slave will toggle.

These changed outputs are returned back to the master inputs. But since clock = 0, the master is still inactive. So it does not respond to these changed outputs. This avoids the multiple toggling which leads to the race around condition. The master slave flip flop will avoid the race around condition.

Delay Flip Flop / D Flip Flop

Delay Flip Flop or D Flip Flop is the simple gated S-R latch with a NAND inverter connected between S and R inputs. It has only one input. The input data is appearing at the output after some time. Due to this data delay between i/p and o/p, it is called delay flip flop. S and R will be the complements of each other due to NAND inverter. Hence S = R = 0 or S = R = 1, these input condition will never appear. This problem is avoid by SR = 00 and SR = 1 conditions.

Block Diagram

Circuit Diagram

Truth Table

OperationS.N. Condition Operation

1 E = 0 Latch is disabled. Hence no change in output.

2 E = 1 and D = 0

If E = 1 and D = 0 then S = 0 and R = 1. Hence irrespective of the present state, the next state is Qn+1 = 0 and Qn+1 bar = 1. This is the reset condition.

3 E = 1 and D = 1If E = 1 and D = 1, then S = 1 and R = 0. This will set the latch and Qn+1 = 1 and Qn+1 bar = 0 irrespective of the present state.

Toggle Flip Flop / T Flip Flop

Toggle flip flop is basically a JK flip flop with J and K terminals permanently connected together. It has only input denoted by T as shown in the Symbol Diagram. The symbol for positive edge triggered T flip flop is shown in the Block Diagram.Symbol Diagram

Block Diagram

Truth Table

OperationS.N. Condition Operation

1 T = 0, J = K = 0 The output Q and Q bar won't change

2 T = 1, J = K = 1 Output will toggle corresponding to every leading edge of clock signal.

Questions

1. a) Design D Flip Flop by using SR Flip Flop and draw the timing diagram

b) Write the differences between combinational and sequential circuits

3. a) Draw the logic symbol, characteristics table and derive characteristics equation of JK flip flop

b) Design T Flip Flop by using JK Flip Flop and draw the timing diagram

4. a) Draw the circuit of JK flip flop using NAND gates and explain its operation

b) Design a 2-input 2-output detector which produces an output 1 every time the

sequence 0101 is detected. Implement the sequence detector using JK flip-flops.

5. (i) Draw the logic diagram of the circuit. (ii) List the state table and draw the

corresponding state diagram

Analysis of Clocked (Synchronous) Sequential Circuits

The behavior of a clocked sequential circuit is determined from its inputs, outputs and state of the flip-flops (i.e., the output of the flip-flops). The analysis of a clocked sequential circuit consists of obtaining a table of a diagram of the time sequences of inputs, outputs and states.

REGISTER

Flip-flop is a 1 bit memory cell which can be used for storing the digital data. To increase the storage capacity in terms of number of bits, we have to use a group of flip-flop. Such a group of flip-flop is known as a Register. The n-bit register will consist of n number of flip-flop and it is capable of storing an n-bit word.

The binary data in a register can be moved within the register from one flip-flop to another. The registers that allow such data transfers are called as shift registers. There are four mode of operations of a shift register.

Serial Input Serial Output Serial Input Parallel Output Parallel Input Serial Output Parallel Input Parallel Output

Serial Input Serial Output

Let all the flip-flop be initially in the reset condition i.e. Q3 = Q2 = Q1 = Q0 = 0. If an entry of a four bit binary number 1 1 1 1 is made into the register, this number should be applied to Din bit with the LSB bit applied first. The D input of FF-3 i.e. D3 is connected to serial data input Din. Output of FF-3 i.e. Q3 is connected to the input of the next flip-flop i.e. D2

and so on.

Block Diagram

OperationBefore application of clock signal, let Q3 Q2 Q1 Q0 = 0000 and apply LSB bit of the number to be entered to Din. So Din = D3 = 1. Apply the clock. On the first falling edge of clock, the FF-3 is set, and stored word in the register is Q3 Q2 Q1 Q0 = 1000.

Apply the next bit to Din. So Din = 1. As soon as the next negative edge of the clock hits, FF-2 will set and the stored word change to Q3 Q2 Q1 Q0 = 1100.

Apply the next bit to be stored i.e. 1 to D in. Apply the clock pulse. As soon as the third negative clock edge hits, FF-1 will be set and output will be modified to Q3 Q2 Q1 Q0 = 1110.

Similarly with Din = 1 and with the fourth negative clock edge arriving, the stored word in the register is Q3 Q2 Q1 Q0 = 1111.

Truth Table

Waveforms

Bidirectional Shift Register

If a binary number is shifted left by one position then it is equivalent to multiplying the original number by 2. Similarly if a binary number is shifted right by one position then it is equivalent to dividing the original number by 2.

Hence if we want to use the shift register to multiply and divide the given binary number, then we should be able to move the data in either left or right direction.

Such a register is called bi-directional register. A four bit bi-directional shift register is shown in fig.

There are two serial inputs namely the serial right shift data input DR, and the serial left shift data input DL along with a mode select input (M).

Block Diagram

Operation

S.N. Condition Operation

With M = 1 − Shift right operation

If M = 1, then the AND gates 1, 3, 5 and 7 are enabled whereas the remaining AND gates 2, 4, 6 and 8 will be disabled.

The data at DR is shifted to right bit by bit from FF-3 to FF-0 on the application of clock pulses. Thus with M = 1 we get the serial right shift operation.

With M = 0 − Shift left operation When the mode control M is connected to 0 then the AND gates 2, 4, 6 and 8 are enabled

while 1, 3, 5 and 7 are disabled.

The data at DL is shifted left bit by bit from FF-0 to FF-3 on the application of clock pulses. Thus with M = 0 we get the serial right shift operation.

A shift register which can shift the data in only one direction is called a uni-directional shift

register. A shift register which can shift the data in both directions is called a bi-directional

shift register. Applying the same logic, a shift register which can shift the data in both

directions as well as load it parallely, is known as a universal shift register. The shift register

is capable of performing the following operation −

Parallel loading

Lift shifting

Right shifting

The mode control input is connected to logic 1 for parallel loading operation whereas it is

connected to 0 for serial shifting. With mode control pin connected to ground, the universal

shift register acts as a bi-directional register. For serial left operation, the input is applied to

the serial input which goes to AND gate-1 shown in figure. Whereas for the shift right

operation, the serial input is applied to D input.

Block Diagram

COUNTER

Counter is a sequential circuit. A digital circuit which is used for a counting pulses is

known counter. Counter is the widest application of flip-flops. It is a group of flip-flops with

a clock signal applied. Counters are of two types.

Asynchronous or ripple counters.

Synchronous counters.

ASYNCHRONOUS OR RIPPLE COUNTERS

The logic diagram of a 2-bit ripple up counter is shown in figure. The toggle (T) flip-flop

are being used. But we can use the JK flip-flop also with J and K connected permanently to

logic 1. External clock is applied to the clock input of flip-flop A and QA output is applied to

the clock input of the next flip-flop i.e. FF-B.

Logical Diagram

Operation

S.N

.Condition Operation

1 Initially let both the FFs be in the reset

state

QBQA = 00 initially

2 After 1st negative clock edge

As soon as the first negative clock edge

is applied, FF-A will toggle and QA will

be equal to 1.

QA is connected to clock input of FF-B.

Since QA has changed from 0 to 1, it is

treated as the positive clock edge by FF-

B. There is no change in QB because FF-

B is a negative edge triggered FF.

QBQA = 01 after the first clock pulse.

3 After 2nd negative clock edge

On the arrival of second negative clock

edge, FF-A toggles again and QA = 0.

The change in QA acts as a negative

clock edge for FF-B. So it will also

toggle, and QB will be 1.

QBQA = 10 after the second clock pulse.

4 After 3rd negative clock edge

On the arrival of 3rd negative clock

edge, FF-A toggles again and QA

become 1 from 0.

Since this is a positive going change,

FF-B does not respond to it and remains

inactive. So QB does not change and

continues to be equal to 1.

QBQA = 11 after the third clock pulse.

5 After 4th negative clock edge On the arrival of 4th negative clock

edge, FF-A toggles again and QA

becomes 1 from 0.

This negative change in QA acts as clock

pulse for FF-B. Hence it toggles to

change QB from 1 to 0.

QBQA = 00 after the fourth clock pulse.

Truth Table

Synchronous counters

If the "clock" pulses are applied to all the flip-flops in a counter simultaneously, then such

a counter is called as synchronous counter.

2-bit Synchronous up counter

The JA and KA inputs of FF-A are tied to logic 1. So FF-A will work as a toggle flip-flop.

The JB and KB inputs are connected to QA.

Logical Diagram

OperationS.N.

Condition Operation

1Initially let both the FFs be in the reset state

QBQA = 00 initially.

2 After 1st negative clock edge

As soon as the first negative clock edge is applied, FF-A will toggle and QA will change from 0 to 1.

But at the instant of application of negative clock edge, QA , JB = KB = 0. Hence FF-B will not change its state. So QB will remain 0.

QBQA = 01 after the first clock pulse.

3 After 2nd negative clock edge

On the arrival of second negative clock edge, FF-A toggles again and QA

changes from 1 to 0.

But at this instant QA was 1. So JB = KB= 1 and FF-B will toggle. Hence QB

changes from 0 to 1.

QBQA = 10 after the second clock pulse.

4 After 3rd negative clock edge On application of the third falling clock edge, FF-A will toggle from 0 to 1 but there is no change of state for FF-B.

QBQA = 11 after the third clock pulse.

5 After 4th negative clock edge

On application of the next clock pulse, QA will change from 1 to 0 as QB will also change from 1 to 0.

QBQA = 00 after the fourth clock pulse.

Ring Counters

Ring counters are a type of counter created using shift registers. A shift register is constructed using D-type flip-flops where the output of one flip-flop is connected to the input of another flip-flop With ring counters, the output of the last flip-flop is fed to the input of the first flip-flop. Ring counters do not count using normal binary code, but their internal state can be used to decode to any output sequence wanted.

There are two types of ring counters:

a) Straight ring counter

b) Johnson counter

There is a third counter type using a shift register, the Linear Feedback Shift Register (LFSR). It has a more elaborate feedback circuit than the other two ring counters and is therefore not discussed in this document.

Straight ring counter

A straight ring counter or Overbeck counter connects the output of the last flip-flop to the first flip-flop input and circulates a single one bit around the ring. It provides a one-hot counting sequence. For example, in a 4-register ring counter, with initial register values of 1000, the repeating sequence is 1000, 0100, 0010, 0001. Note that one of the flip-flops must be pre-loaded with a logic 1 in order for it to operate properly. Also note that an n-bit ring counter cycles through exactly n states.

A schematic of a 4-bit straight ring counter is given in Figure 1. The asynchronous reset will set the initial contents of the counter to 1000 (note that the least significant flip-flop is on the left side).

clk

reset

Figure 1: A 4-bit straight ring counter

1D

[FF3]

1D

[FF2]

1D

[FF1]

1D

[FF0]

Johnson Counter

Another form of ring counter is created by feeding back the complement of the contents of the last flip-flop to the input of the first flip-flop. This is called a twisted ring counter, but is better known as the Johnson counter. The alternative term Möbius counter is found in many books and articles because the Johnson counter resembles the famous Möbius strip .For example, in a 5-flip-flop Johnson counter with an initial register contents (or state) of 00000, the repeating sequence is 00000, 10000, 11000, 11100,11110, 11111, 01111, 00111, 00011, 00001. When observing the pattern, it can be seen that any changes between succeeding states, only one flip-flop changes state. As a result, any of these states is directly, spike-free decodable with only a two-input gate.

Figure 2 shows a 5-bit Johnson counter with terminal count output tc. This output becomes high in the last counting state 00001 before returning to 00000.

clk

tc

Figure 2: A 5-bit Johnson Counter with Terminal Count. The reset is omitted for clarity.

Only the two most significant flop-flops have to be sampled, so tc is logic ‘1’ when Q3 is logic ‘0’ and Q4 is logic ‘1’. Using De Morgan’s theorem, the resulting function can be realised using a NOR gate and the already available flip-flop outputs.

tc = Q3 · Q4 = Q3 + Q4 (1)

It can be easily shown that an n-bit Johnson counter cycles through exactly 2n states. This becomes increasingly inefficient for n > 2 since any n-bit counter has 2n states by itself. If the Johnson counter enters a state that does not belong to the original counting sequence, it will exhibit a single parasitic counting sequence with 2n − 2n states [7, 8]. This is why most commercial devices incorporate self-correcting logic. Within a full counting sequence or so, the device will resume normal operation, as shown for example in the

1D

[FF4]

1D

[FF3]

1D

[FF2]

1D

[FF1]

1D

[FF0]

≥1

UNIT-V

FINITE STATE MACHINES & PROGRAMMABLE MEMORIES

INTRODUCTION TO FSM

We begin our discussion of state machines with a simple example. Consider a turnstile entry control at a subway station: a rotating gate with a coin receiver. The gate is initially ‘locked” and will not rotate to allow a passenger to pass through. When a coin or token is deposited into the receiver, the gate is “unlocked” but does not turn until the person actually pushes on it and passes through the turnstile, at which time the gate locks until the next coin is deposited. From this description, it should be clear that the turnstile is always in exactly 1 of 2 possible states: Locked or Unlocked. There are also only 2 transition triggers: depositing a Coin and Passing through the gate. We can model the system graphically, using rounded rectangles to represent states and arrows to represent transitions between states, as shown in Figure 1 below.

Figure 1: Simple State Machine Model of a Turnstile

While this is a good approximation of how the system functions, we can see that certain information about the turntile’s behavior is not clearly defined. What happens when a coin is deposited before someone passes through the gate? Similarly, what happens if a person tries to pass through the gate without depositing a coin? In both cases, our simple model should remain in its current state. We show this behavior with “loop” transitions in Figure 2. We also add an indication of the initial state of the system using a solid circle and an arrow pointing to the start state.

We could continue to refine this model, but instead we will begin developing a conceptual definition of a finite state machine (FSM).

PassUnlockedLocked

Coin

PassUnlockedLocked

CoinCoinPass

Figure 2: Improved State Machine Model of a Turnstile

Conceptual Definition of a Finite State Machine

From the discussion thus far, we can identify several key characteristics of a system that can be modeled with a finite state machine:The system must be describable by a finite set of states.

• The system must have a finite set of inputs and/or events that can trigger transitions between states.

• The behavior of the system at a given point in time depends upon the current state and the input or event that occur at that time.

• For each state the system may be in, behavior is defined for each possible input or event.

• The system has a particular initial state. Let us consider another example of a system that can be described by a finite state machine — an old, mechanical soda machine. This machine dispenses only 1 kind of soft drink at the price of $0.30 each. It accepts only nickels, dimes, and quarters and automatically returns change for any amount deposited over$0.30. The machine has 2 buttons — one for dispensing a drink; the other to return the deposited coins. Because this is a purely mechanical system, it does not have a memory system, nor can it directly perform arithmetic operations like addition or subtraction.

We begin our analysis of this system by identifying the possible inputs to the soda machine: nickel (N), dime (D), quarter (Q), dispense button (DB), and coin return (R). To identify possible states for the machine, start with the states we can get to by depositing a single coin. We can label these states with the value, in cents, of the coins deposited so far: 5, 10, and 25. We illustrate our model thus far in Figure 3.Next, we can think about what happens when we deposit a nickel in addition to the first coin. The resulting model is shown in Figure 4. We continue this expansion until we have identified the minimal set of states that lead to a total of at least $0.30, but are less than $0.55 (since depositing a quarter after 30 cents has been deposited will return the quarter immediately without changing the state of the machine). We show this version of the FSM in Figure 5. The FSM in Figure 5 covers all possible inputs as long as the sum of the coins previously deposited is less than $0.30. Obviously, the graphical representation of this FSM is quickly becoming hard to handle, so we will introduce an alternative: a tabular representation. We list the states down the left side, and the inputs across the top. The table cell at the intersection of a particular row and column indicates the destination state of the FSM when the column’s input is received when the machine is in the row’s state.

Figure 3: Start of the Soda Machine FSM Model

Figure 4: Second Phase of the Soda Machine FSM Model

Mealy & Moore Models

Moore: outputs depend on current state only

Mealy: outputs depend on current state and inputs

Ant brain is a Moore Machine

Output does not react immediately to input change

We could have specified a Mealy FSM

Outputs have immediate reaction to inputs

As inputs change, so does next state, doesn’t commit until clocking even

25

Q

10D

S

N

5

3025N

Q

15N

10D

S

NN

5

State Reduction

The three main methods of state reduction include: row matching, implication charts, and successive partitioning. Row matching, which is the easiest of the three, works well for state transition tables which have an obvious next state and output equivalences for each of the present states. This method will generally not give the most simplified state machine available, but its ease of use and consistently fair results is a good reason to pursue the method. The implication chart uses a graphical grid to help find any implications or equivalences and is a great systematic approach to reducing state machines. Successive partitioning is almost a cross between row matching and implication chart where both a graphical table and equivalent matching is used.ach of these methods will, in most cases, reduce a state machine into a smaller number of states. Keep in mind that one method may result in a simpler state machine than another. Experience will help in understanding and determining the best method to use in any particular situatio

STATE ASSIGNMENT

The aim of the proposed state assignment method is to minimize the number of the PAL-based macrocells by fitting the FSM to the structure of the CPLD as good as possible (Czerwiński and Kania, 2005; Czerwiński et al., 2006). The elements of two-level minimization are included in the state assignment process.

MEMORY

A memory is just like a human brain. It is used to store data and instruction. Computer memoryis the storage space in computer where data is to be processed and instructions required for processing are stored.The memory is divided into large number of small parts. Each part is called a cell. Each location or cell has a unique address which varies from zero to memory size minus one.

For example if computer has 64k words, then this memory unit has 64 * 1024 = 65536 memorylocation. The address of these locations varies from 0 to 65535.

Memory is primarily of two types

Internal Memory − cache memory and primary/main memory

External Memory − magnetic disk / optical disk etc.

Characteristics of Memory Hierarchy are following when we go from top to bottom.

Capacity in terms of storage increases. Cost per bit of storage decreases. Frequency of access of the memory by the CPU decreases. Access time by the CPU increases.

RAM

A RAM constitutes the internal memory of the CPU for storing data, program and program result. It is read/write memory. It is called random access memory (RAM).Since access time in RAM is independent of the address to the word that is, each storage location insidethe memory is as easy to reach as other location & takes the same amount of time. We can reach intothe memory at random & extremely fast but can also be quite expensive.

RAM is volatile, i.e. data stored in it is lost when we switch off the computer or if there is a power failure. Hence, a backup uninterruptible power system (UPS) is often used with computers. RAM is small, both in terms of its physical size and in the amount of data it can hold.

RAM is of two types

Static RAM (SRAM) Dynamic RAM (DRAM)

Static RAM (SRAM)

The word static indicates that the memory retains its contents as long as power remains applied. However, data is lost when the power gets down due to volatile nature. SRAM chips use a matrix of 6-transistors and no capacitors. Transistors do not require power to prevent leakage, so SRAMneed not have to be refreshed on a regular basis.Because of the extra space in the matrix, SRAM uses more chips than DRAM for the same amount of storage space, thus making the manufacturing costs higher.Static RAM is used as cache memory needs to be very fast and small.

Dynamic RAM (DRAM)

DRAM, unlike SRAM, must be continually refreshed in order for it to maintain the data. This is done by placing the memory on a refresh circuit that rewrites the data several hundred timesper second. DRAM is used for most system memory because it is cheap and small. All DRAMs are made up of memory cells. These cells are composed of one capacitor and one transistor.

MEMORY DECODING

The equivalent logic of a binary cell that stores one bit of information is shown below. Read/Write = 0, select = 1, input data to S-R latch Read/Write = 1, select = 1, output data from S-R latch

4X4 RAM

There is a need for decoding circuits to select the memory word specified by the input address.

During the read operation, the four bits of the selected word go through OR gates to the output terminals.

During the write operation, the data available in the input lines are transferred into the four binary cells of the selected word.

A memory with 2k words of n bits per word requires k address lines that go into

kx2k decoder.

Error detection & correction

In block coding, we divide our message into blocks, each of k bits, called datawords. We add r redundant bits to each block to make the length n = k + r. The resulting n-bit blocks are called codewords. How the extra r bits is chosen or calculated is something we will discuss later. For the moment, it is important to know that we have a set of datawords, each of size k, and a set of codewords, each of size of n. With k bits, we can create a com- bination of 2k datawords; with n bits, we can create a combination of 2n codewords. Since n > k, the number of possible codewords is larger than the number of possible data- words. The block coding process is one-to-one; the same dataword is always encoded as the same codeword. This means that we have 2n

2k codewords that are not used. We call these codewords invalid or illegal

ERROR DETECTION & CORRECTION

In block coding, we divide our message into blocks, each of k bits, called datawords. We add r redundant bits to each block to make the length n = k + r. The resulting n-bit blocks are called codewords. How the extra r bits is chosen or calculated is something we will discuss later. For the moment, it is important to know that we have a set of datawords, each of size k, and a set of codewords, each of size of n. With k bits, we can create a com- bination of 2k datawords; with n bits, we can create a combination of 2n codewords. Since n > k, the number of possible codewords is larger than the number of possible data- words. The block coding process is one-to-one; the same dataword is always encoded as the same codeword. This means that we have 2n

2k codewords that are not used. We call these codewords invalid or illegal

READ-ONLY MEMORY(ROM): perform only the read operation.

The read-only memory is a programmable logic device. Other such units are the programmable logic

array(PLA), the programmable array logic(PAL), and the field- programmable array(FPGA).

Array logic

A typical programmable logic device may have hundreds to millions of gates interconnected through hundreds to thousands of internal paths. In order to show the internal logic diagram in a concise form, it is necessary to employ a special gate applicable to array logic.

Programmable Read Only Memory (PROM)

A block diagram of a ROM is shown below. It consists of k address inputs and n data outputs. The number of words in a ROM is determined from the fact that k address input lines are needed to specify 2k words.

Construction of ROM

Each output of the decoder represents a memory address. Each OR gate must be considered as having 32 inputs. A 2k X n ROM will have an internal k X 2k decoder and n OR gates.

Truth table of ROM

A programmable connection between to lines is logically equivalent to a switch that can be altered to either be close or open .Intersection between two lines is sometimes called a cross-point.

Types of ROMs

The required paths in a ROM may be programmed in four different ways. Mask programming: fabrication process Read-only memory or PROM: blown fuse /fuse intact Erasable PROM or EPROM: placed under a special ultraviolet light for a given period of time

will erase the pattern in ROM. Electrically-erasable PROM(EEPROM): erased with an electrical signal instead of ultraviolet

light.

Combinational PLDs□ A combinational PLD is an integrated circuit with programmable gates divided into an

AND array and an OR array to provide an AND-OR sum of product implementation.

□ PROM: fixed AND array constructed as a decoder and programmable OR array.□ PAL: programmable AND array and fixed OR array. PLA: both the AND and OR arrays can be programmed.

Programmable Logic Array

The decoder in PROM is replaced by an array of AND gates that can be programmed to generate any product term of the input variables. The product terms are then connected to OR gates to provide the sum of products for the required Booleanfunctions. The output is inverted when the XOR input is connected to 1 (since x⊕1 = x’). The output doesn’t change and connect to 0 (since x⊕0 = x).F1 = AB’+AC+A’BC’ F2 = (AC+BC)’

Programming Table

First: lists the product terms numerically Second: specifies the required paths between inputs and AND gates

Third: specifies the paths between the AND and OR gatesFor each output variable, we may have a T(ture) or C(complement) for programming the XOR gate

Simplification of PLA

Careful investigation must be undertaken in order to reduce the number of distinct product terms, PLA has a finite number of AND gates. Both the true and complement of each function should be simplified to see which one can be expressed with fewer product

terms and which one provides product terms that are common to other functions.Example

Implement the following two Boolean functions with a PLA: F1(A, B, C) = ∑(0, 1, 2, 4)

F2(A, B, C) = ∑(0, 5, 6, 7)

PLA table by simplifying the function

Both the true and complement of the functions are simplified in sum of products. We can find the same terms from the group terms of the functions of F1, F1’,F2 and F2’ which will make the minimum terms.F1 = (AB + AC + BC)’ F2 = AB + AC + A’B’C’

Programmable Array Logic

The PAL is a programmable logic device with a fixed OR array and a programmable AND array.

When designing with a PAL, the Boolean functions must be simplified to fit into each section. Unlike the PLA, a product term cannot be shared among two or more OR gates. Therefore, each function can be simplified by itself without regard to common product terms. The output terminals are sometimes driven by three-state buffers or inverters.Example

PAL Table

z has four product terms, and we can replace by w with two product terms, this will reduce the number of terms for z from four to three.