SIDDHARTH INSTITUTE OF ENGINEERING &TECHNOLOGY:: PUTTURELECTRONICS & COMMUNICATON ENGINEERING

DIGITAL IC APPLICATIONSQUESTION BANK

UNIT –I

CMOS LOGIC AND BIPOLAR LOGIC AND INTERFACING1) a) Design a 4-input CMOS AND-OR-INVERTER gate .draw the logic diagram and functional table?

5M [L2][CO1]b) Draw the CMOS inverter and explain its behavior for LOW and HIGH outputs? 5M [L2][CO1]

2) a) Draw the circuit diagram of basic CMOS gate and explain the operation? 5M [L2][CO1] b) Compare CMOS, TTL and ECL logic families. 5M [L5][CO1]3) a) Draw the circuit diagram of a two input LS-TTL nor gate and explain the functional behavior?

5M [L2][CO1] b) Explain in detail about basic ECL logic circuit. 5M [L2][CO1]4) Design the ECL 10K OR/NOR gate and explain its functionality? 10M [L2][CO1]5) a) Design CMOS transistor circuit for 2-input AND gate. With the help of function table, explain the circuit.

5M [L3][CO1] b) Design a CMOS circuit that has the functional behavior f(Z)=A.(B+C). 5M [L4][CO1]6) a) What is the difference between transition time and propagation delay? Explain these two parameters with reference to CMOS logic. 5M [L2][CO1] b) Explain sinking current and sourcing current of TTL Output. Which of the above parameters decide the fan out and how? 5M [L2][CO1]7) a) Distinguish between static and dynamic power dissipation of CMOS circuit. Derive the expression for dynamic power dissipation. 5M [L4][CO1] b) Compare HC, HCT, VHC and VHCT CMOS logic families. 5M [L4][CO1]8) a) Design a three input NAND gate using diode logic and a transistor inverter. Analyze the circuit with the help of transfer characteristics. 5M [L3][CO1] b) Explain the following terms with reference to TTL gate. 5M [L2][CO1]

i) D.C noise margin ii) Logic levels9) a) Draw the circuit diagram of basic TTL NOR gate and explain the three parts with the help of functional operation. 5M [L3][CO1] b) Explain TTL and CMOS interfacing. 5M [L2][CO1]10) a) State CMOS logic levels. 2M [L2][CO1] b) Define Fan-in, Fan-out. 2M [L2][CO1] c) Draw the symbol of NMOS and PMOS transistor. 2M [L2][CO1] d) Define TTL logic levels and noise margin. 2M [L2][CO1] e) Define static and dynamic power dissipation. 2M [L2][CO1]

UNIT –II

THE VHDL HARDWARE DESCRIPION LANGUAGE

1) a) Explain the various data types supported by VHDL. Give the necessary examples. 5M [L2][CO2] b) Explain about VHDL program structure. 5M [L2][CO2]2) a) Explain about functions and procedures with an examples. 5M [L2][CO2] b) Explain about libraries and packages. 5M [L2][CO2]3) a) Design a logic circuit to detect prime number. Write the VHDL program for it. 5M [L4][CO2] b) Design the logic circuit and write a data-flow style VHDL program for the following function. F (P) = ∑A,B,C,D (1,5,6,7,9,13) + d(4,15). 5M [L4][CO2]4) Draw and explain in detail of VHDL design flow. 10M [L2][CO2]5) a) Write about structural design elements with VHDL code. 5M [L2][CO2] b) Write a VHDL entity and Architecture for the following function. F(x) = (a + b) (c d) Also draw the relevant logic diagram. 5M [L3][CO2]6) Design the logic circuit and write VHDL program for the following functions. 10M [L4][CO2]

a) F(X) = ∑A, B, C, D (0, 2, 5, 7, 8, 10, 13, 15) + d (1, 6, 11). b) F(Y) = ∏A, B,C,D (1, 4, 5, 7, 9, 11, 12, 13, 15).7) Design a logic circuit to detect prime numbers and write the VHDL code in component declaration

10M [L3][CO2]8. Explain in detail different modeling styles of VHDL with suitable examples. 10M [L2][CO2]9) a) What is the importance of time dimension in VHDL and explain. 5M [L2][CO2] b) Explain the behavioral design elements of VHDL. 5M [L2][CO2]10. Write Short notes

a) Syntax of entity declaration. 2M [L2][CO2]

b) Process statement in VHDL. 2M [L2][CO2]

c) Difference between Signal and Variable. 2M [L2][CO2]

d) Difference between Function and Procedure. 2M [L2][CO2]

e) IEEE Library. 2M [L1][CO2]

UNIT –III

COBINATIONAL LOGIC DESIGN1. a) Design a 4 to 16 decoder with 74×138 IC’s. 5M [L2][CO3]

b) Write a VHDL program for the above design. 5M [L3][CO3]

2. a) Design a Full adder and Half adder logic circuit. 5M [L2][CO3]

b) Write VHDL code for the above design. 5M [L3][CO3]

3. Write a process based VHDL program for the prime-number detector of 4-bit input and explain the flow using

logic circuit. 10M [L2][CO3]

4. Write a behavioral VHDL code for a74X280 (9 input parity checker. 10M [L3][CO3]

5. a) With the help of logic diagram explain 74×157 multiplexer. 5M [L2][CO3]

b) Write the data flow style VHDL program for this IC. 5M [L2][CO3]

6. Draw the logic diagram, logic symbol of 74 x 245 octal 3-state trans-receivers and explain its operation.

10M [L3][CO3]

7. Design a priority encoder that can handle 32 requests. Use 74×148 and required discrete gates. Provide the

truth table and explain the operation. 10M [L3][CO3]

8. a) Write a VHDL program for a 74x181 ALU. 5M [L2][CO3]

b) Draw the structure of a 4-bit comparator and briefly explain about it. Write a structural VHDL code for it.

5M [L3][CO3]

9. a) Draw the logic symbol of 74 x 85, 4-bit comparator and write a VHDL code for it. 5M[L2][CO3]

b) Design a 16-bit comparator using 74×85 Ics. 5M [L2][CO3]

10. Write Short notes on

a) Draw the circuit for 2-to-4 line decoder. 2M [L2][CO3]

b) Draw the circuit for Full adder using two half adders. 2M [L2][CO3]

c) List different keywords in VHDL program. 2M [L2][CO3]

d) Define library and library clause. 2M [L2][CO3]

e) Define parity generator and checker. 2M [L2][CO3]

UNIT –IVSEQUENTIAL MACHINE DESIGN PRACTICES

1. Write a VHDL code for a serial adder using Mealy type FSM. 10M [L3][CO4]

2. Write a VHDL code for traffic light controller. 10M[L3][CO4]

3. Design an 8 bit parallel in and serial out shift register. Explain the operation of the above Shift register with

the help of timing waveforms. 10M[L4][CO4]

4. Draw the logic diagram of 74x194 and explain the operation. 10M[L3][CO4]

5. What is the difference between ring counter and Johnson ring counter? Design a self-correcting 4 bit, 4 state

ring counter with a single circulating 0 using 74x194. 10M [L4][CO4]

1. Explain how serial data communication is possible using 74x166 as transmitter and 74x164 as receiver.

10M [L2][CO4]

7. a) Distinguish between the synchronous and asynchronous counters. 5M [L4][CO4]

b) What are the impediments to synchronous design? 5M [L2][CO4]

8. Discuss the logic circuits of 74x377 register. Write a VHDL program for the above logic. 10M [L4][CO4]

9. Design a bit LFSR counter using 74x194.List out the sequence assuming that the initial state 111.

10M [L4][CO4]

10 a) Draw the 4 bit parallel in parallel out shift register. 2M [L2][CO4]

b) Draw the logic diagram of IC 7495. 2M [L2][CO4]

c) Draw the logic diagram of IC 74195. 2M [L2][CO4]

d) What is ring counter? 2M [L2][CO4]

e) What do you mean by self-correcting counter. 2M [L2][CO4]

UNIT –VDESIGN ELEMENTS AND SEQUENTIAL LOGIC DESIGN

1. Write a VHDL code for fixed point to floating point conversion. 10M[L3][CO3]

2. What is a dual priority encoder? Explain and write VHDL code for it. 10M[L3][CO3]

3. Design a barrel shifter forv8-bit using three control inputs. Write a VHDL program for the same in data flow

style 10M [L4][CO3]

4. Write a VHDL code for 8 bit comparator circuit. Using this entity write a VHDL code for 24 bit comparator.

Use the structural model for it. 10M [L4][CO3]

5. a) Distinguish between latch and flip flop .Show the logic diagram for both. Explain the operation with the

help of function table. 10M [L4][CO3]

b) Write a VHDL code for a D-flip flop in behavioral model. 5M [L4][CO3]

6. a) Design a self-correcting 4 bit, 4 state ring counter. 5M [L4][CO3]

b) Design a self-correcting 4 bit, 8 state ripple counter. 5M [L4][CO3]

7. a) Distinguish between the synchronous and asynchronous counters 5M [L4][CO3]

b) What are the impediments to synchronous design? 5M [L4][CO3]

8. What is PLD’s? Explain in detail with help of neat sketches. 10M [L4][CO3]

9. Explain about combinational multiplier with a neat diagram. 10M[L2][CO3]

10. Write short notes on

(i) Clock skew. 2M [L2][CO3]

(ii) Gating the clock. 2M [L2][CO3]

(iii) Asynchronous inputs. 2M [L2][CO3]

(iv) Latch and Flip-flop. 2M [L2][CO3]

(v) Ring counter. 2M [L2][CO3]

SIDDHARTH INSTITUTE OF ENGINEERING &TECHNOLOGY:: PUTTURELECTRONICS & COMMUNICATON ENGINEERING

DIGITAL IC APPLICATIONS

BITBANK

UNIT –I

CMOS LOGIC & BIPOLAR LOGIC AND INTERFACING

1. The time takes for the output of a logic circuit to change from one state another state is called [ ]A) Rise time B) Fall time C) Propagation time D) Transition time

2. Dynamic characteristics of CMOS mainly depend on [ ]A) Capacitive load B) Resistive load C) Both A&B D) None

3. First integrated circuit logic family was introduced in [ ]A) 1960 B) 1947 C) 1820 D) 1957

4. The inverter 74AL S04 has the following specifications (Gate-97) [ ] IOH max = -0.4mA, IOL max = 8mA , IIH max = 20µA ,IIL max = -0.1mA the fan out based on above will be

A) 10 B) 20 C) 60 D) 1005. Transistor can act as a switch in which region [ ]

A) Cut off region B) Saturation region C) Active region D) All the above6. Sink current makes the output is at which state [ ]

A) Low B) High C) Undefined D) None7. A Darlington Emitter follower circuit is sometimes used in the output stage of a TTL gate

in order to (Gate-99) [ ]A) In increase its IOL B) Reduce its IOH

C) Increase its speed of operation D) Reduce power dissipation8. Which logic family is the fastest logic family [ ]

A) PMOS B) NMOS C) CMOS D) ECL9. TTL output stage is called [ ]

A) Totem pole B) Pushback C) Pullback D) Pull down 10. Logic family that dissipates more power [ ]

A) TTL B) ECL C) CMOS D) DTL11. The power consumption of a CMOS in DC condition is known as [ ]

A) Static B) Quiescent C) A or B D) None12. Interfacing of different logic families what type of parameters are considered [ ]

A) Fan out B) Load capacitance C) Noise margin D) All the above13. Source current makes output logic is at which state [ ]

A) Low B) High C) Undefined D) None14. Which Regions of transistor acts as OFF and ON switch respectively [ ]

A) Active& saturation region B) Cutoff region &saturationC) Cutoff & active region D) All the above

15. The noise margin of a TTL gate is about (Gate-98) [ ]A) 0.2V B) 0.4V C) 0.6V D) 0.8V

16. Commercially available ECL gates use two ground lines and one negative supply in order to (Gate-99) [ ]

A) To reduce power dissipation B) Increase fan-outC) Reduce loading effect D) Eliminate the effect of power line glitches or the biasing circuit

17. For the difference between Voh (min)-Vih (min) and Vil (max)-Vol (max) differences should be [ ]A) Positive value B) Negative value C) Zero D) Any value

18. Which logic family has high input impedance [ ]A) TTL B) CMOS C) ECL D) RTL

19. In standard TTL the totem pole stage refers to (Gate-97) [ ]A) The multi emitter input stage B) The phase splitterC) The output buffer D) Open collector output stage

20. Sink current indicates the output of CMOS as [ ]A) Logic 0 B) Logic 1 C) Both A&B D) All the above

21. State ‘0’ representing bit in TTL logic is [ ]A) 0-1.5V B) 3.5-5V C) 0-0.8V D) 2.0-5.0V

22. In PMOS transistor Vgs is increased then Rds is [ ]A) Increases B) Decreases C) Remains constant D) None

23. Power dissipation of CMOS in DC will be [ ]A) High B) Low C) Very low D) Very high

24. High state noise margin is defined as [ ]

A)Vnh=Vil (max)-Voh (min) B) Vnh=Vil (max)-Vol(max)

C)Vnh=Voh (min) -Vih (min) D) Vnh=Vol(max)-Vil(max)25. A diode can act as a switch in which bias [ ]

A) Reverse B) Forward C) Zero D) None26. Fan-out defined as [ ]

A) No of gates it can drive B) No of gates it can driven C) Both D) None27. Which logic family consumes less power [ ]

A) CMOS B) TTL C) ECL D) DTL28. The output of the 74 series of TTL gates is taken from a BJT in (Gate-03) [ ]

A) Totem pole and common collector configurationB) Either totem pole or common collector configurationC) Common base configurationD) Common collector configuration

29. NMOS transistor has [ ]A) Low mobility & high resistance B) High mobility & low resistanceC) Low mobility & low resistance D) High mobility & high resistance

30. Dynamic characteristics of CMOS is mainly depends on [ ]A) Capacitive load B) resistive load C) Both A&B D) None

31. Source current indicates the output voltage of CMOS as [ ]A) 1 B) 0 C) Both A&B D) All the above

32. The full forms of the abbreviations TTL and CMOS in reference to logic families are (Gate-09)[ ]A) Triple transistor logic and chip metal oxide semiconductorB) Tri state transistor logic and chip metal oxide semiconductor C) Transistor transistor logic and complementary metal oxide semiconductorD) Tri state transistor logic and complementary metal oxide silicon

33. ON resistance of PMOS is [ ]A) Less B) HIGH C) Zero D) None

34. The gate delay of an NMOS inverter is dominated by charge time rather than discharge time because (Gate-97) [ ]

A) The driver transistor has a larger threshold voltage than the load transistor

B) The driver transistor has a larger leakage currents compared to the transistorC) The load transistor has a smaller W/I ratio compared to the driver transistorD) None of the above

35. Which is an act as a voltage controlled resistance? [ ]A) TTL B) DTL C) RTL D) MOS

36. To make a Schottky transistor the schottky diode is placed in between which terminals [ ]A) Emitter and base B) Collector and base C) Emitter and collector D) None

37. In HC logic levels VOHmin is [ ]A) 1.5V B) 3.5V C) 3.84V D) 0.33V

38. TTL output stage is called [ ]A) Totem pole B) Pushback C) Pullback D) Pull down

39. HCMOS stands for [ ]A) Highest CMOS B) High level CMOS C) High Speed CMOS D) High State CMOS

40. Among the digital IC-families ECL, TTL and CMOS (Gate-89) [ ]A) ECL has least propagation delay B) TTL has the least Fan-outC) CMOS has the biggest noise margin D) TTL has the low power consumption

UNIT-II

THE VHDL HARDWARE DESCRIPTION LANGUAGE

1. Component declaration comes under what type of modeling [ ]A) Structural B) Behavioral C) Data flow D) All

2. Timing analysis is not considered in what type of modeling [ ]A) Data flow B) behavioral C) Structural D) All the above

3. Generate statement is similar as [ ]A) For B) While C) If D) case

4. Which one accepts a number of arguments and returns a result [ ]A) Function B) package C) library D) Both A and B

5. A function can be used in the place of a what [ ]A) Expression B) Statement C) Both A and B D) None

6. Which is a standard library at the beginning of the design [ ]A) IEEE B) Work C) Both A and B D) None

7. A Port is used in the following syntax [ ]A) Architecture B) Entity C) Concurrent statements D) Sequential statements

8. Comments start after which symbol in VHDL [ ]A) -- B) !! C) ## D) @@

9. Which type of models is present in VHDL [ ]A) Data flow B) Behavioral C) Structural D) All the above

10. Package contains the definitions of what [ ]A) Procedures B) Objects C) Functions D) Libraries

11. VHDL stands for [ ]A) Hard ware description language B) very high speed IC HDL C) highest HDL D) None

12. Which one is not a HDL in the following [ ] A) Verilog B) ABEL C) VHDL D) PASCAL

13. Which one is not a mode declaration signal [ ]A) IN B) OUT C) Component D) Buffer

14. VHDL Program structure is a combination of [ ]A) Entity B) architecture C) Both D) None

15. Which of the following is a example of Boolean operators [ ]A) AND B) MOD C) ABS D) REM

16. VHDL support what type of modeling [ ]A) Data flow B) Structural &Behavioral C) Behavioral Only D) Both A and B

17. In VHDL which is a detailed description of the module [ ]A) Entity B) Architecture C) Both D) Process

18. “If then else” VHDL statement used within [ ] A) Process B) select C) assert D) WHILE

19. Signals that can be defined in a package are ……….. Signals [ ]A) Global B) Local C) Both D) None

20. Simulation is a [ ]A) Timing delay B) functional verification C) RTL conversion D) Net list

21. Process statements are used in what type of modeling [ ]A) Structural B) Behavioral C) Data flow D) All

22. A procedure can be used in the place of a [ ]A) Statement B) Object C) Expression D) Function

23. VHDL defines many character strings called---- [ ]A) Reserved words B) Key words C) Both A and B D) None

24. Which signal is an output of the entity, and its value can also be read inside the entity’s architecture[ ]

A) Input B) Output C) Buffer D) In out25. Synthesis means [ ]

A) Net list B) power dissipation amount C) Both A and B D) None26. The type of Integer is defined as the range of integer values including at least range [ ]

A) - 231+1 to + 231-1 B) +231+1 to +231-1 C) - 231+1 to - 231-1 D) + 231+1 to -231-127. VHDL specifies a time delay using the keyword [ ]

A) Loop B) While C) After D) All28. VHDL describe a circuit in terms of flow of data operations on it within the circuit is called [ ]

A) Structural B) Behavioral C) Data flow D) All29. Simulator operator begins at simulation time of [ ]

A) Zero B) One C) Two D) Three30. Begin is used in the following syntax [ ]

A) Architecture B) Entity C) Concurrent statements D) Sequential statements31. A VHDL -----accepts number of arguments and a returns a result. [ ]

A) Function B) Variables C) Packages D) None32 .Which type of port declaration used in VHDL [ ]

A) Module B)Simulation C) Entity D) Architecture32. A VHDL ------- is a place where the VHDL compiler stores information about a particular design project

[ ]A) Package B) Function C) Variable D) Library

33. Which types of models are present in VHDL [ ]A) Data flow B) Behavioral C) Structural D) All the above

34 .Process statements are used in ………..design low [ ]A) Data flow B) Behavioral C) Structural D) All the above

35 .Generic declarations is used in which design flow [ ]A) Data flow B) Behavioral C) Structural D) All the above

36. Which of the following is the fastest adder [ ]A) Half adder B) Full adder C) Carry look ahead adder D) Ripple carry adder

37. In which module inputs & outputs are declared [ ]A) Entity B) Architecture C) Instantiate D) None

38. Which one is to describe the detailed description of the module’s internal behavior [ ]A) Entity B) Signal C) Architecture D) None

39. The reserved words are [ ]A) Entity B) Port C) Is D) all the above

40. Buffer is what type of mode [ ]A) Input B) Output C) Signal D) None

UNIT-IIICombinational Logic Design

1. One of the following is a 3 to 8 decoder [ ]A) 74LS139 B) 74X138 C) 74X129 D) 74X119

2. 74 X 148 outputs are [ ]A) Active low B) Active high C) Buffered D) Inverted

3. Which one is the octal three state Trans receiver IC [ ]A) 74 X 245 B) 74 X 254 C) 74 X 243 D) 74 X 241

4. What is the IC number of 4bit binary adder [ ]A) 74 X 283 B) 74 X 263 C) 74 X 143 D) 74 X 148

5. In VHDL ‘V’ stands for [ ]A) VHSIC B) VIC C) VHS D) Verilog

6. A seven segment decoder has the input code is [ ]A) 4 bit BCD B) 6 bit excess 3 C) 3 bit octal D) 3 bit hex

7.32X1multiplexer implemented by using [ ]A) 74 X 139, four 74 X 151 B) 74 X 136, two 74 X 151C) 74 X 131, four 74 X 155 D) 74 X 130, four 74 X 159

8. Which of the following IC specifies the comparator [ ]A) 74 X 245 B) 74 X 541 C) 74 X 85 D) 74 X 148

9. A 2 bit binary multiplier can be implemented using (Gate-97) [ ] A) 2 input AND gates only B) 2 input XOR and 4-inputs AND gates onlyC) Two 2 input NORs and one XNOR gate D) XOR gates and shift registers

10. Which of the following IC specifies the Full-adder [ ]A) 74 X 999 B) 74 X 99 C) 74 X 199 D) 74 X 289

11. How many 2 to 4 decoders with enable input are needed to construct a 4 to 16 decoder [ ]A) 4 B) 5 C) 6 D) 8

12. Decimal 43 in hexadecimal and BCD number system is [ ]A) B2, 01000011 B)2B, 01000011 C) 2B, 00110100 D) B2,00110100

13. The minimum number of NOR gates required to implement XNOR gate is [ ] A) 4 B) 5 C) 6 D) 7

14. In the logic equation A (A+B1C1+C)+B1(C1+A1+BC)(A+B1C+AC1)=1 if C=A1 then[ ]A) A+B B) A1+B C) A+B1 D) A=1

15. Which of the following IC is 8 input priority encoder [ ]A) 74x283 B) 74X151 C) 74X182 D) 74x148

16. One of the following is 3 to 8 decoder [ ] A) 74X130 B) 74X119 C) 74X36 D) 74X138

17. 2 to 4 decoder is [ ] A) 74X139 B) 74X130 C) 74X129 D) 74X119

18. Which is have 4inputs, 2 bit multiplexer [ ] A) 74 × 541 B) 74 × 148 C) 74 × 153 D) 74 × 151

19. The VHDL code for difference bit in full sub tractor is [ ] A) Diff <= x XOR Y XOR bin; B) diff <= x NAND Y OR bin; C) Diff <= x XNORY XOR bin; D) diff <= x XNORY OR bin;

20. One of the following is OR gate [ ]A) 74X20 B) 74X119 C) 74X36 D) 74X138

21. For 1X32 DEMUX necessary select lines are [ ] A) FIVE B) FOUR C) THREE D) EIGHT

22. Memory element is consists in which circuitry [ ] A) Combinational logic B) Sequential logic C) Both D) None

23. N No. of inputs and 2N No. of outputs logic circuit is [ ] A) Decoder B) Encoder C) Multiplexer D) Demultiplexer

24. Memory present in which circuits [ ]A) Combinational B) Sequential C) Both D) None

25. Which one acts a digital switch [ ]A) Multiplexer B) Demultiplexer C) Buffer D) Encoder

26. Without any additional circuitry, an 8:1 mux can be used to obtain (Gate-03) [ ]A) Some but not all Boolean functions of 3 variablesB) All functions of 3 variables but none of 4 variablesC) All functions of 3 variables and some but not all of 4 variables D) None

27. The most basic 3 state device is a [ ]A) Buffer B) Enable C) Identifier D) Fitter

28. Design of full adder how many no of half adder all require [ ]A) 2 B) 3 C) 4 D) 5

29. The output Y of a 2-bit comparator is logic 1 whenever the 2 bit input A is greater than the 2-bit input B. The no. of͞͞ combinations for which the output logic 1 is (Gate-12) [ ]

A) 4 B) 6 C) 8 D) 1030. In a half-sub tractor circuit with X and Y as inputs, the borrow (M) and difference (N=X-Y)

are given by (Gate-14) [ ]A) M= X xor Y, N=XY B) M= XY, N= X xor YC) M= ͞XY, N= X xor Y D) M=͞XY, N=͞͞X͞ xo͞r ͞Y

31. In Ex-OR gate when A=1 and B=0 the output is [ ]A) 1 B) 0 C) 0 or 1 D) none

32. IC 74* 151 is an [ ]A) 8*1 multiplexer B) 4*1 multiplexer C) 3*1 multiplexer D) 2*1 multiplexer

33. By adding 3 to binary number the resultant code is [ ]A) excess-3 code B) gray code C) BCD code D) binary code

34. Output of sub tractor [ ]A)Sum, Carry B) Borrow, Difference C) Carry, Difference D) none

35. What is IC 74182 [ ]A) Priority B) Carry look ahead C) Full adder D) All the above

36. The logical expression of half adder sum is [ ]A) A EX-OR B B) A+B C) AB D) NOT AB

37. IC 7485 is a [ ]A) 4 bit comparator B) 16 bit comparator C) 8 bit comparator D) 2 bit comparator

38. What are the minimum number of 2 to 1 multiplexer required to generate a 2 input AND gate and a 2 input EX-OR gate? (Gate-09) [ ]A) 1 and 2 B) 1 and 3 C)1 and 1 D)2 and 2

39. The minimum number of 2 to 1 multiplexer required to realize a 4 to 1 multiplexer is(Gate-04) [ ]

A) 1 B) 2 C)3 D)440. For a binary half-subtractor having two inputs A and B , the correct set of logical expressions For the outputs D= (A minus B) and X = barrow are (Gate-99) [ ]

A) D=AB +͞AB , X=͞AB B)D=͞AB +A͞͞͞͞͞B+A͞͞ ͞BC) D=͞AB+A ͞ X=͞AB D)D=AB+͞A͞ ͞B , X=A ͞B

UNIT-IVSEQUENTIAL MACHINE DESIGN PRACTICES:

1. Which mechanism allocates the binary value to the states in order to reduce the cost of the combinational circuits? [ ]

A). State Reduction B). State Minimization C). State Assignment D). State Evaluation 2. Which among the following state machine notations are generated outside the sequential circuits? [ ]

A). Input variables B). Output variables C). State variables D). Excitation variables3.   According to Moore circuit, the output of synchronous sequential circuit depend/s on ______ of flip flop

[ ]A). Past state B). Present state C). Next state D). External inputs

4. Which type of memory elements are used in synchronous sequential circuits? [ ]A). Clocked Flip flops B). Un clocked Flip flops C). Time Delay Elements D). All of the

above5. The bit sequence 0010 is serially entered (right-most bit first) into a 4-bit parallel out shift register that is initially clear. What are the Q outputs after two clock pulses? [ ]

A). 0000 B). 0010 C). 1000 D). 11116. What is a shift register that will accept a parallel input, or a bidirectional serial load and internal shift features, called? [ ]

A). tristate B). End around C). universal D). conversion7. A bidirectional 4-bit shift register is storing the nibble 1101. Its input is HIGH. The nibble 1011 is waiting to be entered on the serial data-input line. After three clock pulses, the shift register is storing ___.[ ]

A). 1101 B). 0111 C).0001 D).11108. Which of the following IC represents 4 bit binary counter [ ]

A) 74x163 B) 74x373 C) 74x174 D) 74x1949. How can parallel data be taken out of a shift register simultaneously? [ ]

A).Use the Q output of the first FF. B). Use the Q output of the last FF.C).Tie all of the Q outputs together. D).Use the Q output of each FF.

10. To operate correctly, starting a ring shift counter requires: [ ]A).clearing all the flip-flops B).presetting one flip-flop and clearing all othersC).clearing one flip-flop and presetting all others D).presetting all the flip-flop

11. What type of register would shit a complete binary number in one bit at a time and shift all the Stored bits out one bit at a time? [ ]A) PIPO B) SISO C) SIPO D) PISO

12. A ripple counter’s speed is limited by the propagation delay of [ ]A) Each flip-flop B) all flip-flop and gates C) only flip-flop only with gates D) only gates

13. In a 6-bit Johnson counter sequence there are a total of how many states, or bit patterns? [ ]A).2 B).6 C).12 D).24

14. The device which changes from serial data to parallel data is [ ]A) Counter B) Multiplexer C) Demultiplexer D) Flip-Flop

15. A sequence of equally spaced timing pulses may be easily generated by which type of counter circuit? [ ]A).ring shift B).clock C).Johnson D).binary

16.  Where do/does the status of memory element in a synchronous sequential circuit get/s affected due to change in input? [ ]A). At an active edge of clock B). At passive edge of clock C). Both A and B D). None of the above20. Race-around condition occurred when the input states are [ ]

A) J=1, K=1 B) J=0, K=1 C) J=0, K=1 D) J=0,K=021. How many 74X85 IC’s are required for built 12bit comparator [ ]

A) Five B) Four C) Three D) Eight22. A switch-tail ring counter is made by using a single D flip-flop. The resulting circuit is a

(Gate-95) [ ]A) SR flip flop B)JK flip flop C)D flip flop D) T flip flop

23. What is the difference between a ring shift counter and a Johnson shift counter? [ ]A).There is no difference. B).A ring is faster.C).The feedback is reversed. D).The Johnson is faster.

24. Synchronous counters are ---- than the ripple counters. (Gate-94) [ ]A) Slower B) Faster C) Less D) None

25. With a 200 kHz clock frequency, eight bits can be serially entered into a shift register in __. [ ]A).4 μs B).40 μs C).400 μs D).40 ms

26. A 4 bit modulo 16 ripple counter uses JK flip flops. If the propagation delay of each FF is 50ns, the maximum clock frequency that can be used is equal to (Gate-90) [ ]

A) 20MHz B) 10 MHz C) 5MHz D) 4MHz27. Group of Flip flop are connected together to form a ------- [ ]

A) Register B) Counter C) Shift register D) None28. Asynchronous counters are [ ]

A) Ripple counter B) binary counter C) mod counter D) shift registers29. Group of registers called [ ]

A) Shift registers B) counters C) flip-flops D) none30. Which register is used to convert data in serial form to parallel form [ ]

A) SIPO B) PIPO C) PISO D) SISO31. Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store the nibble 1100. What will be the 4-bit pattern after the second clock pulse? (Right-most bit first.) [ ]

A).1100 B).0011 C).0000 D).111132. 32. IC 7490 is a [ ]

A) Decode binary counter B) Shift register C) Ring counter D) Modulo counter33. If an 8-bit ring counter has an initial state 10111110, what is the state after the fourth clock pulse?

[ ]A).11101011 B). 00010111 C). 11110000 D). 00000000

34. Johnson counter also called as [ ]A) Twisted ring counter B) Ripple counter C) Mod counter D) None

35. A modulus-12 ring counter requires a minimum of ________. [ ]A).10 flip-flops B).12 flip-flops C).6 flip-flops D).2 flip-flops

37. IC 74*169 is a [ ]A) 4 bit bi-directional syn.Counter B) 4 bit syn. Binary counterC) 4 bit ripple counter D) decode counter

38. The output depends on only present state of the flip flop [ ]

A) Moore circuit B) Mealy circuit C) Sequential circuits D) None39. The output depends on only present state of the flip flop [ ]

A) Universal shift registers B) Shift left register C) Shift right register D) none40. The group of bits 11001 is serially shifted (right-most bit first) into a 5-bit parallel output shift register with an initial state 01110. After three clock pulses, the register contains ________. [ ]

A).01110 B).00001 C).00101 D).00110

UNIT –VDesign Examples & Sequential logic Design

1. Which is specifying the direction of shift, type of shift and amount of shift [ ]A) Barrel shifter B) Carry save shifter C) Sequential shifter D) Group ripple shifter

2. In a floating point encoder the relation between M, E and T is [ ]A) M.2ET B) M.2E + T C) M.E +T D) M.2E+ T

3. In a 16 bit barrel shifter if 4 bits are shifted at a time then the control input that is enabled is [ ]A) S0 B) S1 C) S2 D) S3

4.Which flip-flop is also known as transparent latch [ ]A) D flip-flop B)T flip-flop C)JK flip-flop D) SR flip-flop

5. Race around condition is occurred in [ ]A) D flip-flop B) T flip-flop C) JK flip-flop D) SR flip-flop

6. The difference between the arrival times of the clock at different devices is called [ ]A) Clock delay B) Clock skew C) Both A&B D) none of the above

7. Both AND plane and OR plane are programmable in [ ]A) PLA B) PAL C) Both A&B D) PROM

8. Which of the following IC represents 4 bit binary counter [ ]A) 74x163 B) 74x373 C) 74x174 D) 74x1949. Which of the following IC represents ALU [ ]

A) 74x199 B) 74x181 C) 74x151 D) 74x14310. Find Odd one in the following [ ]A) FPGA B) ASIC C) CPLD D) PLD11. What type of register would shit a complete binary number in one bit at a time and shift all the

Stored bits out one bit at a time? [ ]A) PIPO B) SISO C) SIPO D) PISO

12. A ripple counter’s speed is limited by the propagation delay of [ ]A) Each flip-flop B) all flip-flop and gates C) only flip-flop only with gates D) only gates

13. S - R latch characteristic equation is [ ]A) Q*=S+R|.Q B) Q*=S|+R|.Q|C) Q*=S|+R|.Q D) Q*=S+R|.Q|

14. The device which changes from serial data to parallel data is [ ]A) Counter B) Multiplexer C) Demultiplexer D) Flip-Flop

15. An SR latch is (Gate-95) [ ] A) Combinational Circuit B) Synchronous sequential circuitC) One bit memory element D) One clock delay element

16. One of the following VHDL statements is used for fixed point to floating point conversion [ ]A) If B (8) =1, then M < = B (8 down to 2); E < = “100“; B) If B (10) =1, then M < = B (10 down to 7); E < = “111“; C) If B (9) =1, then M < = B (9 down to 0); E < = “010“; D) If B (6) =1, then M < = B (3 down to 1); E < = “001“;

20. Race-around condition occurred when the input states are [ ]

A) J=1, K=1 B) J=0, K=1 C) J=0, K=1 D) J=0,K=021. How many 74X85 IC’s are required for built 12bit comparator [ ]

A) Five B) Four C) Three D) Eight22. A switch-tail ring counter is made by using a single D flip-flop. The resulting circuit is a

(Gate-95) [ ]A) SR flip flop B)JK flip flop C)D flip flop D) T flip flop

23. How many NAND gates are required for design XOR gate [ ]A) Five B) Four C) Three D) Eight

24. Synchronous counters are ---- than the ripple counters. (Gate-94) [ ]A) Slower B) Faster C) Less D) None

25. Latches are ----- triggered circuits [ ]A) Level B) Edge C) control D) Timing

26. A 4 bit modulo 16 ripple counter uses JK flip flops. If the propagation delay of each FF is 50ns, the maximum clock frequency that can be used is equal to (Gate-90) [ ]

A) 20MHz B) 10 MHz C) 5MHz D) 4MHz27. Group of Flip flop are connected together to form a ------- [ ]

A) Register B) Counter C) Shift register D) None28. Asynchronous counters are [ ]

A) Ripple counter B) binary counter C) mod counter D) shift registers29. Group of registers called [ ]

A) Shift registers B) counters C) flip-flops D) none30. Which register is used to convert data in serial form to parallel form [ ]

A) SIPO B) PIPO C) PISO D) SISO31. All the flip flops are not clocked simultaneously [ ]

A) Synchronous counters B) Asynchronous counters C) Combinational circuits D) None

32. IC 7490 is a [ ]A) Decode binary counter B) Shift register C) Ring counter D) Modulo counter

33. A shift register is constructed with four D flip-flops are called [ ]A) Buffer register B) Counter C) Latch D) None

34. Johnson counter also called as [ ]A) Twisted ring counter B) Ripple counter C) Mod counter D) None

35. The characteristics equation of D flip flop [ ]A) D B) not D C) D + 1 D) (not D)+1

37. IC 74*169 is a [ ]A) 4 bit bi-directional syn.Counter B) 4 bit syn. Binary counterC) 4 bit ripple counter D) decode counter

38. The output depends on only present state of the flip flop [ ]A) Moore circuit B) Mealy circuit C) Sequential circuits D) None

39. The output depends on only present state of the flip flop [ ]A) Universal shift registers B) Shift left register C) Shift right register D) none

40. A 0 to 6 counter consists of 3 flip flops and a combination circuit of 2 input gates. The combination Circuit consists of (Gate-03) [ ]A) One AND gate B) One OR gateC) One AND gate and One OR gate D) Two AND gates