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TRANSCRIPT
Report on FPGA programming in Verilog
Submitted by
Imran AhmedRoll: Sh-965MSc Session: 2014-2015
Department of Electrical and Electronic EngineeringUniversity of Dhaka
Introduction to FPGA
Field-programmable gate arrays (FPGAs) are reprogrammable silicon chips. In contrast to processors that you find in your PC, programming an FPGA rewires the chip itself to implement your functionality rather than run a software application. The FPGA configuration is generally specified using a hardware description language (HDL). FPGAs contain an array of programmable logic blocks, and a hierarchy of reconfigurable interconnects that allow the blocks to be "wired together", like many logic gates that can be inter-wired in different configurations. Logic blocks can be configured to perform complex combinational functions, or merely simple logic gates like AND and XOR. In most FPGAs, logic blocks also include memory elements, which may be simple flip-flops or more complete blocks of memory.
Difference between FPGA and Microcontroller1. Microcontrollers are custom built mini computers in an IC while FPGAs are only
composed of logic blocks that can be rewired electrically2. Microcontrollers consume less power than FPGAs3. FPGAs take a considerably longer time to set-up while there are ready built
microcontrollers being sold for specific uses4. Building devices with FPGAs are more costly than microcontrollers
In our laboratory we used the Altera DE1 board.
Altera DE1 BoardA photograph of the DE1 board is shown in Figure 1. It depicts the layout of the board and indicates the location of the connectors and key components.
Figure 1: The DE1 board
The following hardware is provided on the DE1 board:
Altera Cyclone® II 2C20 FPGA device Altera Serial Configuration device – EPCS4 USB Blaster (on board) for programming and user API control; both JTAG and
Active Serial (AS) programming modes are supported 512-Kbyte SRAM 8-Mbyte SDRAM 4-Mbyte Flash memory SD Card socket 4 pushbutton switches 10 toggle switches 10 red user LEDs 8 reen user LEDs 50-MHz oscillator, 27-MHz oscillator and 24-MHz oscillator for clock sources 24-bit CD-quality audio CODEC with line-in, line-out, and microphone-in jacks VGA DAC (4-bit resistor network) with VGA-out connector RS-232 transceiver and 9-pin connector PS/2 mouse/keyboard connector Two 40-pin Expansion Headers with resistor protection Powered by either a 7.5V DC adapter or a USB cable
In order to use the DE1 board, the user has to be familiar with the Quartus II software. There are three versions based on the design entry method used, namely Verilog, VHDL or schematic entry.
Figure 2: Block Diagram of the DE1 Board
Hardware description languageIn electronics, a hardware description language (HDL) is a specialized computer language used to describe the structure and behavior of electronic circuits, and most commonly, digital logic circuits.
A hardware description language enables a precise, formal description of an electronic circuit that allows for the automated analysis and simulation of an electronic circuit. It also allows for the synthesis of a HDL description into a netlist (a specification of physical electronic components and how they are connected together), which can then be placed and routed to produce the set of masks used to create an integrated circuit.
A hardware description language looks much like a programming language such as C; it is a textual description consisting of expressions, statements and control structures. One important difference between most programming languages and HDLs is that HDLs explicitly include the notion of time.
HDLs form an integral part of electronic design automation (EDA) systems, especially for complex circuits, such as application-specific integrated circuits, microprocessors, and programmable logic devices.
In our laboratory we used Verilog HDL to program our DE1 board.
Verilog HDLVerilog HDL and VHDL (Very high speed ICHardware Description Language) are now
widely accepted industry standard and vendor independent tool for digital system design [6-
9]. Verilog HDL is introduced by Cadence Data Systems, Inc. and later its control is
transferred to a consortium of companies and universities known as open Verilog
international (OVI) whereas VHDL is used primarily by defense contractors. VHDL is
popular in European countries whereas Verilog HDL is widely used in Asia and America.
Currently Verilog is used by the famous IC design companies such as Motorolla, Intel etc.
Verilog HDL is IEEE standard and easier than VHDL. In VHDL, libraries to be used for a
program have to be declared whereas it is not necessary in Verilog HDL programming. It is
also less error prone. It has many pre-defined features very specific to IC design.
There are three types of Verilog coding style as follows:
RTL Verilog Code: Digital circuit can be represented in different ways such as gate level representation, transistor level representation etc. RTL, acronym of Register transfer Level (RTL), is also another type of representation style for digital circuit. The reason why it is named as RTL is that any complex digital system can be partitioned into different modules where each module is basically consists of registers and gates. Information is stored in the registers and specific operation is performed using the information, and then it is transferred among the registers. Figure 1.1 shows the example of RTL code of a 2/1 Mux.
Structural Verilog Code: It describes the components and interconnections present in a design. Electronic Design Automation (EDA) tool compiles and synthesizes the RTL code of a design and produces the netlist of the design in the form of structural code. Table 1.1 shows the example of structural code for a circuit of a 2/1 Mux as shown in Figure 1.2.
Behavioral Verilog code: Behavioral code describes the functionality and behavior of the functional block diagram of a design. It is often used for system level modeling and simulation of a design. Table 1.2 shows an example of behavioral Verilog code (using fork and join). Usually many of the commands in behavioral code are not synthesizable (for example, wait command as shown in Table 1.2) and the code length of a design is much smaller than to write for RTL code of the same design because it is only for simulation purpose.
Apparatus1. Computer2. Software a) Quartus II 12.0sp2 Web Edition b) Quartus II 13.1 Programmer3. Hardware: Cyclone II EP2C20F484C7
Laboratory Exercise 1 (Switches, Lights and Multiplexers)Part 1Simple module that connects the switches (SW9-0) to the red LED lights (LEDR9-0)
AlgorithmStep 1: StartStep 2: LEDR=SWStep 3: Stop
Codemodule part1 (SW,LEDR);
input [9:0] SW;
output [9:0] LEDR;
assign LEDR=SW;
endmodule
Part 2
Implement a four bit 2-to-1 muliplexer.
Theory
Figure: MUX circuit with truth table
Figure: 4 bit 2to1 MUX
AlgorithmStep 1: StartStep 2: M= (~select & X | select & Y)Step 3: Repeat step 2 for all 3 bitsStep 4: Stop
Codemodule part2 (SW, LEDR, LEDG);
input [9:0]SW;
output [9:0]LEDR;
output [3:0] LEDG;
wire Sel;
wire [3:0] X, Y, M;
assign LEDR=SW;
assign X= SW[3:0];
assign Y= SW[7:4];
assign Sel= SW[9];
assign M[0]= (~Sel & X[0])| (Sel & Y[0]);
assign M[1]= (~Sel & X[1])| (Sel & Y[1]);
assign M[2]= (~Sel & X[2])| (Sel & Y[2]);
assign M[3]= (~Sel & X[3])| (Sel & Y[3]);
assign LEDG[3:0]= M;
endmodule
Part 3
Implement a 2-bit 3-to-1 multiplexer.
Theory
Figure: 3 to 1 MUX
Figure: 2 bit 3 to 1 MUX with truth table
AlgorithmStep 1: StartStep 2: m_0= (~S & U)|(S & V)Step 3: M=(~S & m_0)|(S & W)Step 4: Repeat step 2 and 3 for 3 bitsStep 5: Stop
Codemodule part3 (SW, LEDR, LEDG);
input [9:0]SW;
output [9:0]LEDR;
output [1:0]LEDG;
wire m_0, m_1;
wire[1:0] S, U, V, W, M;
assign S[1:0]=SW[9:8];
assign U=SW[1:0];
assign V=SW[3:2];
assign W=SW[5:4];
assign LEDR = SW;
assign m_0 =(~S[0] & U[0]) | (S[0] & V[0]);
assign M[0] =(~S[1] & m_0) | (S[1] & W[0]);
assign m_1 =(~S[0] & U[1]) | (S[0] & V[1]);
assign M[1] =(~S[1] & m_1) | (S[1] & W[1]);
assign LEDG [1:0] = M;
endmodule
Part 4
Implement a circuit that can display four characters on a 7-segment display.
Theory
Figure: A 7-segment decoder
Table: Characters with corresponding inputs
AlgorithmStep 1: StartStep 2: Implement logic according to truth tableStep 3: Logic→HEXStep 4: Stop
Codemodule part4(SW, LEDR, HEX0);
input [1:0]SW;
output[1:0] LEDR;
output[0:6] HEX0;
assign LEDR =SW;
wire [1:0] C;
assign C[1:0]=SW[1:0];
assign HEX0[0]= ~(~C[1] & C[0]);
assign HEX0[1]= C[0];
assign HEX0[2]= C[0];
assign HEX0[3]= C[1];
assign HEX0[4]= C[1];
assign HEX0[5]= ~(~C[1] & C[0]);
assign HEX0[6]= C[1];
endmodule
Part 5
Implement a circuit that can display different 3-letter word on three 7-segment.
Theory
Figure: Displaying multiplexed characters
Table: Rotation of the characters
AlgorithmStep 1: StartStep 2: MUX 3 channelsStep 3: H_Ch→HEX,Step 4: Stop
Codemodule part5 (SW, LEDR, HEX3, HEX2, HEX1, HEX0);
input [9:0] SW;
output [9:0] LEDR;
output [0:6] HEX3, HEX2, HEX1, HEX0;
assign LEDR = SW;
wire [1:0] Ch_Sel, Ch1, Ch2, Ch3, Blank;
wire [1:0] H2_Ch, H1_Ch, H0_Ch;
assign Ch_Sel = SW[9:8];
assign Ch1 = SW[5:4];
assign Ch2 = SW[3:2];
assign Ch3 = SW[1:0];
assign Blank = 2'b11;
mux_2bit_3to1 M2 (Ch_Sel, Ch1, Ch2, Ch3, H2_Ch);
mux_2bit_3to1 M1 (Ch_Sel, Ch2, Ch3, Ch1, H1_Ch);
mux_2bit_3to1 M0 (Ch_Sel, Ch3, Ch1, Ch2, H0_Ch);
char_7seg H3 (Blank, HEX3);
char_7seg H2 (H2_Ch, HEX2);
char_7seg H1 (H1_Ch, HEX1);
char_7seg H0 (H0_Ch, HEX0);
endmodule
module mux_2bit_3to1 (S, U, V, W, M);
input [1:0] S, U, V, W;
output [1:0] M;
wire m_0, m_1;
assign m_0= (~S[0] & U[0])|(S[0] & V[0]);
assign M[0]= (~S[1] & m_0)|(S[1] & W[0]);
assign m_1= (~S[0] & U[1])|(S[0] & V[1]);
assign M[1]= (~S[1] & m_1)|(S[1] & W[1]);
endmodule
module char_7seg (C, Display);
input [1:0] C;
output[0:6] Display;
assign Display [0] = ~(~C[1] & C[0]);
assign Display [1] = C[0];
assign Display [2] = C[0];
assign Display [3] = C[1];
assign Display [4] = C[1];
assign Display [5] = ~(~C[1] & C[0]);
assign Display [6] = C[1];
endmodule
Part 6
Implement a circuit that can display different 3-letter words on the four 7-segment displays.
TheoryDesigning a circuit that will be able to display words with three (or fewer) characters on the four displays, and rotate the displayed word when the switches SW9-8 are toggled. IfthedisplayedwordisdE1, then our circuit should produce the patterns shown in Table 3.
Table: Rotating the word dE1 on eight displays.
AlgorithmStep 1: StartStep 2: MUX 4 channelsStep 3: H_Ch→HEXStep 4: Stop
Codemodule part6 (SW, LEDR, HEX3, HEX2, HEX1, HEX0);
input[9:0] SW;
output[9:0] LEDR;
output [0:6] HEX3, HEX2, HEX1, HEX0;
assign LEDR = SW;
wire[1:0] Ch_Se1, Ch1, Ch2, Ch3, Blank;
wire[1:0] H3_Ch, H2_Ch, H1_Ch, H0_Ch;
assign Ch_Se1 = SW[9:8];
assign Ch1 = SW[5:4];
assign Ch2 = SW[3:2];
assign Ch3 = SW[1:0];
assign Blank = 2'b11;
mux_2bit_4to1 M3 (Ch_Se1, Blank, Ch1, Ch2, Ch3, H3_Ch);
mux_2bit_4to1 M2 (Ch_Se1, Ch1, Ch2, Ch3, Blank, H2_Ch);
mux_2bit_4to1 M1 (Ch_Se1, Ch2, Ch3, Blank, Ch1, H1_Ch);
mux_2bit_4to1 M0 (Ch_Se1, Ch3, Blank, Ch1, Ch2, H0_Ch);
char_7seg H3 (H3_Ch, HEX3);
char_7seg H2 (H2_Ch, HEX2);
char_7seg H1 (H1_Ch, HEX1);
char_7seg H0 (H0_Ch, HEX0);
endmodule
module mux_2bit_4to1 (S, G1, G2, G3, G4, M);
input [1:0] S, G1, G2, G3, G4;
output [1:0] M;
wire [1:2] m_0, m_1;
assign m_0[1]= (~S[0] & G1[0]) | (S[0] & G2[0]);
assign m_0[2]= (~S[0] & G3[0]) | (S[0] & G4[0]);
assign M[0]= (~S[1] & m_0[1]) | (S[1] & m_0[2]);
assign m_1[1]= (~S[0] & G1[1]) | (S[0] & G2[1]);
assign m_1[2]= (~S[0] & G3[1]) | (S[0] & G4[1]);
assign M[1]= (~S[1] & m_1[1]) | (S[1] & m_1[2]);
endmodule
module char_7seg (C, Display);
input [1:0] C;
output [0:6] Display;
assign Display [0] = ~(~C[1] & C[0]);
assign Display [1] = C[0];
assign Display [2] = C[0];
assign Display [3] = C[1];
assign Display [4] = C[1];
assign Display [5] = ~(~C[1] & C[0]);
assign Display [6] = C[1];
endmodule
Laboratory Exercise 2 (Numbers and Displays)
In this report details of six experiments have been highlighted. Their algorithms of the corresponding experiments, coding, logic circuits and procedures are given in brief. The purpose of all these experiments is to design combinational circuits that can perform binary to decimal number conversion and binary-coded-decimal (BCD) addition.
Part 1Designing a circuit that should be able to display the digits from 0 to 9 and should treat the valuations 1010 to 1111 as don’t-cares.
AlgorithmStep 1: StartStep 2: BCD to 7seg logic→HEXStep 3: Stop
Codemodule part1 (SW, LEDR, HEX1, HEX0);
input [7:0] SW;
output [7:0] LEDR;
output [0:6] HEX1, HEX0;
assign LEDR = SW;
bcd7seg digit1 (SW[7:4], HEX1);
bcd7seg digit0 (SW[3:0], HEX2);
endmodule
module bcd7seg (B, H);
input [3:0] B;
output [0:6] H;
wire [0:6] H;
assign H[0] = (~B[3] & B[2] & ~B[1] & ~B[0])| (~B[3] & ~B[2] & ~B[1] & ~B[0]);
assign H[1] = (~B[2] & B[1] & ~B[0])| (~B[2] & ~B[1] & ~B[0]);
assign H[2] = (~B[2] & B[1] & ~B[0]);
assign H[3] = (~B[3] & B[2] & ~B[1] & ~B[0])| (~B[3] & ~B[2] & ~B[1] & ~B[0]) |(~B[3] & ~B[2] & ~B[1] & ~B[0]) ;
assign H[4] = (~B[1] & ~B[0])| (B[3] & ~B[0])| (~B[3] & ~B[2] & B[1]);
assign H[5] = (~B[1] & ~B[0])| (B[2] & ~B[1])| (~B[3] & ~B[2] & B[0]);
assign H[6] = (~B[2] & ~B[1]& ~B[0])| (~B[3] & ~B[2] & B[1]);
endmodule
Part 2
Designing a circuit that converts a four bit binary number into its two-digit decimal equivalent.
AlgorithmStep 1: StartStep 2: BCD to 7seg logic→HEXStep 3: Stop
Codemodule part2 (SW, HEX1, HEX0);
input [3:0] SW;
output [0:6] HEX1, HEX0;
wire [3:0] V, M;
wire [2:0] A;
wire z;
assign V = SW;
assign z= (V[3] & V[2]) | (V[3] & V[1]);
assign A[2] = V[2] & V[1];
assign A[1] = V[2] & ~V[1];
assign A[0] = (V[1] & V[0])| (V[2] & V[0]);
assign M[3] = ~z & V[3];
assign M[2] = (~z & V[2]) | (z & A[2]);
assign M[1] = (~z & V[1]) | (z & A[1]);
assign M[0] = (~z & V[0]) | (z & A[0]);
bcd7seg U1 (M , HEX0);
assign HEX1= {1'b1 , ~z, ~z, 4'b1111};
endmodule
module bcd7seg (B, H);
input [3:0] B;
output [0:6] H;
wire [0:6] H;
assign H[0] = (~B[3] & B[2] & ~B[1] & ~B[0])|(~B[3] & ~B[2] & ~B[1] & B[0]);
assign H[1] = (B[2] & ~B[1] & B[0])|(B[2] & B[1] & ~B[0]);
assign H[2] = (~B[2] & B[1] & ~B[0]);
assign H[3] = (~B[3] & ~B[2] & ~B[1] & B[0])|(~B[3] & B[2] & ~B[1] & ~B[0])|(~B[3] & B[2] & B[1] & B[0]);
assign H[4] = (~B[1] & B[0])|(~B[3] & B[0])|(~B[3] & B[2] & ~B[1]);
assign H[5] = (B[1] & B[0])|(~B[2] & B[1])|(~B[3] & ~B[2] & B[0]);
assign H[6] = (B[2] & B[1] & B[0])|(~B[3] & ~B[2]& ~B[1]);
endmodule
Part 3
Designing a four-bit ripple-carry adder (full adder)
Theory
Figure: Full adder circuit
Figure: Four-bit ripple-carry adder circuit with truth table
AlgorithmStep 1: StartStep 2: s=a xor b xor cStep 3: c=( ~a_xor_b & b) | (a_xor_b & ci);Step 4: Repeat step 2 and 3 for 3 more bitsStep 5: Stop
Codemodule part3 (SW, LEDR, LEDG);
input [8:0] SW;
output [8:0] LEDR;
output [4:0] LEDG;
wire [3:0] A, B, S;
wire [4:0] C;
assign A = SW[7:4];
assign B = SW[3:0];
assign C[0] = SW[8];
fa bit0 (A[0] , B[0] , C[0] , S[0] , C[1]);
fa bit1 (A[1] , B[1] , C[1] , S[1] , C[2]);
fa bit2 (A[2] , B[2] , C[2] , S[2] , C[3]);
fa bit3 (A[3] , B[3] , C[3] , S[3] , C[4]);
assign LEDR = SW;
assign LEDG = {C[4], S};
endmodule
module fa (a, b, ci, s, co);
input a, b, ci;
output s, co;
wire a_xor_b;
assign a_xor_b = a ^ b;
assign s = a_xor_b ^ ci;
assign co = ( ~a_xor_b & b) | (a_xor_b & ci);
endmodule
Part 4
Designing a circuit that adds the two BCD digitsusing simple assign statements and ripple-carry adder algorithm.
Codemodule part4 (SW, LEDR, LEDG, HEX3, HEX2, HEX1, HEX0);
input [8:0] SW;
output [8:0] LEDR;
output [7:0] LEDG;
output [0:6] HEX3, HEX2, HEX1, HEX0;
wire [3:0] A, B, S;
wire Cin;
wire [4:1] C;
wire [3:0] S0;
wire [3:0] S0_M;
wire S1;
assign A = SW [7:4];
assign B = SW [3:0];
assign Cin = SW[8];
assign LEDR = SW;
fa bit0 (A[0] , B[0] , Cin, S[0], C[1]);
fa bit1 (A[1] , B[1] , C[1], S[0], C[2]);
fa bit2 (A[2] , B[2] , C[2], S[0], C[3]);
fa bit3 (A[3] , B[3] , C[3], S[0], C[4]);
assign LEDG [4:0] = {C[4], S};
bcd7seg H_3 (A, HEX3);
bcd7seg H_2 (B, HEX2);
assign LEDG[7] = (A[3] & A[2]) | (A[3] & A[1]) | (B[3] & B[2]) | (B[3] & B[1]);
assign LEDG [6:5] = 2'b00;
bcd_decimal BCD_S (S, S1, S0);
assign S0_M[3] = (~C[4] & S0[3]) | ( C[4] & S0[1]);
assign S0_M[2] = (~C[4] & S0[2]) | ( C[4] & ~S0[1]);
assign S0_M[1] = (~C[4] & S0[1]) | ( C[4] & ~S0[1]);
assign S0_M[0] = S0[0];
bcd7seg H_0 (S0_M, HEX0);
endmodule
module fa (a, b, ci, s, co);
input a, b, ci;
output s, co;
wire a_xor_b;
assign a_xor_b = a ^ b;
assign s = a_xor_b ^ ci;
assign co =(~a_xor_b & b) | (a_xor_b & ci);
endmodule
module bcd_decimal (V, z, M);
input [3:0] V;
output z,
output [3:0] M;
wire [2:0] A;
assign z = ( V[3] & V[2]) | (V[3] & V[1]);
assign A[2] = V[2] & V[1];
assign A[1] = V[2] & ~V[1];
assign A[0] = (V[1] & V[0]) | (V[2] & V[0]);
assign M[3] = ~z & V[3];
assign M[2] = (~z & V[2]) | ( z & A[2]);
assign M[1] = (~z & V[1]) | ( z & A[1]);
assign M[0] = (~z & V[0]) | ( z & A[0]);
endmodule
module bcd7seg (B, H);
input [3:0] B;
output [0:6] H;
wire [0:6] H;
assign H[0] = (~B[3] & B[2] & ~B[1] & ~B[0]) | (~B[3] & ~B[2] & ~B[1] & B[0]);
assign H[1] = (B[2] & ~B[1] & B[0]) | (B[2] & B[1] & ~B[0]);
assign H[2] = (~B[2] & B[1] & ~B[0]);
assign H[3] = (~B[3] & ~B[2] & ~B[1] & B[0]) | (~B[3] & B[2] & ~B[1] & ~B[0]) | (~B[3] & B[2] & B[1] & B[0]);
assign H[4] = (~B[1] & B[0]) | (~B[3] & B[0]) | (~B[3] & ~B[2] & ~B[1]);
assign H[5] = (B[1] & B[0]) | (~B[2] & B[1]) | (~B[3] & ~B[2] & B[0]);
assign H[6] = (B[2] & B[1] & B[0]) | (~B[3] & ~B[2] & ~B[1]);
endmodule
Part 5Designing a circuit that adds the two BCD digits using if-else statements along with the Verilog >, + and – operators.
AlgorithmStep 1: StartStep 2: T0 = A+B+C0Step 3: If (T0>9) then Z0 = 10; C1 = 1;Step 4: Else Z0 = 0; c1 = 0;Step 5: S0 = T0 − Z0;Step 6: S1=c1Step 7: Stop
Codemodule part5 (SW, HEX3, HEX2, HEX1, HEX0);
input [8:0] SW;
output [0:6] HEX3, HEX2, HEX1, HEX0;
wire [3:0] A, B;
wire Cin;
assign A = SW[7:4];
assign B = SW[3:0];
assign Cin =SW[8];
wire [4:0] S0;
wire S1;
reg C1;
wire [4:0] T0;
reg [4:0] Z0;
assign T0 = {1'b0,A} + {1'b0,B} + Cin;
always @ (T0)
begin
if (T0 > 5'd9)
begin
Z0 =5'd10;
C1 =1'b1;
end
else
begin
Z0= 5'd0;
C1 = 1'b0;
end
end
assign S0 = T0 - Z0;
assign S1 = C1;
bcd7seg digit3 (A, HEX3);
bcd7seg digit2 (B, HEX2);
bcd7seg digit1 ({3'b000,S1}, HEX1);
bcd7seg digit0 (S0[3:0], HEX0);
endmodule
module bcd7seg (bcd, display);
input [3:0] bcd;
output [0:6] display;
reg [0:6] display;
always @ (bcd)
case (bcd)
4'h0: display = 7'b0000001;
4'h1: display = 7'b0101111;
4'h2: display = 7'b0010010;
4'h3: display = 7'b0000110;
4'h4: display = 7'b0001100;
4'h5: display = 7'b0100100;
4'h6: display = 7'b0100000;
4'h7: display = 7'b0001111;
4'h8: display = 7'b0000000;
4'h9: display = 7'b0000100;
default: display = 7'b1111111;
endcase
endmodule
Part 5 2’s ComplementDesigning a circuit that adds the two BCD digits using if-else statements along with the Verilog >, + and – operators.
AlgorithmStep 1: StartStep 2: T0 = A+B+C0Step 3: If (T0>9) then Z0 = 6; C1 = 1;Step 4: Else Z0 = 0; c1 = 0;Step 5: S0 = T0 +Z0;Step 6: S1=c1Step 7: Stop
Codemodule part5 (SW, HEX3, HEX2, HEX1, HEX0);
input [8:0] SW;
output [0:6] HEX3, HEX2, HEX1, HEX0;
wire [3:0] A, B;
wire Cin;
assign A= SW[7:4];
assign B= SW[3:0];
assign Cin = SW[8];
wire [3:0] S0;
wire S1;
reg C1;
wire [4:0] T0;
reg [3:0] Z0;
assign T0 ={1'b0,A} + {1'b0,B} + Cin;
always @ (T0)
begin
if (T0 > 5'd9)
begin
Z0 = 4'd6;
C1 = 1'b1;
end
else
begin
Z0 = 4'd0;
C1 = 1'b0;
end
end
assign S0 = T0[3:0] + Z0;
assign S1 = C1;
bcd7seg digit3 (A, HEX3);
bcd7seg digit2 (B, HEX2);
bcd7seg digit1 ({3'b000, S1}, HEX1);
bcd7seg digit0 (S0, HEX0);
endmodule
module bcd7seg (bcd, display);
input [3:0] bcd;
output [0:6] display;
reg [0:6] display;
always @ (bcd)
case (bcd)
4'h0: display = 7'b0000001;
4'h1: display = 7'b1001111;
4'h2: display = 7'b0010010;
4'h3: display = 7'b0000110;
4'h4: display = 7'b1001100;
4'h5: display = 7'b0100100;
4'h6: display = 7'b0100000;
4'h7: display = 7'b0001111;
4'h8: display = 7'b0000000;
4'h9: display = 7'b0000100;
default: display = 7'b1111111;
endcase
endmodule
Part6Designing a combinational circuit that converts a 6-bit binary number into a 2-digit decimal number represented in the BCD form.
Codemodule part6 (SW, HEX3, HEX2, HEX1, HEX0);
input [5:0] SW;
output [0:6] HEX3, HEX2, HEX1, HEX0;
reg [5:0] bcd_1;
reg [3:0] bcd_h;
wire [5:0] bin6;
assign bin6 =SW;
always @ (bin6)
begin
if (bin6 < 10)
begin
bcd_h = 4'h0;
bcd_1 =bin6;
end
else
if (bin6 < 20)
begin
bcd_h =4'h1;
bcd_1 = bin6 - 6'd10;
end
else
if (bin6 < 30)
begin
bcd_h =4'h2;
bcd_1 = bin6 - 6'd20;
end
else
if (bin6 < 40)
begin
bcd_h =4'h3;
bcd_1 = bin6 - 6'd30;
end
else
if (bin6 < 50)
begin
bcd_h =4'h4;
bcd_1 = bin6 - 6'd40;
end
else
if (bin6 < 60)
begin
bcd_h =4'h5;
bcd_1 = bin6 - 6'd50;
end
else
begin
bcd_h =4'h6;
bcd_1 =bin6 - 6'd60;
end
end
bcd7seg digit1 (bcd_h, HEX1);
bcd7seg digit0 (bcd_1 [3:0], HEX0);
bcd7seg digit3 (4'hF, HEX3);
bcd7seg digit2 (4'hF, HEX2);
endmodule
module bcd7seg (bcd, display);
input [3:0] bcd;
output [0:6] display;
reg [0:6] display;
always @ (bcd)
case (bcd)
4'h0: display = 7'b0000001;
4'h1: display = 7'b1001111;
4'h2: display = 7'b0010010;
4'h3: display = 7'b0000110;
4'h4: display = 7'b1001100;
4'h5: display = 7'b0100100;
4'h6: display = 7'b0100000;
4'h7: display = 7'b0001111;
4'h8: display = 7'b0000000;
4'h9: display = 7'b0000100;
default: display = 7'b1111111;
endcase
endmodule