week 1 - chapter 1 (part i)

Upload: hidayah-hadi

Post on 14-Apr-2018

221 views

Category:

Documents


0 download

TRANSCRIPT

  • 7/27/2019 Week 1 - Chapter 1 (Part I)

    1/43

    Analogue Electronics Circuit II

    EKT 214/4

    Chapter 1

    Operational Amplifier

    1

    Semester 2 2010/11

    By: Norizan Binti Mohamed Nawawi

  • 7/27/2019 Week 1 - Chapter 1 (Part I)

    2/43

    1.0 Operational Amplifier

    1.1 Introduction 1.2 Ideal Op-Amp 1.3 Op-amp Input Modes 1.4 Op-amp Parameters 1.5 Operation

    Single-mode Differential-mode Common-mode operation

    1.6 Op-Amps Basics 1.7 Practical Op Amp Circuits 1.8 Op Amp Datasheet

    2

  • 7/27/2019 Week 1 - Chapter 1 (Part I)

    3/43

    1.1 Introduction

    3

    Typical IC packages

    IC packages placed on circuit board

  • 7/27/2019 Week 1 - Chapter 1 (Part I)

    4/43

    1.1 Introduction

    The operational amplifier or op-amp is a circuit ofcomponents integrated into one chip.

    A typical op-amp is powered by two dc voltages and has oneinverting(-) input, one non-inverting input (+) and oneoutput.

    Op-amps are used to model the basic mathematical

    operations ; addition, subtraction, integration anddifferentiation in electronic analog computers.

    Other operations include buffering and amplification of DCand AC signals.

    4

    Definition

  • 7/27/2019 Week 1 - Chapter 1 (Part I)

    5/43

    1.1 Introduction

    5

    Op-amp schematic symbol One Output Terminal

    Two Input Terminals

    Inverting input Non-inverting input

    Two Power Supply (PS)

    +V : Positive PS

    -V : Negative PS

  • 7/27/2019 Week 1 - Chapter 1 (Part I)

    6/43

    1.1 Introduction

    6

    Applications of Op-Amp

    To provide voltage amplitude changes

    (amplitude and polarity)

    Comparators

    Oscillators

    Filters Sensors

    Instrumentation amplifiers

  • 7/27/2019 Week 1 - Chapter 1 (Part I)

    7/43

    1.1 Introduction Stages of an op-amp

    7

    INPUT

    STAGE

    OUTPUT

    STAGE

    GAIN

    STAGE

  • 7/27/2019 Week 1 - Chapter 1 (Part I)

    8/43

    1.1 Introduction Typical op-amp packages

    8

  • 7/27/2019 Week 1 - Chapter 1 (Part I)

    9/43

    1.1 Introduction The 741 op-amp

    9

    Literally a black boxReal op-amp : 741

  • 7/27/2019 Week 1 - Chapter 1 (Part I)

    10/43

    1.2 Ideal Op-Amp

    10

    Ideal Op-AmpPractical Op-Amp

  • 7/27/2019 Week 1 - Chapter 1 (Part I)

    11/43

    1.2 Ideal Op-Amp

    Infinite input impedance

    Zero output impedance

    Infinite open-loop gain

    Infinite bandwidth

    Zero noise contribution

    Zero DC output offset

    11

    Ideal Op-Amp Practical Op-Amp

    Input impedance 500k-2M

    Output impedance 20-100

    Open-loop gain (20k to 200k)

    Bandwidth limited (a few kHz)

    Has noise contribution

    Non-zero DC output offset

    Properties

  • 7/27/2019 Week 1 - Chapter 1 (Part I)

    12/43

    i

    i

    i

    I

    VZ

    12

    Infinite Input Impedance

    Input impedance is measured across the input

    terminals.

    It is the Thevenin resistance of the internal connection

    between the two input terminals. Input impedance is the ratio of input voltage to input

    current.

    When Zi is infinite, the input current is zero.

    The op amp will neither supply current to a circuit nor

    will it accept current from any external circuit.

    In real op-amp, the impedance is 500k

    to 2M

    1.2 Ideal Op-Amp

  • 7/27/2019 Week 1 - Chapter 1 (Part I)

    13/43

    13

    Zero Output Impedance

    Looking back into the output terminal, we see it as avoltage source with an internal resistance.

    The internal resistance of the op-amp is the outputimpedance of op-amp

    This internal resistance is in series with the load, reducingthe output voltage available to the load

    Real op-amps have output impedance in the range of 20-100 .

    1.2 Ideal Op-Amp

  • 7/27/2019 Week 1 - Chapter 1 (Part I)

    14/43

    Infinite Open-Loop Gain

    Open-Loop Gain, A is the gain of the op-ampwithout feedback.

    In the ideal op-amp, A is infinite

    In real op-amp, A is 20k to 200k

    invout VAV

    14

    1.2 Ideal Op-Amp

  • 7/27/2019 Week 1 - Chapter 1 (Part I)

    15/43

    15

    Infinite Bandwidth

    The ideal op-amp will amplify all signals from DC to the

    highest AC frequencies

    In real op-amps, the bandwidth is rather limited This limitation is specified by the Gain-Bandwidth product,

    which is equal to the frequency where the amplifier gainbecomes unity

    Some op-amps, such as 741 family, have very limitedbandwidth, up to a few kHz only

    1.2 Ideal Op-Amp

  • 7/27/2019 Week 1 - Chapter 1 (Part I)

    16/43

    16

    Zero Noise Contribution

    in an ideal op amp, all noise voltages produced

    are external to the op amp. Thus any noise in theoutput signal must have been in the input signal aswell.

    the ideal op amp contributes nothing extra to theoutput noise.

    In real op-amp, there is noise due to the internalcircuitry of the op-amp that contributes to theoutput noise

    1.2 Ideal Op-Amp

  • 7/27/2019 Week 1 - Chapter 1 (Part I)

    17/43

    17

    Zero Output Offset

    The output offset voltage of any amplifier is the outputvoltage that exists when it should be zero.

    The voltage amplifier sees zero input voltage when bothinputs are grounded. This connection should produce azero output voltage.

    If the output is not zero then there is said to be anoutput voltage present.

    In the ideal op amp this offset voltage is zero volts, butin practical op amps the output offset voltage is nonzero(a few miliVolts).

    1.2 Ideal Op-Amp

  • 7/27/2019 Week 1 - Chapter 1 (Part I)

    18/43

    18

    Both Differential Inputs Stick Together

    this means that a voltage applied to one inverting

    inputs also appears at the other non-inverting inputs.

    If we apply a voltage to the inverting input and thenconnect a voltmeter between the non-inverting inputand the power supply common, then the voltmeter willread the same potential on non-inverting as on theinverting input.

    1.2 Ideal Op-Amp

  • 7/27/2019 Week 1 - Chapter 1 (Part I)

    19/43

    1.3 Op-Amp Input Modes Single-Ended Input Mode

    Input signal is connected to ONE input and the other input isgrounded.

    19

    Non- Inverting Mode

    input signal at +ve terminal

    output same polarity as

    the applied input signal

    Inverting Mode

    input signal atve terminal

    output opposite in phase

    to the applied input signal

  • 7/27/2019 Week 1 - Chapter 1 (Part I)

    20/43

    1.3 Op-Amp Input Modes Differential Input Mode

    TWO out-of-phase signals are applied with the difference ofthe two amplified is produced at the output.

    21 inind

    ddout

    VVV

    VAV

    20

  • 7/27/2019 Week 1 - Chapter 1 (Part I)

    21/43

    1.3 Op-Amp Input Modes Common Mode Input

    Two signals of same phase, frequency, and amplitude are applied tothe inputs which results in no output (signals cancel). But, inpractical, a small output signal will result.

    This is called common-mode rejection. This type of mode is usedfor removal of unwanted noise signals.

    21

  • 7/27/2019 Week 1 - Chapter 1 (Part I)

    22/43

    1.4 Op-Amp Parameters COMMON-MODE REJECTION (CMRR) COMMON-MODE INPUT VOLTAGE

    INPUT OFFSET VOLTAGE

    INPUT BIAS CURRENT

    INPUT IMPEDANCE

    INPUT OFFSET CURRENT

    OUTPUT IMPEDANCE

    SLEW RATE 22

  • 7/27/2019 Week 1 - Chapter 1 (Part I)

    23/43

    1.4 Op-Amp Parameters Common-Mode Rejection Ratio (CMRR)

    The ability of amplifier to reject the common-mode signals(unwanted signals) while amplifying the differential signal(desired signal)

    Ratio of open-loop gain,Aolto common-mode gain,Acm The open-loop gain is a datasheet value

    cm

    ol

    A

    ACMRR

    cm

    ol

    A

    ACMRR log20

    23

    The higher the CMRR, the better, in which the open-loop gainis high and common-mode gain is low.

    CMRR is usually expressed in dB & decreases withfrequency

  • 7/27/2019 Week 1 - Chapter 1 (Part I)

    24/43

    1.4 Op-Amp Parameters Common-Mode Input Voltage

    The range of input voltages which, when applied to both inputs,will not cause clipping or other output distortion.

    24

    Input Offset Voltage

    Ideally, output of an op-amp is 0 Volt if the input is 0 Volt.

    Realistically, a small dc voltage will appear at the output whenno input voltage is applied.

    Thus, differential dc voltage is required between the inputs toforce the output to zero volts.

    This is called the Input Offset Voltage, Vos. Range between 2mV or less.

  • 7/27/2019 Week 1 - Chapter 1 (Part I)

    25/43

    1.4 Op-Amp Parameters Input Bias Current

    Ideally should be zero

    The dc current required by the inputs of the amplifier to

    properly operate the first stage. Is the average of both input currents

    25

  • 7/27/2019 Week 1 - Chapter 1 (Part I)

    26/43

    1.4 Op-Amp Parameters Input Impedance

    Is the total resistance between the inverting and non-invertinginputs.

    Differential input impedance : total resistance between theinverting and non-inverting inputs

    Common-mode input impedance: total resistance betweeneach input and ground

    26

  • 7/27/2019 Week 1 - Chapter 1 (Part I)

    27/43

    1.4 Op-Amp Parameters Input Offset Current

    Is the difference of input bias currents

    21 IIIos

    27

    inininos RIIRIRIV 2121

    inosos RIV

    inosverrorout RIAV )(

    Input offset current Offset voltage

    Thus, error

  • 7/27/2019 Week 1 - Chapter 1 (Part I)

    28/43

    1.4 Op-Amp Parameters Output Impedance

    Ideally should be zero

    Is the resistance viewed from the output terminal of the op-amp. In reality, it is non-zero.

    28

  • 7/27/2019 Week 1 - Chapter 1 (Part I)

    29/43

    1.4 Op-Amp Parameters Slew Rate

    Is the maximum rate of change of the output voltage in responseto a step input voltage.

    t

    V

    SlewRateout

    29)(where maxmax VVVout

  • 7/27/2019 Week 1 - Chapter 1 (Part I)

    30/43

    1.4 Op-Amp Parameters Slew Rate

    Its a measure of how fast the output can follow the input signal.

    30

  • 7/27/2019 Week 1 - Chapter 1 (Part I)

    31/43

    1.4 Op-Amp Parameters Example

    Determine the slew rate:

    t

    VSlewRate out

    31

    sVs

    VVSlewRate

    /181

    )9(9

  • 7/27/2019 Week 1 - Chapter 1 (Part I)

    32/43

    1.5 Operation

    Types of Op-amp Operation

    32

    Differential Amplifier Circuit

    If an input signal is applied to either input with the other input is

    connected to ground, the operation is referred to as single-

    ended.

    If two opposite-polarity input signals are applied, the operation is

    referred to as double-ended.

    If the same input is applied to both inputs, the operation is called

    common-mode.

  • 7/27/2019 Week 1 - Chapter 1 (Part I)

    33/43

    1.5 Operation

    Basic amplifier circuit 33

    Differential Amplifier Circuit

  • 7/27/2019 Week 1 - Chapter 1 (Part I)

    34/43

    1.5 OperationDC bias of differential amplifier circuit

    0)( EEEEBE VRIV

    E

    BEEE

    E R

    VV

    I

    34

    Differential Amplifier Circuit

    DC ANALYSIS

    0since2

    21 BE

    CC VI

    II

    C

    E

    CCCCCCCCRIVRIVVV

    221

  • 7/27/2019 Week 1 - Chapter 1 (Part I)

    35/43

    1.5 OperationExample : Differential Amplifier Circuits

    35

    Calculate the dc voltages and currents

  • 7/27/2019 Week 1 - Chapter 1 (Part I)

    36/43

    1.5 OperationExample

    36

    E

    BEEEE

    R

    VVI

    Differential Amplifier Circuit

    Solution

    mAmI

    II ECC 25.12

    5.2

    221

    CCCCCRIVV

    mAkVVIE 5.2

    3.37.09

    VkmVVC 1.4)9.3)(25.1(9

  • 7/27/2019 Week 1 - Chapter 1 (Part I)

    37/43

    1.5 Operation

    37

    Differential Amplifier Circuit

    Connection to calculate : Av1 = Vo1 / Vi1

    AC ANALYSIS Single-Ended

  • 7/27/2019 Week 1 - Chapter 1 (Part I)

    38/43

    1.5 Operation

    38

    Differential Amplifier Circuit

    AC ANALYSIS Single-Ended

    AC equivalent of differential amplifier circuit

    B

    E

    C

  • 7/27/2019 Week 1 - Chapter 1 (Part I)

    39/43

    1.5 Operation

    Scan figure 10.11 & 10.15

    ibibi rIrIV 1

    21

    39

    Differential Amplifier Circuit

    AC Analysis - Single ended

    i

    i

    b r

    V

    I 2

    1

    bbb III 21iii rrr

    21

    KVL

    i

    i

    bcr

    VII

    2

    1

    1

    1

    22i

    e

    c

    i

    ci

    cco Vr

    R

    r

    RVRIV

    e

    c

    i

    ov

    r

    R

    V

    VA

    21

    Partial circuit for calculating Ib

    Hence

    :Note

    ie

    CQ

    Ti

    rr

    I

    Vrr

  • 7/27/2019 Week 1 - Chapter 1 (Part I)

    40/43

    1.5 Operation

    7521

    AI

    I E

    C

    5.962

    VkAV 5.4)47)(5.96(9 2690965.0

    26

    CQ

    TeI

    Vr

    40

    Differential Amplifier Circuit

    Example

    krrii 2021

    Ak

    VV

    R

    VVI

    E

    EEE 193

    43

    7.097.0

    ccccc RIVV

    4.87)269(2

    47

    2

    k

    r

    RA

    e

    cv

    Calculate the single-ended output

    voltage Vo1

    Solution

    VkVc 5.4)47)(5.96(9

    VmVAV ivo 175.0)2)(4.87(1

    mV26TV

  • 7/27/2019 Week 1 - Chapter 1 (Part I)

    41/43

    1.5 Operation

    i

    c

    d

    od

    r

    R

    V

    VA

    2

    21where iid VVV

    41

    Differential Amplifier Circuit

    AC Analysis - Double ended

    A similar analysis can be used to show that for the condition of

    signals applied to both inputs, the differential voltage gain

    magnitude is

  • 7/27/2019 Week 1 - Chapter 1 (Part I)

    42/43

    1.5 Operation

    42

    Differential Amplifier Circuit

    AC Analysis - Common-mode

    Common-mode connection

  • 7/27/2019 Week 1 - Chapter 1 (Part I)

    43/43

    1.5 Operation

    iVI

    g,Rearrangin

    co

    v

    RVA

    Differential Amplifier Circuit

    AC Analysis - Common-mode

    i

    Ebib

    r

    RIVI

    )1(2

    Ei

    ci

    cbccoRr

    RVRIRIV

    )1(2

    1