week 1 intro to interfacing tech

8/4/2019 Week 1 Intro to Interfacing Tech

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DEFINITION AND COMPONENTSOF INTERFACE

CLASSIFICATION OF DATA

TRANSFER SCHEMES: PROGRAM CONTROLLED TRANSFER

INTERRUPT DRIVEN TRANSFER

PERIPHERAL CONTROL TRANSFER

CHAPTER 1Introduction to Interfacing

Techniques &Data Transfer Schemes


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Interfacing

Why? microcomputer revolution will continue into the future

many will be required to specify and integratemicroprocessors into products or systems in their own

disciplines

well-designed flexible interfaces will be required to ensurecompatibility with other equipments and to extend designoptions

interfaces are the last items to be seriously considered in therace of new technology

it deals with the systematic study of microprocessorinterfaces and their applications in many diversified fields


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In this subject students learnhow to interface

microprocessors, and hencemicrocomputers and other

related equipments, to externaldigital or analog devices.


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P

progress has advanced at a pace perhaps unparallelin scientific history since its introduction in 1971

there have been four generations of microprocessors

the number of devices per chip has increased by afactor of 2000, the clock frequency by a factor of1000

the overall throughput of the microprocessor hasincreased by hundred or several hundreds ofmagnitudes


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Developing a microprocessor (P)-based systemrepresents one of the most difficult tasks that canconfront an engineer. Advances in microprocessorarchitectures and capabilities are forcing changes indevelopment systems and the ways in which theydevelop microcode instructions. Also, all Parchitectures are not created equal when it comes to

providing designers with the tools they need foreffective systems resource management.


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Therefore, a well designedflexible interfaces will berequired to ensure

compatibility and extenddesign options.


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Definitions:

Microprocessor - The central unit of a microcomputer thatcontains logical elements for manipulating data and performingarithmetic or logical operations. A single chip may contain RAM,ROM, and PROM memories, clocks, and interfaces for memory andI/O device.

Microprogramming- A method for controlling the operation ofthe CPU in which each complete instruction starts the execution of asequence of instructions, called microinstructions, which are at amore elementary level.

Multiprocessor- As defined by ANSI, it is a computer employingtwo or more processing units under integrated control. Althoughthis definition may be correct, it is not complete enough to be toohelpful.There are other important features that include both hardware andsoftware. A multiprocessor will be defined as a system with: a) two ,or more processing units, b)shared memory, and c) shared I/0.


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Interface Definitions

Interface

a shared boundary between system elements defined bycommon physical interconnection characteristics, signalcharacteristics, and meanings of interchanged signals.

is a tool and concept that refers to a point of interactionbetween components, and is applicable at the level ofboth hardware and software.

allows a component to function independently whileusing interfaces to communicate with other componentsvia an input/output system and an associated protocol.


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Cont

Interface Device

A device that meets the interface specifications on one

side of an interface.

The term is usually applied to a device through which asystem or equipment works to meet interfacespecifications.


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Interface Specification

a set of technical requirements that must be met at aninterface.

Direct Memory Access

A technique that permits a peripheral device to enteror extract blocks of data from the memory withoutinvolving the central processing unit. In some cases,the CPU can perform other functions while the datatransfers occur.


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Components of Interface

InterfaceSignals

InterfaceSignals

InterfacingDevice

(ID 1)

InterfacingDevice

(ID 2)

InterfacingStandard

s&

Co

nverters

The interfacing devices should make use of standard data

transfer schemes for the efficient exchange of data.


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Data Transfer Schemes refers to the method of data transfer between the

processor and peripheral devices:

microprocessor and memory

microprocessor and I/O devices

memory and I/O devices

For effective data transfer between thesedevices, the timing parameters of thedevices should be matched.

But most of the devices haveincompatible timings.


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Two Categories:

1. Programmed data

transfer.2. Direct memory access

data transfer.


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Programmed Data Transfer

a memory resident routine(subroutine) requests thedevice for data transfer toor from one of the

processor register scheme is used when a

relatively small amountdata are to be transferred

usually one byte or wordof data is transferred at atime

Examples of devices usingparallel data transfer areADC,DAC, Hex-keyboard, 7-segment LED's, etc.


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3 Types of Programmed Data Transfer

The scheme can be further classified into thefollowing:

1. Synchronous data transfer scheme.

2. Asynchronous data transfer scheme.

3. Interrupt driven data transfer scheme.


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Direct Memory Access (DMA) Data Transfer

the processor is forced to holdstate by an I/O device untilthe data transfer between thedevice and the memory iscompleted

the processor does notexecute any instructions

during the hold period is used for large block of data

transfer between I/O deviceand memory

Typical examples of devices usingDMA are CRT controller, floppydisk, hard disk, high speed lineprinter, etc


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3 Types of DMA Data Transfer

The schemes are:

1. Cycle stealing DMA.

2. Block or Burst mode DMA.3. Demand transfer mode DMA.


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Types of Data Transfer Schemes


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PROGRAM CONTROLLED TRANSFER the transfer of data is completely under the control of

the microprocessor program

data transfers can take place synchronously orasynchronously

an i/o operation takes place only when an i/o instruction isencountered in the execution of the program

synchronous transfers mean

transfers occurring at the sametime

asynchronous transfers mean

transfers taking place atirregular intervals

Data transfers between the microprocessor and theperipherals are primarily asynchronous


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Program controlled data transfers can take placeunder several conditions

Unconditional

Polling

Interrupt

With ready signal

With handshake signals

assumes that a peripheral is always available

kept in a loop to check whether data are available

interrupted from its normal execution of programby an I/O device, when the latter is ready

when peripheral response time is slower than themicroprocessor execution time, READY signal is used

handshake signals are signals exchanged prior to data transfer


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Synchronous data transfer scheme

is the simplest of all datatransfer schemes

the processor does notcheck the readiness ofthe device

I/O device or peripheralshould have matchedtiming parameters

the mode-O input or output in 8155 or 8255 is an example of synchronous data transfer


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Asynchronous Data Transfer Schemes

is employed when the speedof processor and I/O devicedoes not match

the processor ends a requestto the device for read/write

operation then the processor keeps on

polling the status of the device once the device is ready, the

processor executes a data transferinstruction to complete the process

to implement this scheme, thedevice should provide a signalwhich may be tested by theprocessor to ascertain whether it isready or not

handshake data transfer without interrupt (mode-l and mode-2) of8155 or 8255 is an example


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Interrupt Driven Data Transfer Scheme is the best method of data f

transfer for effectivelyutilizing the processor time

the processor first initiates the I/O devicefor data transfer. After initiating the device,the processor will continue the execution ofinstructions in the program. Also at the end ofan instruction the processor will check for avalid interrupt signal. If there is no interruptthen the processor will continue the execution.

When the IO device is ready, it willinterrupt the processor. On receiving aninterrupt signal, the processor will complete thecurrent instruction execution and saves theprocessor status in stack. Then the processorcall an interrupt service routine (ISR) to servicethe interrupted device.


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when the processor callan interrupt serviceroutine (ISR) toservice the interrupted

device. At the end ofISR the processorstatus is retrieved fromstack and theprocessor startsexecuting its mainprogram.


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PROGRAM CONTROLLED DMA TRANSFERS

In DMA transfer, the microprocessor is forced to holdon by an I/O device until the data transfer is

complete

In programmed data transfer, a memory resident routine requests the device fordata transfer to and from one of the microprocessor registers

Programmed data are used when relatively small amounts of data are transferredusing relatively slow I/O devices such AID, D/A converters, and peripheral floatingpoint arithmetic unit.

DMA is preferred when a large block of data is to betransferred. This scheme is generally employed fortransferring data between the microprocessor andperipheral mass storage devices like hard disk or a high-speed line printer.


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Interrupt

An interrupt is a condition that causes themicroprocessor to temporarily work on a differenttask, and then later return to its previous task.

Interrupts can be internal or external. Internalinterrupts, or "software interrupts," are triggered bya software instruction and operate similarly to a

jump or branch instruction.

An external interrupt, or a "hardware interrupt," iscaused by an external hardware module.


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As an example, many computer systemsuse interrupt driven I/O, a process wherepressing a key on the keyboard or clicking a buttonon the mouse triggers an interrupt.

The processor stops what it is doing, it reads the inputfrom the keyboard or mouse, and then it returns to

the current program.


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The image below shows conceptually how aninterrupt happens:

The grey bars represent the control flow. The top line is theprogram that is currently running, and the bottom bar is the

interrupt service routine (ISR). Notice that when theinterrupt (Int) occurs, the program stops executing and themicrocontroller begins to execute the ISR. Once the ISR iscomplete, the microcontroller returns to processing theprogram where it left off.
http://en.wikibooks.org/wiki/File:Interrupt.svg


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INTERRUPT PROCESS IN MICROCOMPUTERS

8085

FIVE pins on the chip for implementingthe interrupt process

PIN NO Name

6 TRAP

7 RST 7.5

8 RST 6.59 RST 5.5

10 INTR.


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On these five lines, 8085 canreceive signals from the peripheraldevices, requesting the

microprocessor to attend to datatransfers from them or send datato them. These are calledHARDWARE INTERRUPTS.

Pin No 11 on the chip is an

active low signal, sent by themicroprocessor, to acknowledge thereceipt of the interrupt signal.

In addition 8085 has an internalflip-flop called INTERRUPT

ENABLE flip flop, This should beset, in order for the ~p to beinterrupted. 8085 has the followinginstructions the set or reset thisflip -flop.


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8085 has the following instructions the set or reset this flip flop:

EI : (Enable Interrupt):

This is a one byte instruction

-This sets the IE flip -flop and enables the interruptprocess.

-System reset or an interrupt disables the interruptprocess


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DI : (Disable Interrupt):

This is also one byte instruction.

-This resets the IE flip -flop and disables the interruptprocess.

-It should be included in a program segment where aninterrupt from an external source can nut be

tolerated.


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These Interrupts are called VECTOREDINTERRUPTS. What it means is that each of theinterrupts except INTR is associated with a branchaddress on page OOH in ROM.

an interrupt vector is the memory address ofan interrupt handler, or an index into an array calledan interrupt vector table or dispatch table containing the

memory addresses of interrupt handlers. When aninterrupt is generated, the processor saves its executionstate via a context switch, and begins execution of theinterrupt handler at the interrupt vector.


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On occurrence of an interrupt, the processor's controlis automatically transferred to the respective location.

This is achieved by internal hardware. This way of

automatically transferring control in response to aninterrupt is called VECTORING.

In case of INTR, the lNTA signal issued in response tothe signal on INTR lines is used to insert a RST

instruction lone byte CALL) on the data bus. Thebranch addresses is determined by the RSTinstruction.


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I/O devices can interrupt the ~p on any of the 5 pins. The nature of theinterrupt signals, their characteristics and their branch addresses are asfollows:

Name of the

Interrupt Triggering Branch

Location(ISR)Priority

TRAP Level and Edge 0024H 1RST 7.5 Edge 003CH 2RST 6.5 Level 0034H 3RST 5.5 Level 002CH 4INTR Level Enable/Disable under

Program

A t h i f i t i


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SIM : Set Interrupt Mask. This is a 1 -byteinstruction, used to mask or unmask the interruptsRST 7.5, 6.5 & 5.5.

To use this instruction, the accumulator is to be loadedwith a data byte whose bits have the purposes shownin figure below:

D7 D6 D5 D4 D3 D2 D1 D0

Interpretation of Accumulator bits for SIM

SOD SDE X R 7.5 MSE M 7.5 M 6.5 M 5.5

A technique of suppressing certaininterrupts and allowing the control programto handle these masked interrupts at alater time.


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D7 (SOD): Serial output Data -If D6 == 0, D7 isignored

D6 (SDE): Serial Data enable -If 1, D7 is output

serially. M7.5, 6.5, 5.5, Mask -set: 0: available 1: masked.

MSE Mask set enable: IfO, bits Do, Dl, D2 areignored;

R 7.5 : RESET RST 7.5 If 1, RST 7.5 is reset.


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RIM : (READ INTERRUPT MASK)This is also 1 -byte instruction; this instruction is used to

identify finding interrupts, when multiple devices interruptthe processor. When this instruction is written in a

program and is executed by the microprocessor, theaccumulator is loaded with a byte, whose bits indicate theinformation shown in figure below.

week 1 intro to interfacing tech

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