WEEK 7 BRIEFING

EE1003

Zhang Jianwen

2

PCM encoder

Frame marker

Analogy voice signal

Logic

MUX Laser

Photodiode

All Digital Phase lock

loop

Frame synchronization

PCMdecoder

Project diagram

Decoder timing (short frame)

MCLK, BCLK and FSR have their rising edges aligned.

FSR precedes data frame by one BCLK period.

BCLK falling edges align with the center of respective data bits.

Detection of digital signal

Determine the received data bit at the right moments.

Transmitting signal

Received signal

Decision time

detection

1 0 1 0 1 0 1

1 1 1 0 1 1 1

Detection of digital signal

Generally, we make decision at the center of each received bit signal.

1. Recover the delayed version of the transmit side clock.

2. Make decision at the rising/falling edges of the recovered bclk

1 0 1 0 1 0 1

6

Implications to the system design

We need ADPLL to recover BCLK and MCLK

We need frame markers to assist frame synchronization. Generate the frame markers. Switch between frame markers and the

data frames. Identify the frame markers and retrieve FSR

signal. Filter the false FSR.

7

Design report

Design report ---10% Follow the template. Due by midnight of your session day on

week 8. Submit a soft copy your report to student

submissions fold in workbin of IVLE. Not more than 10 pages of A4 paper. Font type: Times New Roman, Size 12 at

least.

8

Software for schematics

Fritzing from http://fritzing.org/ Free to use electronic design automation

tool. Download from

http://fritzing.org/download/ Functions:

Schematics: describe your design with chip level details.

Breadboard layout: design your breadboard layout based on your schematics.

Creat custom parts. (There are 2 ways to do it.)

http://fritzing.org/learning/tutorials/creating-custom-parts/

9

Software for schematics

10

Software for schematics

11

Week 7

Group/subgroup discussion Design report (Monday midnight next

week) Project session

12

Constellations

Midterm: Wed, 4 March, 9:00-11:00, MPSH1B. Bring your writing materials and calculator.

Detailed information from IVLE.

13

Laser link

Think about the supporting for the laser pointer and photodiode such that the laser link is reliable.

Negative pole of photodiode is often connected with its cover.

14

Develop your project portfolio online Platform: Wiki@nus

http://wiki.nus.edu.sg/dashboard.action https://wiki.nus.edu.sg/display/EE1003/AY+1415+Semester+2+

Home+Page Common space

https://wiki.nus.edu.sg/display/EE1003/AY+1415+Semester+2+Common+Space

Your group space Links will be sent to individual group later.

How it works? You login wiki@nus Access right to your group page will be granted to your group. You prepare your project portfolio on wiki.

Discussion online I will check your progress online and join your discussion Participations will be counted.

Operational Amplifier

Compute the gain. Input impedance = ∞ Voltage difference ≈ 0

+

_R1

R2

GND

x y

012

R

x

R

yx

R

Ry

1

2By KCL