Welding next to electronicsRichard French, John Matheson, Ian Wilmut

May 2012

• The Swagelok orbital welder

• Use of the orbital welder at the patch panels

• A lead from the literature

• “Destructive” testing: XCHIP, ABCN-25, ABCN-13, FEI4

• EMFs induced by changing magnetic field

• Conclusions so far

• What next ?

Orbital welder setup

power supplyweld head

jig for butting tubes

small weld head

tungsten tip, motor drivenpower cables run close together

Nominal current waveform

RAL services mockup

Built to examine feasibility of joining pipes using orbital welder

Each pipe has a joining section2 welds per pipePosition, orientation of weld head known (or so we believe.... )

Mockup built by Mike Bell, John Hill (RAL)

Electric welding hazard to spacecraft electronics, Whittlesey and Lumsden, IEEE Int Symp on EMC, Boulder 1981

measure energy to blow small fuse fuse blow test with welder

In this work, the risk for electronics came from V fluctuations on the pipeas the arc start circuit fired: 40 kV spark used to initiate arc

Comparison with Literature -1

Used orbital welder on propellant tubing near electronics (Galileo spacecraft)Any voltage transient on pipe can couple into electronics“The basic welding process is benign”

Recommendations:Minimise starting powerGround tubing between weld and ESDS electronicsShield connectors

Swagelok welder: output V ramps to 1600V before arc established- measured using potential divider and ‘ scope

Comparison with Literature - 2

* ESDS Equipment Susceptibility to Welding Generated EM Fields, Anderson et al, IEEE 1998

First principles calculation, welding on submarinesCables make current loop, associated B and E fieldsArc radiates magnetic field (E small for scratch start)Changing magnetic fields induce voltage on PCB

Recommendations: shield connectors, 15cm between welding and electronics

Our numbers not frightening if we take 1/(converter f = 79 kHz ) as risetime(but watch out for start transient)

Loop A I (A) distance risetime E field Loop B Arc B Induced V

Submarines 1 m2 2000 15 cm 100 us 10 V/cm 6 G 10G 4V /400cm2

6mm pipes 25 cm2 20 10 cm 12 us 4mV/cm <1G 1G 1V /100cm2

ε ~ dϕ / dt

ESD testing of XCHIP

input showing ESD protection diodes

IV curve input pad to GND before/after ESD test

the protection diodehas blown in the lower trace

this region is gate leakagegood gate => pA leakagedamaged gate => nA leakage

Estimated energy:to melt diode 208 uJto vapourise 1200uJ

2000V on 100pF= 200uJHBM 2000V

Thanks to Stephen Thomas (RAL)

XSTRIP input soldered directly to the pipe blows the input every timeXSTRIP connected to pipe via ceramic C: damage scales with C, I

50pF 100pF 220pF 500pF dc

10A OK OK blow blow

20A OK blow blow

30A OK blow blow blow

40A OK blow blow

How to blow an XSTRIP with the welder

should be possible to estimate actual C coupling to pipe (later)can we estimate a threshold for a given geometry and chip ?can we define a regime where we are confident of no damage ??

making the connection during the weld shows the channel blows as the arc starts, not during the weld itself

X

50pF 100pF 220pF 500pF

40A OK OK blow blow

Repeat measurementNew weld head May 2012

Effect of ground strap

previously chip blew by 100pF, now 220pFweld head, temperature, humidity not the same....not a big change for our purposes

Chip3 chan 13 with 470pFAfter 1 weld 40A/10A/10%No ground strap - blown

Chip 3 chan 11 with 1000pFAfter 9 welds 1 misfireAdded ground strap – no damage

measurement of ABCN-25 before/after welding

ABCN-25 has thinner gate oxide than XSTRIPBUT, standard IBM 250 um OK to HBM 4000V cf. XSTRIP HBM 2000V

As feature size in CMOS process gets smaller, gate oxide gets thinnerDetector ROIC: noise scales with input capacitanceTrade-off between noise and ESD protectionInput FET is the weakest point

shown here 1 channel bonded to PCB at input C>Cdet

One ABCN-25 channel has undergone anumber of welds in proximity, no effectAlso with channel connected to pipe (results on next slide !)

Thanks to Peter Phillips

ABCN-25 after welding, test electrode bonded to input – capacitance causes excess noise

ABCN-25 after welding, bond pulled from input – gain, noise of tested channel normal

input connected to pipe50A/5A/5%

need to check for cumulative stressmany welds followed by thermal ageing

ABCN-25 I-V of input pad

ABCN-13 test chip destructive testing

Thanks to: Jan Kaplon, Matt Noy (CERN) Alexander Bitadze (Glasgow) Steve McMahon (RAL)

ABCN-13 front end test structureCalibration lines allow test pulse input60 fF calibration capacitorsESD protection grounded gate NMOSShould protect for 1200V HBMTrade-off ESD protection vs noise

Welding: one input bonded outSM capacitor on PCBPipe placed in contactVery severe test !

PCB10, 10pF cap, 40A/5A/10%

A=102

A=101

σ=2.73

σ=3.21

ENC = (σ/A) * 15000 RMS e- => 399 initially, 476 finally

ABCN-13 destructive testing

before

after

welding OK, if coupling is small enoughguesstimate coupling C ~ 5pFNeed to measure it !

ground strap on pipe will improve mattersa grounded layer in the bus tape ?ceramic breaks in the pipe (proposed for G+S)

ABCN-13 destructive testing

Compilation of all tests on 4 samples

C = εA/W with V = eNDW2/2ε and ND=1E12 /cc strip is 2.5cm by 80μmdepleted strip to backplane C = 0.7pFno bias strip to backplane C = 7pFac coupling capacitor ~ 20pF

what is the equivalent circuit ?

SensorBus tapeFacingFoam core

FEI4 pixel chip destructive testing

Tune the chipSave DAC settings Run with same settings + checkWeldRun with same settings + check

Tune:choose desired ToT for given Q inapply calibration pulsestune feedback and threshold DACs

Thanks to: Christian Gallrapp (CERN) Andy Blue, Kate Doonan, Richard Bates (Glasgow)

Check:threshold scanToT verifyanalogue and digital tests

FEI4 pixel chip test results

Original tuning to threshold 3200 electrons, ToT = 5 clock counts for 10k electrons

Threshold map from s-curve measured before/after a single weld

FEI4 pixel chip test results

Noise map from s-curve measured before/after a single weld

Original tuning to threshold 3200 electrons, ToT = 5 clock counts for 10k electrons

FEI4 pixel chip test results

ToT map for 10k electron cal pulses before/after a single weld

Original tuning to threshold 3200 electrons, ToT = 5 clock counts for 10k electrons

Measurement of changing B-field

Any loop can couple....Use near field probes:http://www.ets-lindgren.com/7405Work is ongoing

Specific worry about DCDC coilsMax. emf during start transient3V measured with DCDC coil next to weld head 1V at realistic distance, orientationGrounded Al foil => x2 improvement Reproducibility suspect: T, humidity ?

Conclusions

ROICs can be damaged by preamp input being capacitively coupled to voltage fluctuations on the pipe, as the arc is first initiated

Fields near the weld head are not large and (with small statistics) no chip has ever failed by welding in proximity, without a deliberate input connection

XSTRIP test structures: no damage until C way beyond a realistic setup. Damage preventable by ground strap between weld head and chip connection to pipe.

ABCN-25: no damage for any setup tested so far

ABCN-13: susceptible to damage at C which is “not unreasonable”

FEI4: only tested by welding in proximity, no change

Voltage induced on shielded DCDC inductor looks acceptable; best to discuss with DCDC experts

Where next ?

Measuring the voltage fluctuations during welding and considering equivalent circuitscould give a full understanding of the physics (maybe not necessary ?).

Grounding, shielding and the welding programme could be tailored to prevent damage

If ceramic breaks were added to the pipes, capacitive coupling will be minimal

Could shielding be built in to stave ? Small mass cf. compression fittings....

Measure how a real module couples electrically to the pipe (simulation too ?) ?

Further destructive tests with ABCN-13, more realistic test layout and ground strap

Multiple welds followed by ageing at elevated T to check for latent damage

Continue measurements with near field probes: coupling to loops, inductors

Spare Slides

‘scope traces with Current probe on output leads

Low = 5A High = 10A 20% duty cycle

Note >45A current spike at start

Measuring welder output current

Inverter f = 79 kHzIrrespective of current setting

Arc start transient voltage few 10s of ms to fireLow = 5A High = 20A10% duty cycle200:1 potential divider => 1600 V

Voltage during weldingLow = 5A High = 40A20% duty cycle 20:1 potential divider10-20V

Start voltage transient at welder output

redefining the problem

bus cable

ac-coupled detector

arc

input FET

We believe E and dB/dt from the arc likely to be too small to be relevant here.But we should demonstrate it (near field probes , module mockup, etc.?) !

to (over ?) simplify:pickup electrodes charge up a capacitance , which discharges into the input FET gate

the geometry of the electrodes matters, relative to the electric field configurationthe stored energy matters – need enough to rupture the gate, E = ½ CV2

the electrodes could couple capacitively to V fluctuations on the pipe

The input FET is likely the most vulnerable point. All chip pads will have protection diodes,but big protection diodes decrease PSRR – so the diodes are made as small as possible. All open connectors would be grounded.

XCHIP ESD diodes 100 um * 100 um * 3 umHBM 2000V

ABCN-25standard library protection is HBM 4000V pdiode 495 p nwell diode 184 pactually used pdiode134 p, nwell diode 141 p, 15 OhmHBM ?? < 4000V

ABCN-13 standard library protection is HBM 4000V NFET 360 um / 240 nmactually used NFET 80um / 120nm – expect HBM 1200V

ESD protection in different technologies

Voltage on pipe relative toWall ground

High = 30A Low = 10ADuty cycle = 10%

Upper: no deliberate pipe groundLower: Cu braid grounding pipe

Y- ground causes misfires ??

Measuring V on pipe

Where next ? equivalent circuits

what are the relevant coupling capacitances ?what are the relevant arc sampling geometries ?the detector will be undepleted during welding !

can we scale between chip processes, based on gate parameters ?

1pF

3.9pF

10pF