WEN-BEN JONE

Curriculum Vitae

AREAS OF INTEREST

Current research interests include VLSI design for testability and low power dissipation, error

resilient VLSI circuit design and test, deep neural network accelerator VLSI design, approximate

circuit synthesis for deep neural network.

EDUCATION

Case Western Reserve University (USA)

PhD in Computer Engineering (August 1987)

Thesis Title: Methodology for Parallel Testing of VLSI Circuits Based on Partitioning and

Built-In Self-Testing Techniques

National Chiao-Tung University (Taiwan)

ME in Computer Engineering (May 1981)

Thesis Title: Random Testing and Logic Design

National Chiao-Tung University (Taiwan)

BS in Computer Science (June 1979)

PROFESSIONAL ACTIVITIES AND SOCIETIES

* Senior member of the IEEE

* Member of the IEEE Test Technology Technical Committee

* Member of the IEEE Technical Committee on Fault-Tolerant Computing

* Member of the Institute of Chinese Electrical Engineering

* Associate editor of International Journal of Computers, Information Technology and Engineering

* Associate editor of Research Letters in Electronics

* Program committee of the 1993-1997 VLSI Desgn/CAD Symposium (in Taiwan)

* General Chair of the 1998 VLSI Design/CAD Symposium (in Taiwan)

* Program committee of the 1995-2001 Asia and South Pacific Design Automation Conference

* Program committee of the 1995-1996, 2000, 2004, 2009 Asian Test Symposium

* Publication Chair of the 2000, 2004 Asian Test Symposium

* Program committee of the 1998 International Conference on Chip Technology

* Program committee of the 2000, 2007-2010 IEEE International Symposium on Defect and Fault

Tolerance in VLSI Systems

* Program committee of the 2002, 2003 Great Lake Symposium on VLSI

* Publication Chair of 48th IEEE International Midwest Symposium on Circuits and Systems, 2005

* Review committee member of 50th IEEE International Midwest Symposium on Circuits and

Systems, 2007

* Referee of the International Journal of Modeling and Simulation

* Referee of the IEEE Computer Magazine (special issue on Software Tool for Hardware Test

* Referee of the IEEE International Test Conference

* Referee of the ACM/IEEE Design Automation Conference

* Referee of the International Journal of Computer Aided VLSI Design

* Referee of the Journal of Electronic Testing: Theory and Applications

* Referee of the IEEE Transactions on Computers

* Referee of the IEEE Transactions on Computer-Aided Design

* Referee of the IEEE Transactions on System, Man and Cybernetics

* Referee of the IEEE Transactions on VLSI Systems

* Referee of the IEEE Journal of Solid-State Circuits

* Referee of the IEEE Design & Test of Computers

* Referee of the National Science Foundation (USA)

* Referee of the National Science Council (Taiwan)

* Referee of the IEEE/ACM International Conference on Computer-Aided Design

* Referee of the International Conference on Parallel and Distributed Systems

* Referee of the Asian Test Conference

TUTORIALS

Parallel Test Pattern Generation for VLSI Circuits, 1994 International Conference on Parallel and

Distributed Systems (jointly with Prof. Sunil R. Das)

WORK EXPERIENCE (ACADEMIC)

Assistant Professor

August 87 - May 92

Associate Professor (with tenure)

May 92 - February 93

Department of Computer Science

New Mexico Tech

Socorro, NM 87801

USA

Professor

February 93 – Jan. 2001

Department of Computer Science and Information Engineering

National Chung-Cheng University

Chiayi, Taiwan, ROC

Associate Professor with tenure

Feb. 2001 – present

Department of Electrical & Computer Engineering and Computer Science

University of Cincinnati

Cincinnati, OH 45221

Sample Courses Taught

CS 121 Computer Programming

CS 122 Data Structure

CS 221 Introduction to System Programming

CS 240 Discrete Mathematics

CS 341 Switching Theory and Logic Design

CS 381 Computer Organization

CS 431 Computer Architecture (CAD Tools: Cadence Verilog-XL)

CS 460 Micro-processor Design

CS 550 Fault Tolerant Computing

CS 582 VLSI Testing (CAD Tools: Synopsys Test Compiler, Mentor Graphics Test Tools)

CS 531 Advanced Computer Architecture

CS 581 VLSI Systems Design (CAD Tools: Opus, Dracula, Design Compiler)

CS 590 Low Power Design for VLSI Systems

WORK EXPERIENCE (INDUSTRY)

R&D Officer and Systems Analyst

Military 206 Arsenal of Taiwan

July 81 - May 83

Worked in the Digital System Lab., and designed highly reliable digital systems (used in

missiles).

Assisted the Military Arsenal Computer Center to develop the Arsenal Information

Management Systems (in the networks of IBM S/34).

HONORS AND AWARDS

1. Master Thesis was judged to be the Best Thesis and was awarded First Prize by the Chinese

Electrical Engineering Association in 1981.

2. Elevated to IEEE Senior Member grade in March 2002.

3. Listed in the 15th Edition of Marquis Who's Who in the World, 1998, 2001

4. Co-recipient of 2003 IEEE Donald G. Fink Prize Paper Award.

The IEEE Donald G. Fink Prize Award was established in 1979. It is presented for the outstanding

survey, review, or tutorial paper in any of the IEEE transactions, journals, and magazines, or in

Proceedings of IEEE, issued during the previous calendar year. The paper “Fault Tolerant Systems

Design in VLSI Using Data Compression Under Constraints of Failure Probabilities” co-authored by

Das, Ramamoorthy, Assaf, Petriu and Jone is a powerful reference for professionals who develop these

new chips. The paper offers a lucid case for the importance of response data compaction, as well as an

extensive overview of the various built-in self-test (BIST) methods available. (copied from 2003 IEEE

Awards Bulletin)

5. Co-recipient of 2008 International Symposium for Low-Power Electronics and Design Best

paper award. The paper title is: “Dynamic Virtual Ground Voltage Estimation for Power Gating”

co-authored by Hao Xu and Ranga Vemuri.

6. Co-recipient of 2012 International Symposium on VLSI Design, Automation & Test best paper

award. The paper title is "Imitator: A Deterministic Multicore Replay System with Refining

Techniques," co-authored by S. Y. Chen, C. N. Wen, G. H. Yang, and T. F. Chen.

7. His papers have been cited more than 1800 times according to the statistics by Google Scholar.

8. Listed in the 6th Edition of Marquis Who's Who in Science and Engineering, 2002-2003.

9. Listed in the 64th Edition of Who’s who in America, 2010.

10. Listed in Top Authors in Scientific Computing – Microsoft Academic Search

(http://academic.research.microsoft.com/CSDirectory/author_category_22_last10_60.htm)

11. Listed in Top Authors in Machine Learning and Pattern Recognition – Microsoft Academic

Search (http://journalogy.com/CSDirectory/author_category_6_54.htm)

12. Listed in Top Authors in Computer Science Overall – Microsoft Academic Search

http://academic.research.microsoft.com/CSDirectory/author_category_24_last5_95.htm

13. Elected Professor of Quarter, Spring, 2008 for his excellent teaching in Introduction to Digital Systems

Design.

14. The First-Class Research Award, National Science Council, Taiwan, Republic of China,

1994-2000.

15. Co-recipient of Best Teaching Award, Department of Electrical Engineering and Computing

Systems for his excellent teaching in Programming for ECE, 2016.

16. Co-recipient of Masters Educator Award, College of Engineering and Applied Science for his

excellent teaching and service.

GRANTS

1. VLSI Testing: from Research and Development and Division, New Mexico Tech, 1/1/89 - 1/1/90

(US$7000.00).

2. Random Pattern Testability of VLSI Circuits: Supported by Sandia National Laboratories,

Contract Number Sandia 54-9306, 10/1/89 - 9/30/90 (US$30,000.00).

3. Knowledge-Driven Test Generation for Sequential Circuits: Supported by Sandia National

Laboratories, Contract Number Sandia 27-6108, 10/1/90 - 9/30/91 (US$30,000.00).

4. Combinational Circuit Testing Using Random Testing Techniques: Supported by National

Science Council, Taiwan, Contract Number NSC 83-0404-E-194-041, 2/1/93 - 1/31/94

(US$10,000.00).

5. VLSI Systems Design: Equipment Funding, Supported by National Science Council, Taiwan,

Contract Number NSC 83-0910-F-200-103, 9/1/93 - 1/31/94 (US$20,000.00).

6. Pseudorandom Test Analysis using Differential Solutions: Supported by National Science

Council, Taiwan, Contract Number NSC 84-0404-E-194-020, 2/1/94 - 7/31/95 (US$20,000.00).

7. Defect Level Analysis, Yield Prediction, and Test Management for VLSI Fabrication and

Testing: Supported by National Science Council, Taiwan, Contract Number NSC

85-2215-E-194-003, 8/1/95 - 7/31/96 (US$10,000.00).

8. Delay Fault Coverage Enhancement Using Multiple Test Observation Times: Supported by

National Science Council, Taiwan, Contract Number NSC 86-2215-E-194-004, 8/1/96 - 7/31/97

(US$ 13,000.00).

9. Instruction Circuit Optimization for Low-Power Application-Specific Embedded

Micro-controller: Supported by National Science Council, Taiwan, Contract Number NSC

86-2215-E-194-008, 8/1/96 - 7/31/97 (US$ 11,000.00).

10. CPU Testing and Testability Features: Supported by National Science Council, Taiwan,

Contract Number NSC 86-2622-E-008-010, 6/1/96 - 5/31/97, Jointly with Prof. K. J. Lee (US$

63,000.00).

11. An Adaptive Path Selection Method for Delay Testing: Supported by National Science Council,

Taiwan, Contract Number 87-2215-E-194-007, 8/1/97-7/31/98 (US$ 14,000.00).

12. Instruction Circuit Optimization for Low-Power Application-Specific Embedded

Microcontroller: Supported by National Science Council, Taiwan, Contract Number NSC

87-2215-E-194-003, 8/1/97 - 7/31/98 (US$ 10,000.00).

13. CPU Testing and Testability Features: Supported by National Science Council, Taiwan,

Contract Number NSC 87-2622-E-008-010, 6/1/97 - 5/31/98, Jointly with Prof. K. J. Lee (US$

45,000.00).

14. Register Transfer Level Optimization for Low-Power Application-Specific Embedded

Micro-controller: Supported by National Science Council, Taiwan, Contract Number NSC

88-2215-E-194-003, 8/1/98 - 7/31/99 (US$ 15,000.00).

15. CPU Testing and Testability Features: Supported by National Science Council, Taiwan,

Contract Number NSC 88-2622-E-008-010, 6/1/98 - 5/31/99, Jointly with Prof. K. J. Lee (US$

45,000.00).

16. Signal Integrity Testing for High-Performance VLSI Circuits in Deep Sub-Micron Technology:

Supported by Ohio Board of Regent Computing Research Award, May 2001-May 2003 (US$

24,200.00)

17. Built-in Self-test and Self-repair Techniques for Capacitive MEMS Devices: Supported by

Ohio Board of Regent Computing Research Award, Feb. 2004-March 2005 (US$ 32,200.00)

18. Acquisition of research instrumentation for electronic systems emulation, prototyping, and

testing: Supported by National Science Foundation (USA), US$ 280,085, with R. Vemuri, F.

Beyette, H. Carter, W.-B. Jone, K. Tomko, P. Wilsey, and C. Purdy, 9/1/04-8/31/07.

19. Low Power Cache Architectures Using Selective Way Activation – Low-Power Design and Test:

Supported by National Science Foundation (USA), US$ 390,000, jointly with Prof. Yiming Hu,

2006-2010.

PATENTS

1. Built-in Self Test for Multiple Memories in a chip, by Kuen-Jong Lee, Jing-Yang Wu and

Wen-Ben Jone, US Patent No. 09/268,666, ROC Patent No. 123,572. Period: 2000/11/11 -

2018/6/22.

THESIS SUPERVISION

1. Robert T. Perez (MS), Random Pattern Testability of FET Stuck-Open Faults in COMS

Combinational Logic Circuits, Sep. 1988.

2. Marcos Pereira (MS), Parallel Testing of VLSI Circuits, Feb. 1989.

3. Patrick Madden (MS), Multiple Fault Detection of Fanout-free Circuits by Using Single Test

Sets, Dec. 1989.

4. Chi-Perng Yang (MS), PLA Testing by Adding Extra Inputs and Outputs, Sep. 1990.

5. Cheng-Juei Wu (MS), On Multiple Fault Detection of Parity Checkers, Sep. 1990.

6. Anita Gleason (PhD), Hamming-Count - A New Test Compression Method, Dec. 1990.

7. Nigam Shah (MS), PGEN: A Novel Approach to Sequential Circuit Testing, Feb. 1991.

8. Paresh Gondalia (MS), Defect Level and Yield Estimation for VLSI Fabrication, Dec. 1992.

9. Jen-Liang Fang (MS), Critical path identification and timing optimization for circuit synthesis,

August 1992.

10. Dan Li (MS), On Pseudorandom Testability Analysis for VLSI Built-In Self-Testing, Dec. 1992.

11. Kuen-Sien Tsai (MS), Confidence Analysis for Defect Level Estimation of VLSI Random

Testing, June 1995.

12. Yun-Pen Ho (MS), Delay Fault Coverage Enhancement Using Multiple Test Observation Times,

June 1995.

13. Jen-Chi Rau (MS), A Tree-Structured LFSR Synthesis Scheme for Pseodo-Exhaustive Testing

of VLSI Circuits, June 1995.

14. Hui-Nan Chang (MS), Low Power Design of VLSI Circuits Using Gate Resizing and Supply

Voltage Scaling Techniques, June 1996.

15. Wu-Sung Yeh (MS), An Adaptive Path Selection Method for Delay Testing, June 1996.

16. Jen-Yu Chen (MS), Segmented Bus Design for Low-Power Systems, June 1997.

17. Shuen-Chen Wu (MS), An Efficient BIST Method for Distributed Small Buffers, June 1997.

18. I. Ping Hsu (MS), Implementation Techniques of Segmented Bus Design for Low-Power VLSI

Chips, June 1998.

19. Kwen-Yo Chen (MS), Random Pattern Testability Enhancement by Circuit Rewiring, June

1998.

20. Tsong-Siu Wu (MS), Functional Testing for Superscalar Processors, June 1998.

21. Chia-Haw Chang (MS), Testable Design and Implementation for a Microcontroller, June 1999.

22. Wen-Chi Fong (MS), Low-Swing Bus Segmentation Design for Low-Power Systems, June

1999.

23. Jia-Hui Jiang (MS), Embedded Core Testing Using Broadcast Test Architecture, June 2000.

24. Sen-Tien Lin (MS), True Single Phase Circuit Design for Testability, June 2000.

25. Jian-Chi Rau (PhD), Pseudo-Exhaustive Testing for VLSI Circuits Using Tree-Structured Test

Scheme, Oct. 2000.

26. Chin-Hua Cheng (PhD), Charge-Sharing Alleviation and Detection for Domino Circuits, Nov.

2000.

27. Der-Chen Huang (PhD), Built-In Self Testing and Diagnosis for Embedded Memory Arrays,

Nov. 2000.

28. Chau-Wei Chen (MS), Testable Design and Implementation for a 32-bit Micro-controller, June

2001.

29. Vikram Arora (MS), An Efficient Built-In Self-Diagnostic Method for Non-Traditional Faults of

Embedded Memory Arrays, Nov. 2002.

30. Vinod Narayanan (MS), A Built-In Self-Testing Method for Embedded Multiple-Port Memory

Array, Jan. 2003.

31. J. Liu (MS), Crosstalk Test Generation and Alleviation for Dynamic PLAs, July 2003.

32. M. Li (MS), Test Frequency Selection for Analog Circuits Based on Bode Diagram and

Equivalent Fault Grouping, May 2004 (Co-Advisor: Dr. Ranga Vemuri).

33. S. Ghosh (MS), Scan Chain Fault Identification Using Weight-Based Codes for SoC Circuits,

May 2004.

34. Sriram Hariharan (MS), Performance Evaluation of On-Chip Communications in a

Network-on-Chip System, Feb. 2005.

35. K. Maddi MS), A Methodology for Interconnect Testing of Network-on-Chip, March 2005.

36. R. Martin (MS), The Flash Single Bit Per Cell and Multi-level Cell Overview, June 2005.

37. X. Xiong (PhD), Built-in Self-Test and Self-Repair for Capacitive MEMS Devices, July 2005.

38. F. Lu (MS), A Hardware Implementation for Multiple Backtracing Algorithm, Sep. 2005.

39. S. Kalala (MS), Timing and Placement Optimization for Segmented Bus Architectures for

Low-Power ASIC Design, Sep. 2005.

40. W. Pei (MS), Fault Modeling and Detection for Drowsy SRAM Caches, Oct. 2005.

41. Y. Zhou (MS), Memory Power Variations and Test Scheduling for Embedded Memory Arrays,

Jan. 2006.

42. A. Krishnamurthy (MS), Statistical Estimation and Reduction of Leakage Current by Input

Vector Control with Process Variations Considered, March 2006.

43. G. Gupta (MS), Design and Analysis of Low-Power Set-Associative Cache Using Partial Tag

Comparison, Feb. 2006.

44. S. K. Shenoy (MS), Design and Test of a MEMS Reconfigurable and Tunable Capacitor, May

2006.

45. C. K. Wang (MS), An Iterative Crosstalk Timing Analyzer, Sep. 2006.

46. M. Li (PhD), Design and Test of a High-Performance Network-on-Chip Architecture for Highly

Integrated Systems, Sep. 2006.

47. W. Mao (MS), Design and Test Generation for Clock Skew Faults of Clock-Delayed Domino

Logic Circuits, Oct. 2006.

48. X. Pan (MS), Performance Analysis for Clock and Data Recovery Circuits under Process

Variation, May 2007.

49. B. Qi (MS), Performance Analysis of Location Cache for Low Power Cache System, May

2007.

50. J. Nemeth (MS), Location Cache Design and Performance Analysis for Chip Multiprocessors,

July 2008.

51. S. Prasad (MS), A New Memory Architecture, Nov. 2008.

52. C. Velayutham (MS), A Hybrid Network-on-Chip and Segmented Bus Architecture for

Low-Power CMP Caches, Dec. 2008.

53. D. Ramakrishnan (MS), Design and Analysis of Location Cache in a Network-on-Chip Based

Multiprocessor System, Dec. 2008.

54. K. Renangi (MS), Analysis of Cache Networking by NoC and Segmented Bus, Dec. 2008.

55. D. Shi (MS), Robustness Issues of Runtime Leakage Control in Nano-Scale Technologies, June

2010.

56. H. Xu (PhD), Runtime Leakage Control in Deep Sub-micron CMOS Technologies, Nov. 2010

(co-advisors: Prof. W. B. Jone and Prof. R. Vemuri).

57. Q. Han (MS), An Error-Tolerant Dynamic Voltage Scaling Method for Low-Power Pipeline

Circuit Design, Nov. 2011.

58. G. Jaggnnagri (MS), Bridging and Open Faults Detection in a Two Flip-Flop Synchronizer,

Nov. 2011.

59. J. Liu (PhD), Pseudo-Exhaustive Built-in Self-Testing for Signal Integrity of High-Speed SoC

Interconnects, Nov. 2011.

60. H. K. Kim (PhD), Defect-oriented fault analysis of a two-D-flip-flop synchronizer and test

method for its application, June 2012.

61. S. Velaga (MS), Fault modeling and analysis for multiple-voltage power supplies in low-power

design, Jan. 2013.

62. R. K. Meenakshi Siddharthan (MS), Fault modeling and analysis for FinFET SRAM arrays,

Feb. 2013.

63. J. Liu (MS), Variance validation for post-silicon debugging in network on chip, May 2013.

64. S. Coimbatore Raamanujan (MS), Fault modeling and analysis of LP mode FinFET SRAM

arrays, July 2013.

65. X. Sun, Fault modeling and fault type distinguishing test methods for digital microfluidics chips,

August 2013.

66. K. Parthasarathy (MS), Aging Analysis and Aging-Resistant Design for Low-Power Circuits,

Nov. 2014.

67. S. Nilamboor (MS), A study on Performance Binning in Error Resilient Circuits, Feb. 2015.

68. Q. Han (PhD), On resilient system testing and performance binning, Jan. 2015.

UNIVERSITY SERVICE

Academic Standards and Admissions Committee (1990-1991, NMT)

Chairman of the Academic Standards and Admissions Committee (1991-1992, NMT)

Council of University (1993-1998, NCCU)

DEPARTMENT SERVICE

Graduate Program Coordinator (1988-1989, NMT)

Faculty Search Committee (1988-1990, NMT)

Graduate Curriculum and Exams Committee (1988-1991, NMT)

Graduate Recruiting Committee (1993-1998, NCCU)

Departmental Equipment and Finance Committee (1993-1998, NCCU)

Council of College of Engineering (CS&IE Representative, 1993-1998, NCCU)

Faculty Searching Committee (1993-1998, NCCU)

Director of DQE and Graduate Student Admission (2005 -2010, University of Cincinnati)

PUBLICATIONS

Book Chapters

1. K. T. Cheng, W. B. Jone, and L. T. Wang, “Test Technology Trends in the Nanometer Age,”

Chapter 12, VLSI Test Principles and Architectures, published by Elsevier., L. T. Wang, C. W.

Wu and X. Wen (Editors), ISBN-13: 978-0-12-370597-6, 2006.

2. C. Liu, Krishnendu Chakrabarty and W. B. Jone, “SOC/NOC Test Architectures,”

System-on-Chip Test Architectures: Nanometer Design for Testability, Chapter 4, published

by Elsevier, L. T. Wang, C. Stroud, and N. A. Touba (Editors), ISBN: 978-0-12-373973-5,

2008.

Papers Published in Refereed Journals

1. S. R. Das, W. J. Hsu, Z. Chen and W. B. Jone, "Further studies on the matrix approach to the

measurement and control problems of synchronous sequential machines - performance

evaluation by computer simulation and application of specific heuristics," Computers and

Electrical Engineering, Vol. 12, No. 3/4, pp. 161-173, 1986.

2. S. R. Das and W. B. Jone, "Modified transition matrix and fault testing in sequential logic

circuits under random stimuli with a specified measure of confidence," Cybernetics and

Systems - An International Journal, 17:1-12, 1986.

3. S. R. Das and W. B. Jone and K. W. Chiang, "A first order optimal algorithm for state

identification in sequential logic using the concept of entropy," Cybernetics and Systems - An

International Journal, 18:251-270, 1987.

4. W. B. Jone, M. Pereira and C. A. Papachristou, "A new test scheduling method and its

hardware support," IEEE VLSI Technical Bulletin, Vol. 3, pp. 85-103, Dec. 1988.

5. S. R. Das, W. B. Jone, G. Fares and A. Nayak, "Probabilistic fault location in combinational

logic network using concepts of fault distance and input feature," Cybernetics and Systems -

An International Journal, 20:385-399, 1989.

6. W. B. Jone and S. R. Das, "Multiple-output parity bit signature for exhaustive testing,"

Journal of Electronic Testing: Theory and Applications, Vol. 1, No. 2, pp. 175-178, June

1990.

7. S. R. Das, W. B. Jone and K. L. Wong, "Probabilistic modeling and fault analysis in

sequential logic using computer simulation," IEEE Transactions on Systems, Man and

Cybernetics, Vol. 20, No. 2, pp. 490-498, March/April, 1990.

8. W. B. Jone and S. R. Das, "A space compression method for built-in self-testing of VLSI

circuits," International Journal of Computer Aided VLSI Design, Vol. 3, pp. 309-322, 1991.

9. W. B. Jone and S. R. Das, "An improved analysis on random test length estimation,"

International Journal of Computer Aided VLSI Design, Vol. 3, pp. 393-406, 1991.

10. W. B. Jone and A. Gleason, "Analysis of hamming count compaction scheme," Journal of

Electronic Testing: Theory and Applications, Vol. 2, pp. 373-384, 1991.

11. S. R. Das and W. B. Jone. "On random testing for combinational circuits with a high measure

of confidence," IEEE Trans. on Systems, Man and Cybernetics, Vol. 22, pp. 748-754,

July/August, 1992.

12. W. B. Jone and P. H. Madden, "Multiple faults testing using single test sets for fan-out free

circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,

Vol. 12, pp. 149-157, Jan. 1993.

13. W. B. Jone, "Defect level estimation of circuit testing using sequential statistical analysis,"

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 12, pp.

336-348, Feb. 1993.

14. W. B. Jone and C. J. Wu, "Multiple fault detection of parity checkers," IEEE Trans. on

Computers, Vol. 43, pp. 1096-1099, Sep. 1994.

15. S. R. Das, W. B. Jone, A. R. Nayak and I. Choi, "On testing of sequential machines using

circuit decomposition and stochastic modeling," IEEE Trans. on Systems, Man and

Cybernetics, Vol. 25, No. 3, pp. 489-504, March 1995.

16. W. B. Jone and S. R. Das, "CACOP - a random pattern testability analyzer," IEEE Trans. on

Systems, Man and Cybernetics, Vol. 25, No. 5, pp. 865-871, May 1995.

17. W. B. Jone and C. A. Papachristou, "A coordinated circuit partitioning and test generation

method for pseudo-exhaustive testing of VLSI circuits," IEEE Trans. on Computer-Aided

Design of Integrated Circuits and Systems, Vol. 14, No. 3, pp. 374-384, March 1995.

18. C. L. Fang and W. B. Jone, "Timing optimization by gate resizing and critical path

identification," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems,

Vol. 14, No. 2, pp. 201-217, Februry, 1995.

19. W. B. Jone, P. Gondalia and A. Gutjahr, "Realizing a high measure of confidence for defect

level analysis of random testing," IEEE Trans. on VLSI Systems, Vol. 3, No. 3, pp. 446-450,

Sep. 1995.

20. W. B. Jone and D. Li, "On pseudorandom testability analysis using differential solutions,"

IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 15, No. 7,

pp. 815-825, July 1996.

21. W. B. Jone, N. Shah, A. Gleason and S. R. Das, "PGEN - a novel approach to sequential

circuit test generation," VLSI Design: An International Journal of Custom-Chip Design,

Simulation and Testing, Vol. 4, pp. 149-166, 1996.

22. W. B. Jone, Y. P. Ho, and S. R. Das, "Delay fault coverage enhancement using variable test

observation times," Journal of Electronic Testing: Theory and Applications , Vol. 11, No. 2,

pp. 131-146, Oct. 1997.

23. W. B. Jone and K. S. Tsai, "Confidence analysis for defect level estimation of VLSI random

testing," ACM Trans. on Design Automation of Electronic Systems, vol. 3, issue 3, pp.

389-407, 1998.

24. S. R. Das, N. Goel, W. B. Jone, and A. R. Nayak, “Syndrome signature in output compaction

for VLSI built-in self-test, VLSI Design: An International Journal of Custom-Chip Design,

Simulation and Testing, vol. 7, no. 2, pp. 191-201, June 1998.

25. J. Y. Chen, W. B. Jone, J. S. Wang, H. I. Lu, and T. F. Chen, "Segmented bus design for

low-power systems," IEEE Trans. on VLSI systems, vol. 7, no. 1, pp. 25-29, March 1999.

26. S. C. Chang, W. B. Jone, and S. S. Chang, "TAIR: testability analysis by implication

reasoning," IEEE Trans. on Computer-Aided Design, vol. 19, no. 1, pp. 152-160, Jan. 2000.

27. S. C. Chang, K. J. Lee, Z. Z. Wu, and W. B.Jone, "Reducing test application time by scan

Flip-Flop sharing," IEE proceeding-Computes and Digital Techniques, vol. 147, pp. 42-48,

Jan. 2000.

28. J. C. Rau, W. B. Jone, S. C. Chang, and Y. L. Wu, “A tree-structured LFSR synthesis scheme

for pseudo-exhaustive testing of VLSI circuits,” IEE proceeding-Computes and Digital

Techniques, vol. 147-(5), pp. 343-348, Sep. 2000.

29. C. H. Cheng, W. B. Jone, J. S. Wang, and S. C. Chang, “Low-speed scan testing of

charge-sharing faults for CMOS domino circuits,” IEE Electronic Letters, vol. 36, no. 20,

1684-1685, vol. 36, Sep. 2000.

30. S. C. Chang, C. H. Cheng, W. B. Jone, S. D. Li, and J. S. Wang, “Charge sharing alleviation

and detection for CMOS domino circuits, IEEE Trans. on Computer-Aided Design, vol. 20,

no. 2, pp. 266-280, Feb. 2001..

31. S. C. Chang, K. Y. Chen, C. H. Cheng, W. B. Jone, and S. R. Das, "Random pattern testability

enhancement by circuit rewiring," VLSI Design: An International Journal of Custom-Chip

Design, Simulation and Testing, vol. 12, no. 4, pp. 537-549, Dec. 2001..

32. W. B. Jone, D. C. Huang, S. C. Chang, and S. R. Das, “ A stochastic method for defect level

analysis of pseudorandom testing, “ VLSI Design: An International Journal of Custom-Chip

Design, Simulation and Testing, vol.12, no. 4, pp. 457-474, Dec. 2001.

33. W. B. Jone, W. S. Yeh, C. W. Yeh, and S. R. Das, “An adapted path selection method for delay

testing of digital circuits,” IEEE Trans. on Instrumentation and Measurement, vol. 50, no. 5,

pp. 1109-1118, Oct. 2001.

34. S. R. Das, C. V. Ramamoorthy, M. H. Assaf, E. M., Petriu, and W. B. Jone, “Fault tolerance in

systems design in VLSI using data compression under constraints of failure probabilities,”

IEEE Trans. on Instrumentation and Measurement, vol. 50, no. 6, pp. 1725-1747, Dec. 2001.

35. S. R. Das, M. H. Assaf, E. Petriu, W. B. Jone and K. Chakrabarty, “A novel approach to

designing aliasing-free space comparators based on switching theory formulation,” IEEE

Trans. on Instrumentation and Measurement, vol. 51, no. 4, pp. -. August 2002.

36. D. C. Huang and W. B. Jone, “A parallel built-in self-diagnostic method for embedded

memory arrays,” IEEE Trans. on Computer-Aided Design, vol. 21, no. 4, pp. 449-465, April

2002..

37. D. C. Huang and W. B. Jone, “A parallel transparent BIST method for embedded memory

arrays by tolerating redundant operations,” IEEE Trans. on Computer-Aided Design, vol. 21,

no. 5, pp. 617-628, May 2002.

38. W. B. Jone, D. C. Huang, S. C. Wu, and K. J. Lee, "An efficient BIST method for distributed

small buffers," IEEE Trans. on VLSI Systems, vol. 10, no. 4, pp. 512-515, August 2002.

39. W. B. Jone, J. S. Wang, H. I. Lu, I. P. Hsu, and J. Y. Chen, “Design theory and implementation

for low-power segmented bus systems,” ACM Trans. on Design Automation of Electronic

Systems, vol. 8, no. 1, pp. 38-54, January 2003..

40. W. B. Jone, D. C. Huang, and S. R. Das, “An efficient BIST method for non-traditional faults

of embedded memory arrays,” IEEE Trans. on Instrumentation and Measurement, vol. 52, no.

5, pp. 1381-1390, Oct. 2003.

41. J. H. Jiang, W. B. Jone, S. C. Chang, and S. Ghosh, “Embedded core test generation using

broadcast test architecture and netlist scrambling,” IEEE Trans. on Reliability – Special

section on DFT in VLSI , pp. 435-443, Dec. 2003.

42. V. Arora, W. B. Jone, D. C. Huang, and S. R. Das, “A parallel built-in self-diagnostic method

for non-traditional faults of embedded memory arrays, IEEE Trans. on Instrumentation and

Measurement, pp. 915-932, August 2004..

43. X. Xiong, Y. L. Wu, and W. B. Jone, “A dual-mode built-in self-test technique for capacitive

MEMS devices, “IEEE Trans. on Instrumentation and Measurement, vol. 54, no. 5, pp.

1739-1750, Oct. 2005

44. V. Narayanan, S. Ghosh, W. B. Jone, and S. R. Das, “A built-in self-testing method for

embedded multiport memory arrays, IEEE Trans. on Instrumentation and Measurement, .vol.

54, no. 5, pp. 1720-1738, Oct. 2005.

45. J. Liu, W. B. Jone, and S. R. Das, “Crosstalk test pattern generation for dynamic programmable

logic arrays,” IEEE Trans. on Instrumentation and Measurement, vol. 55, no. 4, pp.

1288-1302, August 2006.

46. W. Pei, W. B. Jone, Y. Hu, “Fault modeling and detection for drowsy SRAM caches,” IEEE

Trans. on Computer-Aided Design, vol. 26, no. 6, pp. 1084-1100, June 2007.

47. X. Xiong, Y. L. Wu, and W. B. Jone, “Yield analysis for self-repairable MEMS devices,”

Analog Integrated Circuits and Signal Processing, vol. 56, no. 1-2, pp. 71-81, August 2008.

48. L. T. Wang, R. Apte, S. Wu, B. Sheu, K. J. Lee, X. Wen, W. B. Jone, C. H. Yeh, W. S.

Wang, H. J. Chao, J. Guo, J. Liu, Y. Niu, Y. C. Sung, C. C. Wang, and F. Li, “Turbo1500:

core-based design for test and diagnosis using the IEEE 1500 standard,” IEEE Design &

Test, vol. 26, issue 1, pp.26-35, Jan.-Feb. 2009.

49. L. T. Wang, X. Wen, S. Wu, H. Furukawa, H. J. Chao, B. Sheu, J. Guo, W. B. Jone, “Using

launch-on-capture for testing BIST designs containing synchronous and asynchronous clock

domains,” IEEE Trans. on Computer-Aided Design of Integrated Circuits, vol. 29, no. 2, pp.

299-312, Feb. 2010.

50. H. K. Kim, W. B. Jone, and L. T. Wang, “Fault modeling and analysis for resistive bridging

defects in a synchronizer,” Journal of Electronic Testing: Theory and Applications, vol. 26, pp.

367-392, 2010.

51. D. Ramakrishnan, Y. L. Wu and W. B. Jone, “Design and analysis of location cache in a

NoC-based chip multiprocessor system,” Journal of Low Power Electronics, vol. 6, no. 2, pp.

1-23, Sep. 2010.

52. Hao Xu, Wen-Ben Jone, Ranga Vemuri, “Tuning Vth hopping for aggressive runtime leakage

control,” Journal on Low Power Electronics, INVITED PAPER, vol. 6, no. 3 , October 2010.

53. J. Nemeth, R. Min, W. B. Jone, and Y. Hu, “Location cache design and performance

analysis for chip multiprocessors,” IEEE Trans. on VLSI Systems, vol. 19, pp. 104-117,

Jan. 2011.

54. H. Xu, R. Vemuri, and W. B. Jone, “Dynamic characteristics of power gating during mode

transition,” IEEE Trans. on VLSI Systems, vol. 19, pp.237-249, Feb. 2011.

55. H. Xu, R. Vemuri, and W. B. Jone, “Aggressive runtime leakage control through

light-weight Vth hopping with temperature and process variation,” IEEE Trans. on VLSI

Systems, vol. 19, no. 7, pp.1319-1323, July 2011.

57. S. Wu, L. T. Wang, X. Wen, Z. Jiang, L. Tan, Y. Zhang, Y. Hu, W. B. Jone, M. S. Hsiao, C.

M. Li, J. L. Huang and L. Yu, “Using launch-on-capture for testing scan designs containing

synchronous and asynchronous clock domains,” IEEE Trans. on Computer-Aided Design of

Integrated Circuits, vol. 30, no. 3, pp. 455-463, March 2011.

59. H. K. Kim, L.T. Wang, Y. L. Wu and W. B. Jone, "Testing of synchronizers in asynchronous

FIFO," Journal of Electronic Testing: Theory and Applications, vol. 29, issue 1, pp. 49-72,

Feb. 2013.

60. H. M. Chou, M. Y. Hsiao, Y. C. Chen, K. H. Yang, J. Tsao, S. C. Chang, W. B. Jone, and T.

F. Chen, “Soft-error tolerant design methodology for balancing performance, power and

reliability,” IEEE Trans. on VLSI Systems, vol. 23, no. 9, pp. 1628-1639, Sep. 2015.

61. H. M. Chou, K. H. Yang, Y. C. Chen, P. Z. Huang, J. Tsao, S. C. Chang, W. B. Jone, and T.

F. Chen, “High-performance deadlock-free ID assignment for advanced interconnect

protocols”, IEEE Trans. on VLSI Systems, vol. 24, no. 3, pp. 1169-1173, March 2016.

62. Y. C. Peng, C. C. Chen, K. J. Tsai, K. H. Yang, P. Z. Huang, S. C. Chang, W. B. Jone, and T.

F. Chen, “Leak Stopper: an actively revitalized snoop filter architecture with effective

generation control,” ACM Trans. on Design Automation of Electronics Systems, vol. 22, no.

3, May 2017.

63. Q. Han, Q. Xu, and W. B. Jone, “SERA: statistical error rate analysis for profit-oriented

performance binning of resilient circuits,” VLSI Integration, vol. 60, pages 1-12, Jan. 2018.

Refereed Conferences and Symposia

1. S. R. Das, W. B. Jone et. al., "Fault location in combinational logic networks by multistage

binary tree classifier," IEEE International Conference on Circuits and Computers, New York,

U. S. A., Sep. 28 - Oct. 1, 1982 (Proceeding pp. 624-628).

2. S. R. Das and W. B. Jone, "Digital signature analysis in circuit fault detection," Presented at

the National Seminar on Microwave Integrated Circuits, Communications and Signal

processing (MICCASP), Osmania University, Hyderabad, India, Dec. 17-18, 1984

( Conference Proceedings, pp. A79-A81 ) – Invited contribution.

3. S. R. Das, W. B. Jone and K. W. Chiang, "On an approach to finding the state identification

58. S. Wu, L. T. Wang, X. Wen, W. B. Jone, M. S. Hsiao, F. Li, J. Li, and J. L. Huang,

“Launch-on-shift test generation for testing scan designs containing synchronous and

asynchronous clock domains,” ACM Trans. on Design Automation of Electronic Systems,"

vol. 17, no. 4, Article 48, pp. 48-1 - 48-16, October, 2012.

sequences in sequential machines using the concept of entropy," Presented at the International

Computer Symposium, Tamkang University, Taipei, Republic of China, Dec 12-14, 1984

( Symposium Proceedings, Vol. 2, pp. 1141-1147 ).

4. S. R. Das and W. B. Jone, "Modified transition matrix and fault testing in sequential logic

circuits under random stimuli with a specified measure of confidence," Presented at the

International Conference on Computers, systems and Signal Processing, Bangalore, India,

Dec 9-12, 1984 (Conference Proceedings, Vol. 2, pp. 707-711).

5. S. R. Das, W. B. Jone and Z. Chen, "Realizing a high measure of confidence in random test

generation for irredundant combinational logic networks," Presented at the International

Computer Symposium, Taichung, Taiwan, Republic of China, Dec. 15-17, 1982 ( Symposium

Proceedings, Vol. 2, pp. 905-914 ).

6. S. R. Das, W. B. Jone and Z. Chen, "Digital signature analysis and fault testing in

microprocessor-based systems," Presented at the Golden Jubilee Conference on advances in

Information Science and Technology, Indian Statistical Institute, Calcutta, India, Jan. 11-14,

1982 ( Conference Abstracts, P. - ) - Invited contribution.

7. S. R. Das, W. J. Hsu, Z. Chen and W. B. Jone, "Further studies on the matrix approach to the

measurement and control problems of synchronous sequential machines - performance

evaluation by computer simulation and application of specific heuristics," Presented at the

International Computer Symposium, Taipei, Republic of China, Dec. 16-18, 1980

( Symposium Proceedings, Vol. 2, pp. 1312-1324 ).

8. S. R. Das, W. B. Jone, Z. Chen and S. Y. Lee, "Analysing the behavior of sequential logic

circuits under random stimuli using the concept of modified transition matrix and fault testing

with a specified degree of confidence", 16th Asilomar Conference on Circuits, Systems, and

Computers, Pacific Grove, California, U. S. A., Nov. 8-10, 1982 (accepted but not

presented).

9. S. R. Das, Z. Chen and W. B. Jone, "Random test generation for irredundant combinational

logic networks with a high measure of confidence", Real-Time Systems Symposium, Miami

Beach, Flo, U. S. A., Dec. 8-10, 1981 (accepted but not presented).

10. C. A. Papachristou and W. B. Jone, "On test pattern selection of VLSI," IASTED International

Conference on Reliability and Control, Paris, France, June 24-26, 1987. - Invited Contribution.

11. S. R. Das, W. B. Jone and W. L. Wong, "Probabilistic modeling and fault analysis in sequential

logic using computer simulation," IASTED International Conferences on Computer-aided

Design and Applications, and Applied Simulation and Modeling, Vancouver, BC, Canada,

June 1986 (Proceeding pp. 87-93).

12. W. B. Jone, S. R. Das and C. A. Papachristou, "Derivation of minimum vertex cut and its

application in VLSI testing," Accepted by 1988 International Computer Symposium.

13. C. A. Papachristou and W. B. Jone, "Partitioning and pseudoexhaustive BIST of VLSI

circuits," 1988 TECHCON, Sponsored by Semiconductor Research Corporation, (Proceeding

pp. 160-163).

14. W. B. Jone and C. A. Papachristou, "Is overlaying concurrent testing worthwhile ?,"The 11th

Annual IEEE Workshop on Design for Testability, April 1988.

15. W. B. Jone and C. A. Papachristou, "Methodology for parallel testing of VLSI circuits based

on partitioning and built-in self-testing techniques," The 6th IEEE Built-In Self-Test

Workshop, March 1988.

16. W. B. Jone and C. A. Papachristou, "On partitioning for pseudo exhaustive testing of VLSI

circuits," 21th IEEE International Symp. on Circuits and Systems, Espoo, Finland, June 7-9,

1988 (Proceedings, Vol. 2, PP. 1843-1846).

17. W. B. Jone and S. R. Das, "Multiple-output parity bit signature generation for exhaustive

testing," 1989 IASTED International Symp. On Reliability and Quality Control, June 1989.

18. A.Gleason and W. B. Jone, "Hamming count - a compaction testing technique," IEEE

International Conference on Computer Design, October 1989 (Proceeding pp. 344-347).

19. W. B. Jone, C. A. Papachristou and M. Pereira, "A scheme for overlaying concurrent testing of

VLSI circuits," 26th ACM/IEEE Design Automation Conference, June 1989 (Proceeding pp.

531-536).

20. W. B. Jone and C. A. Papachristou, "A coordinated approach to partitioning and test pattern

generation for pseudoexhaustive testing," 26th ACM/IEEE Design Automation Conference,

June 1989 (Proceeding pp. 525-530).

21. A. Gleason and W. B. Jone, "Counter reduction techniques for hamming count," Fifth New

Mexico Computer Science Conference, April 1990 (Proceeding pp. 36-63).

22. W. B. Jone, "Defect level analysis of random and pseudorandom testing," 21th International

Test Conference, October 1990 (poster section).

23. W. B. Jone, "DSC - a space compression method," 23th IEEE International Symp. On Circuits

and Systems, May 1990 (Proceeding pp. 2756-2759).

24. A. Gleason and W. B. Jone, "Reduced hamming count and its aliasing probability," IEEE

International Conference on Computer Design, October, 1991 (Proceeding pp. 356-359).

25. A. Gleason and W. B. Jone, "Counter reduction techniques for hamming count," 24th IEEE

International Symp. on Circuits and Systems, 1991 (Proceeding pp. 1980-1983).

26. W. B. Jone, "Defect level estimation of random and pseudorandom testing," 22th International

Test Conference, Nov. 1991, (Proceeding pp. 712-721).

27. P. Gondalia, A. Gutjahr and W. B. Jone, "Realizing a high measure of confidence for defect

level analysis of random testing," 24th International Test Conference, Oct. 1993 (Proceeding

pp. 478-487).

28. W. B. Jone and C. L. Fang, "Timing optimization by gate resizing and critical path

identification," 30th ACM/IEEE Design Automation Conference, June 1993 (Proceeding pp.

135-140).

29. W. J. Wu and W. B. Jone, "On multiple fault detection of parity checkers," 26th International

Symposium on Circuits and Systems, May 1993 (Proceeding pp. 1515-1518).

30. P. Gondalia, A. Gutjahr and W. B. Jone, "Realizing a high measure of confidence for defect

level analysis of random testing," 4th VLSI Design/CAD Workshop, August 1993 (Proceeding

pp. 221-225).

31. W. B. Jone and S. R. Das, "CACOP - a random pattern testability analyzer," 6th International

Conference on VLSI Design, January 1993 (Proceeding pp. 61-64).

32. S. R. Das, H. T. Ho and W. B. Jone, "Modified dynamic space compression for built-in

self-testing of VLSI circuits, 37th Midwest Symp. on Circuits and Systems, August, 1994

(Proceeding 217-224).

33. S. R. Das, W. B. Jone, A. R. Nayak and I. Choi, "On probabilistic testing of large-scale

sequential circuits using circuit decomposition," 7th International Conference on VLSI Design,

January 1994 (Proceeding 311-314).

34. A. R. Nayak, W. B. Jone, and S. R. Das, "Designing general-purpose fault-tolerant distributed

systems - a layered approach," 1994 International Conf. on Parallel and Distributed Systems,

December 1994 (Proceeding 360-364).

35. S. R. Das, H. T. Ho, W. B. Jone, and A. R. Nayak, "An improved output compaction technique

for built-in self-test in VLSI circuits," 8th International Conference on VLSI Design, January

1995 (Proceeding 403-407).

36. S. R. Das, N. Goel, and W. B. Jone, "Syndrome signature in output compaction for VLSI

BIST," 9th International Conference on VLSI Design, January 1996 (Proceeding 337-338).

37. J. C. Rau and W. B. Jone, "A tree-structured LFSR synthesis scheme for pseudo-exhaustive

testing of VLSI circuits," The 7th VLSI Design/CAD Symposium, August 1996 (Proceeding

69-72).

38. W. B. Jone, Y. P. Ho, and S. R. Das, "Delay fault coverage enhancement using multiple test

observation times," The 10th International Conference on VLSI Design, January 1997

(Proceeding 106-110).

39. S. R. Das, A. R. Nayak, M. H. Assaf, and W. B. Jone, "Realizing ultimate compression with

acceptable fault coverage degradation to reduce MISR size in BIST applications by

nonexhaustive test patterns," 1997 International Symp. on Circuit and Systems, June 1997

(Proceeding 2717-2720).

40. C. W. Yeh, M. C. Chang, S. C. Chang, W. B. Jone and J. S. Wang, "Reducing power

consumption by iterative gate sizing and voltage scaling," 8th VLSI Design/CAD Symposium,

August 1997 (Proceeding 281-283).

41. W. B. Jone and S. R. Das, "A stochastic method for defect level analysis of pseudorandom

testing," 11th International Conference on VLSI Design, January 1998 (Proceeding 382-385).

42. S. C. Chang, S. S. Chang, W. B. Jone, and C. C. Tsai, "A novel testability analysis by

considering signal correlation," International Test Conference, October 1998 (Proceeding pp.

322-330).

43. W. B. Jone, J. C. Rau, S. C. Chang, and Y. L. Wu, "A tree-structured LFSR synthesis scheme

for pseudo-exhaustive testing of VLSI circuits," International Test Conference, October 1998

(Proceeding pp. 658-667).

44. S. C. Chang, K. Y. Chen, W. B. Jone, and S. R. Das, "Random pattern testability enhancement

by circuit rewiring," International Conference on VLSI Design, January 1999 (Proceeding pp.

T9.4).

45. W. B. Jone, D. C. Huang, S. C. Wu, and K. J. Lee, "An efficient BIST method for distributed

small buffers," 17th IEEE VLSI Test Symposium, 1999 (Proceeding pp. 246-251).

46. C. W. Yeh, M. C. Chang, S. C. Chang, and W. B. Jone, "Gate-level design exploiting dual

supply voltages for power-driven applications," ACM/IEEE Design Automation Conference,

1999 (Proceeding pp. 68-71).

47. C. H. Cheng, S. C. Chang, J. S. Wang, and W. B. Jone, "Charge sharing fault detection for

CMOS domino logic circuits," International Symp. on Defect and Fault Tolerance in VLSI

Systems, 1999 (Proceeding pp. 77-85).

48. W. B. Jone, W. S. Yeh, C. W. Yeh, and S. R. Das, “An adapted path selection method for delay

testing of digital circuits,” IEEE Instrumentation and Measurement Technology Conference,

May 2000 (pp. 212-216).

49. S. R. Das, J. Liang, E. M. Petriu, W. B. Jone, and K. Charkrabarty, “Data compression in space

under generalized mergeability based on concepts of cover table and frequency ordering,”

IEEE Instrumentation and Measurement Technology Conference, May 2000 (pp. 217-222).

50. C. H. Cheng, J. S. Wang, S. C. Chang, and W. B. Jone, “Charge sharing fault analysis and

testing for CMOS domino circuits,” First IEEE Latin-American Test Workshop, June 2000

(Proceeding pp. 59-64).

51. C. H. Cheng, W. B. Jone, J. S. Wang, and S. C. Chang, “Low-speed scan testing of

charge-sharing faults for CMOS domino circuits,” International Symp. on Defect and Fault

Tolerance in VLSI Systems, 2000 (Proceeding pp. 329-337).

52. S. C. Chang, C. H. Cheng, W. B. Jone, S. D. Lee, and J. S. Wang, “Synthesis of CMOS

domino circuits for charge sharing alleviation,” International Conference on Computer-Aided

Design, 2000 (Proceeding pp. 387-391).

53. D. C. Huang and W. B. Jone, “An efficient parallel transparent diagnostic BIST,” Asian Test

Symposium, 2000 (Proceeding pp. 299-303).

54. C. H. Cheng, W. B Jone, S. C. Chang, and J. S. Wang, “Charge sharing fault analysis and

testing for CMOS domino logic,” Asian Test Symposium, 2000 (Proceeding pp. 435-440).

55. D. C. Huang, W. B. Jone, and S. R. Das, “An efficient parallel transparent BIST method for

multiple embedded memory buffers,” International Conference on VLSI Design, 2001

(Proceeding pp. 379-384).

56. D. C. Huang, W. B. Jone, and S. R. Das, “A parallel built-in self-diagnostic method for

embedded memory buffers,” International Conference on VLSI Design, 2001 (Proceeding pp.

397-402).

57. S. R. Das, M. H. Assaf, E. M. Petriu, W. B. Jone, and K. Chakrabarty, “A novel approach to

designing aliasing-free space compactors based on switching theory formulation using a new

probability measure under generalized mergeability,” IEEE Instrumentation and Measurement

Technology Conference, pp. 198-203, May 2001.

58. J. H. Jiang, W. B. Jone, and S. C. Chang, “Embedded core testing using broadcasting test

architecture,” International Symp. on Defect and Fault Tolerance in VLSI Systems, pp. 95-103,

Oct. 2001.

59. W. B. Jone, D. C. Huang, and S. R. Das, “An efficient BIST method for non-traditional faults

of embedded memory arrays,” IEEE Instrumentation and Measurement Technology

Conference, pp. 601-606, May 2002.

60. S. R. Das, M. H. Assaf, E. M. Petriu and W. B. Jone, “Fault simulation and response

compaction in full scan circuits using HOPE,” IEEE Instrumentation and Measurement

Technology Conference, pp. 607-612, May 2002.

61. V. Arora, W. B. Jone, D. C. Huang, and S. R. Das, “A parallel built-in self-diagnostic method

for non-traditional faults of embedded memory arrays,” IEEE Instrumentation and

Measurement Technology Conference, pp. 700-706, May 2003.

62. S. R. Das, M. H. Assaf, E. M. Petriu and W. B. Jone, “Revisiting response compaction in space

for full scan circuits with non-exhaustive test sets using concept of sequence characterization,”

IEEE Instrumentation and Measurement Technology Conference, pp. 693-699, May 2003.

63. R. Min, Z. Xu, Y. Hu, and W. B. Jone, “Partial tage compression: a new technology for

power-efficient set-associative cache designs,” International Conference on VLSI Design, pp.

183-188, Jan. 2004.

64. V. Narayanan, S. Ghosh, W. B. Jone, and S. R. Das, “A built-in self-testing method for

embedded multiport memory arrays,” IEEE Instrumentation and Measurement Technology

Conference, .vol. 3, pp. 2007-2032, 2004.

65. X. Xiong, Y. L. Wu, and W. B. Jone, “A dual-mode built-in self-test technique for capacitive

MEMS devices,” 22nd IEEE VLSI Test Symposium, pp.148-153, 2004.

66. R. Min, Y. Hu, and W. B. Jone, “Location cache: a low-power L2 cache system,” ACM/IEEE

International Symposium on Low Power Electronics and Design, pp. 120-125, 2004.

67. R. Min; W. B. Jone; Y. Hu, “Phased tag cache: an efficient low power cache system,”

International Symp. on Circuits and Systems, pp. II- 805-8 Vol.2, May 2004.

68. S. Ghosh, K. W. Lai, W. B. Jone, S. C. Chang, “Scan chain fault identification using

weight-based codes for SoC circuits,” Asian Test Symposium, pp. 210-215, Nov. 2004.

69. C. H. Lin, Y. C. Huang, S. C. Chang, and W. B. Jone, “Design and design automation of

rectification logic for engineering change,” Asia South Pacific Design Automation Conference,

pp. 1006-1009, 2005.

70. X. Xiong, Y. Wu, and W. B. Jone, "Design and analysis of self-repairable MEMS

accelerometer," Proceedings of IEEE International Symposium on Defect and Fault Tolerance

in VLSI Systems (DFT'05), pp.21-29, 2005.

71. X. Xiong, Y. Wu, and W. B. Jone, “Yield analysis for self-repairable MEMS devices,”

Proceedings of Midwest Symposium on Circuits and Systems, pp. 359-362, 2005.

72. J. Liu, W. B. Jone, and S. R. Das, “Crosstalk test pattern generation for dynamic programmable

logic arrays,” Proceedings of IEEE Instrumentation and Measurement Technology

Conference,” pp. 55-60, 2005.

73. M. Li, W. B. Jone, and Q. Zeng, “An efficient wrapper scan chain configuration method for

network-on-chip testing,” Proceedings of IEEE Computer Society Annual Symp. on VLSI, pp.

147-152, 2006.

74. R. Martin, W. B. Jone, and S. R. Das, “Fault detection and diagnosis for multi-level cell flash

memories,” Proceedings of IEEE Instrumentation and Measurement Technology Conference,

pp. 1896-1901, 2006.

75. M. Li, W. B. Jone, and Q. Zeng, “DyXY - A proximity congestion-aware deadlock-free

dynamic routing algorithm for network on chip,” Proceedings of Design Automation

Conference, pp. 849-852, 2006.

76. W. Pei, W. B. Jone, Y. Hu, “Fault modeling and detection for drowsy SRAM caches,” Proc. of

International Test Conference, Oct. 2006.

77. X. Xiong, Y. Wu, and W. B. Jone, “Reliability analysis of self-repairable MEMS accelerometer,”

Proceedings of IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

(DFT'06), pp. 236-244, 2006.

78. J. Liu, W. B. Jone, and S. R. Das, “Pseudo-Exhaustive Built-in Self-Testing of Signal Integrity

for High-Speed SoC Interconnects,” Proceedings of IEEE Instrumentation and Measurement

Technology Conference (Accepted for publication).

79. J. Liu and W. B. Jone, “An efficient routing method for pseudo-exhaustive built-in self-testing

of high-speed interconnects,” IEEE International Conference on Computer Design, pp.

360-367, 2007.

80. H. Xu, R. Vemuri, and W. B. Jone, “Dynamic virtual ground voltage estimation for power

gating,” Proc. of International Symposium for Low-Power Electronics and Design, pp. 27-32,

2008.

81. H. Xu, W. B. Jone and R. Vemuri, “Accurate energy breakeven time estimation for

run-time power gating,” Proc. of International Conference on Computer-Aided Design, pp.

161-168, 2008.

82. X. Xiong, Y. L. Wu and W. B. Jone, “Material fatigue and reliability of MEMS

accelerometers,” Proc. of IEEE International Symposium on Defect and Fault Tolerance in

VLSI Systems, pp. 314-322, 2008.

83. L. T. Wang, R. Apte, S. Wu, B. Sheu, K. J. Lee, X. Wen, W. B. Jone, C. H. Yeh, J. Guo, J. Liu,

and Y. C. Sung, “Turbo1500: toward core-based design for test and diagnosis using IEEE Std.

1500,” Proc. of International Test Conference, paper 29.3, 2008.

83. H. Xu, R. Vemuri, and W. B. Jone, ” Run-time active leakage reduction by power gating and

reverse body biasing: an energy view,” Proc. of IEEE International Conference on Computer

Design, 618-625, 2008.

84. H. Xu, R. Vemuri, and W. B. Jone, ”Selective light Vth hopping (SLITH): bridging the gap

between run-time dynamic and leakage power reduction,” Proc. of Design Automation and Test

in Europe, 594-597, 2009.

85. H. K. Kim, W. B. Jone, and L. T. Wang, “Analysis of resistive open defects in a synchronizer,”

Proc. of IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp.

164-172, 2009.

86. H. K. Kim, W. B. Jone, L. T. Wang, and S. Wu, “Analysis of resistive bridging defects in a

synchronizer,” Proceedings of Asian Test Symposium, 443-449, 2009.

87. H. Xu, R. Vemuri, and W. B. Jone, “Temporal and spatial circuit clustering for

optimum-grained leakage control by reverse body biasing,” Proc. of International Conference

on Computer-Aided Design, pp. 468-473, 2009.

88. H. Xu, R. Vemuri, and W. B. Jone, “Stretching the limit of microarchitectural level leakage

control with adaptive light-weight Vth hopping,” Proc. of International Conference on

Computer-Aided Design, pp. 632-636, 2010.

89. H. Xu, R. Vemuri, and W. B. Jone, “Current shaping and multi-thread activation for fast and

reliable power mode transition in multicore designs,” Proc. of International Conference on

Computer-Aided Design, 637-641, 2010.

90. S. Wu, L. T. Wang, L. Yu, H. Furukawa, X. Wen, W. B. Jone, N. A. Touba, F. Zhao, J. Liu, H. J. Chao, F.

Li, and Z. Jiang, “Logic BIST architecture using staggered launch-on-shift for testing designs

containing asynchronous clock domains,” Proc. of IEEE International Symposium on Defect

and Fault Tolerance in VLSI Systems, pp. 358-368, 2010.

91. S. Y. Chen, C. N. Wen, W. B. Jone, and T. F. Chen, “IMITATOR: A deterministic multicore replay

system with refining techniques,” Proc. of International Symp. on VLSI Design, Automation & Test , pp.

1-4, Digital Object Identifier: 10.1109/VLSI-DAT.2012.6212625 , 2012.

92. F. Yuan, Y. Liu, W. B. Jone, and Q. Xu, "On testing timing-speculative circuits," Proc. of

ACM/IEEE Design Automation Conference 2013.

93. R. Ye, F. Yuan, Z. Sun, W. B. Jone, and Q. Xu, "Post-placement voltage island generation for

timing-speculative circuits," Proc. of ACM/IEEE Design Automation Conference, 2013.

94. Q. Han, J. Guo, W. B. Jone, and Q. Xu, "Path delay testing in resilient system," Proc. of IEEE

56th International Midwest Symp. on Circuits and Systems, 2013.

95. J. Guo, Q. Han, W. B. Jone, and Y. L. Wu, "A cross-layer fault-tolerant design method for high

manufacturing yield and system reliability," Proc. of IEEE International Symposium on Defect

and Fault Tolerance in VLSI Systems, 2013.

96. S. Y. Chen, M. Y. Hsiao, W. B. Jone and T. F. Chen, “A configurable bus-tracer for error

reproduction in post-silicon validation,” Proc. of International Symp. on VLSI Design,

Automation & Test, 2013.

97. T. K. Lam, X. Wei, W. B. Jone, Y. Diao and Y. L. Wu, “On Macro-Fault: A New Fault Model,

Its Implications On Fault Tolerance And Manufacturing Yield,” Prof. of Great Lakes

Symposium on VLSI, 2014.

98. Q. Han, J. Guo, Q. Xu, and W. B. Jone, “On Resilient System Performance Binning,”

Proceedings of International Symp. On Physical Design, pp. 119-125, March 2015.