what can fpga designers do with personal data centers?
DESCRIPTION
These are the slides presented by Plunify during the event, "Accelerate Time-To-Market Using Cloud Computing", held on 14th Oct 2011, organized by the Singapore Semiconductor Industry Association.TRANSCRIPT
Cloud Computing for Chip Design
“What Can FPGA Designers Do With Personal Data Centers?”
Harnhua Ng, Plunify Pte Ltd October 14, 2011
Agenda
Page § 2
§ FPGA Design Data Center § Specific Areas of Note
§ FPGA Timing Closure § Current Approach § Demonstration § Cloud Approach
§ Going Forward
“Personal Data Center for FPGA Design”
Page § 3
Simulation
Routing/ Synthesis
Page § 4
Confidentiality, Ease of Use Precedents: Foundry <-> foundry customer interaction
• Secure and Encrypted End-to-End Transfers • Plugins to Existing Tools • Distributed File Uploads / Downloads
Audited Security Standards § AES encryption
§ SSL transmission § Asymmetric keys
Page § 5
FPGA Timing Closure
“Timing Experiments”
§ Case 1: Miss timing by a bit
§ Change a setting, repeat till successful
§ Case 2 : Timing is way off
§ Back to drawing board – path restructuring, pipelining etc.
Drawbacks - Takes time to re-iterate one at a time - Usually at a later design stage - Randomness: *Fingers crossed* - Requires communication between “tools
people” and “design people”
Costly Delays
N hrs per iteration M iterations
Total: N x M hours
≈ days, weeks…
Current Limitations
Page § 6
§ Run iterations in parallel § Save time wasted from waiting for
each iteration
§ Save time on re-engineering the design
§ Use generated results from iterations to troubleshoot better
Data Center Approach
N hrs per iteration Total: N hours
X servers
Cloud Closure
Design – OR1200 32-bit processor core
Page § 7
§ 32-bit RISC § Harvard architecture § 5-stage pipeline § Virtual memory § Basic DSP capabilities § Implemented in various
commercial ASICs & FPGAs
Target Chip & Software
Page § 8
§ Altera Stratix III L50 § 65-nm technology § Logic elements: 47.5K § Package: F780 § Speed Grade: Commercial 2
§ Altera Quartus II § Version 10.0 SP1
Timing Problem
Page § 9
Timing Aspect Slack (ns) Worst Setup Time -0.519
Page § 10
• Calculate various parameters § “Seeds”
§ Placement optimizations
§ Routing optimizations
§ Register-to-register timing
§ Effort levels
§ Schedule and run in parallel
Run in Parallel
Multiple parallel runs
Cloud Approach
Result: Timing Solutions Found
Page § 11
Set Timing Aspect Slack (ns) 19 Worst Setup Time 0.093 26 Worst Setup Time 0.011
Cloud Compile - Cloud Collab
Page § 12
EDAxtend Platform
• Sigasi HDT • TransEDA
Design Entry
Complete design tool flow
Simulate
• Aldec Riviera Pro • Mentor Graphics Modelsim
Synthesis
• Altera Quartus II
Place and
Route
• Altera Quartus II
Timing/ Power
Analysis
• Altera Quartus II
Design Rule
Checking
• Magma • Simucad
Cloud Explore Cloud Closure
Cloud Test
IP Libraries
§ Support more FPGA processes § IP cores § Complementary tasks e.g. multi-vendor flows
§ Extend features to broader EDA tasks § E.g. Simulator,
DFM, Verification tools
Next Steps
Page § 13
§ Web account: register at www.plunify.com
§ Desktop plugin: contact us at [email protected]
§ What would you like to see in the cloud?
Test Drive & Feedback
Page § 14
§ Secure, easy to use § Demo: Timing closure
§ Shorten Time-To-Market
§ Reduce overheads and development costs
Cloud-Accelerated FPGA Design
Page § 15