william stallings computer organization and a hit td
TRANSCRIPT
![Page 1: William Stallings Computer Organization and A hit td](https://reader033.vdocument.in/reader033/viewer/2022060104/629276296323f3763a1e0267/html5/thumbnails/1.jpg)
William Stallings William Stallings Computer Organization
d A hit tand Architecture
Chapter 16Parallel ProcessingParallel Processing
![Page 2: William Stallings Computer Organization and A hit td](https://reader033.vdocument.in/reader033/viewer/2022060104/629276296323f3763a1e0267/html5/thumbnails/2.jpg)
Multiple Processor OrganizationMultiple Processor Organization
Single instruction, single data stream - SISDSingle instruction, multiple data stream - SIMDMultiple instruction, single data stream - MISDMultiple instruction, multiple data stream- MIMD
![Page 3: William Stallings Computer Organization and A hit td](https://reader033.vdocument.in/reader033/viewer/2022060104/629276296323f3763a1e0267/html5/thumbnails/3.jpg)
Single Instruction, Single Data Stream SISDStream - SISD
Single processorSingle instruction streamData stored in single memoryUni-processor
![Page 4: William Stallings Computer Organization and A hit td](https://reader033.vdocument.in/reader033/viewer/2022060104/629276296323f3763a1e0267/html5/thumbnails/4.jpg)
Single Instruction, Multiple Data Stream SIMDData Stream - SIMD
Single machine instruction Controls simultaneous executionNumber of processing elementsLockstep basisEach processing element has associated data memoryEach instruction executed on different set of data by different processorsVector and array processors
![Page 5: William Stallings Computer Organization and A hit td](https://reader033.vdocument.in/reader033/viewer/2022060104/629276296323f3763a1e0267/html5/thumbnails/5.jpg)
Multiple Instruction, Single Data Stream MISDData Stream - MISD
Sequence of dataTransmitted to set of processorsEach processor executes different instruction sequenceNever been implemented
![Page 6: William Stallings Computer Organization and A hit td](https://reader033.vdocument.in/reader033/viewer/2022060104/629276296323f3763a1e0267/html5/thumbnails/6.jpg)
Multiple Instruction, Multiple Data Stream MIMDData Stream- MIMD
Set of processorsSimultaneously execute different instruction sequencesDifferent sets of dataSMPs, clusters and NUMA systems
![Page 7: William Stallings Computer Organization and A hit td](https://reader033.vdocument.in/reader033/viewer/2022060104/629276296323f3763a1e0267/html5/thumbnails/7.jpg)
Taxonomy of Parallel Processor ArchitecturesArchitectures
![Page 8: William Stallings Computer Organization and A hit td](https://reader033.vdocument.in/reader033/viewer/2022060104/629276296323f3763a1e0267/html5/thumbnails/8.jpg)
MIMD OverviewMIMD - Overview
General purpose processorsEach can process all instructions necessaryFurther classified by method of processor communication
![Page 9: William Stallings Computer Organization and A hit td](https://reader033.vdocument.in/reader033/viewer/2022060104/629276296323f3763a1e0267/html5/thumbnails/9.jpg)
Tightly Coupled SMPTightly Coupled - SMP
Processors share memoryCommunicate via that shared memorySymmetric Multiprocessor (SMP)
Share single memory or poolShared bus to access memoryMemory access time to given area of memory is approximately the same for each processorapproximately the same for each processor
![Page 10: William Stallings Computer Organization and A hit td](https://reader033.vdocument.in/reader033/viewer/2022060104/629276296323f3763a1e0267/html5/thumbnails/10.jpg)
Tightly Coupled NUMATightly Coupled - NUMA
Nonuniform memory accessAccess times to different regions of memroy may differ
![Page 11: William Stallings Computer Organization and A hit td](https://reader033.vdocument.in/reader033/viewer/2022060104/629276296323f3763a1e0267/html5/thumbnails/11.jpg)
Loosely Coupled ClustersLoosely Coupled - Clusters
Collection of independent uniprocessors or SMPsInterconnected to form a clusterCommunication via fixed path or network connections
![Page 12: William Stallings Computer Organization and A hit td](https://reader033.vdocument.in/reader033/viewer/2022060104/629276296323f3763a1e0267/html5/thumbnails/12.jpg)
Parallel Organizations SISDParallel Organizations - SISD
![Page 13: William Stallings Computer Organization and A hit td](https://reader033.vdocument.in/reader033/viewer/2022060104/629276296323f3763a1e0267/html5/thumbnails/13.jpg)
Parallel Organizations SIMDParallel Organizations - SIMD
![Page 14: William Stallings Computer Organization and A hit td](https://reader033.vdocument.in/reader033/viewer/2022060104/629276296323f3763a1e0267/html5/thumbnails/14.jpg)
Parallel Organizations - MIMD Shared MemoryShared Memory
![Page 15: William Stallings Computer Organization and A hit td](https://reader033.vdocument.in/reader033/viewer/2022060104/629276296323f3763a1e0267/html5/thumbnails/15.jpg)
Parallel Organizations - MIMDDistributed MemoryDistributed Memory
![Page 16: William Stallings Computer Organization and A hit td](https://reader033.vdocument.in/reader033/viewer/2022060104/629276296323f3763a1e0267/html5/thumbnails/16.jpg)
Symmetric MultiprocessorsSymmetric MultiprocessorsA stand alone computer with the following characteristics
Two or more similar processors of comparable capacityProcessors share same memory and I/OProcessors share same memory and I/OProcessors are connected by a bus or other internal connectionMemory access time is approximately the same for each processorprocessorAll processors share access to I/O⌧Either through same channels or different channels giving paths to
same devicessame devices
All processors can perform the same functions (hence symmetric)S t t ll d b i t t d ti tSystem controlled by integrated operating system⌧providing interaction between processors ⌧Interaction at job, task, file and data element levels
![Page 17: William Stallings Computer Organization and A hit td](https://reader033.vdocument.in/reader033/viewer/2022060104/629276296323f3763a1e0267/html5/thumbnails/17.jpg)
SMP AdvantagesSMP Advantages
PerformanceIf some work can be done in parallel
AvailabilitySince all processors can perform the same functions, failure of a single processor does not halt the systemfailure of a single processor does not halt the system
Incremental growthUser can enhance performance by adding additionalUser can enhance performance by adding additional processors
Scalinga gVendors can offer range of products based on number of processors
![Page 18: William Stallings Computer Organization and A hit td](https://reader033.vdocument.in/reader033/viewer/2022060104/629276296323f3763a1e0267/html5/thumbnails/18.jpg)
Block Diagram of Tightly Coupled MultiprocessorCoupled Multiprocessor
![Page 19: William Stallings Computer Organization and A hit td](https://reader033.vdocument.in/reader033/viewer/2022060104/629276296323f3763a1e0267/html5/thumbnails/19.jpg)
Organization ClassificationOrganization Classification
Time shared or common busMultiport memoryCentral control unit
![Page 20: William Stallings Computer Organization and A hit td](https://reader033.vdocument.in/reader033/viewer/2022060104/629276296323f3763a1e0267/html5/thumbnails/20.jpg)
Time Shared BusTime Shared Bus
Simplest formSimplest formStructure and interface similar to single processor systemprocessor systemFollowing features provided
Addressing - distinguish modules on busAddressing distinguish modules on bus Arbitration - any module can be temporary masterTime sharing - if one module has the bus, others g ,must wait and may have to suspend
Now have multiple processors as well as multiple I/O modules
![Page 21: William Stallings Computer Organization and A hit td](https://reader033.vdocument.in/reader033/viewer/2022060104/629276296323f3763a1e0267/html5/thumbnails/21.jpg)
Time Share Bus AdvantagesTime Share Bus - Advantages
SimplicityFlexibilityReliability
![Page 22: William Stallings Computer Organization and A hit td](https://reader033.vdocument.in/reader033/viewer/2022060104/629276296323f3763a1e0267/html5/thumbnails/22.jpg)
Time Share Bus DisadvantageTime Share Bus - Disadvantage
Performance limited by bus cycle timeEach processor should have local cache
Reduce number of bus accesses
Leads to problems with cache coherenceSolved in hardware - see later
![Page 23: William Stallings Computer Organization and A hit td](https://reader033.vdocument.in/reader033/viewer/2022060104/629276296323f3763a1e0267/html5/thumbnails/23.jpg)
Multiport MemoryMultiport Memory
Direct independent access of memory modules by each processorLogic required to resolve conflictsLittle or no modification to processors or
d l i dmodules required
![Page 24: William Stallings Computer Organization and A hit td](https://reader033.vdocument.in/reader033/viewer/2022060104/629276296323f3763a1e0267/html5/thumbnails/24.jpg)
Multiport Memory - Advantages and Disadvantagesand Disadvantages
More complexExtra login in memory system
Better performanceEach processor has dedicated path to each module
f fCan configure portions of memory as private to one or more processors
Inc eased sec itIncreased security
Write through cache policy
![Page 25: William Stallings Computer Organization and A hit td](https://reader033.vdocument.in/reader033/viewer/2022060104/629276296323f3763a1e0267/html5/thumbnails/25.jpg)
Central Control UnitCentral Control Unit
Funnels separate data streams between independent modulesCan buffer requestsPerforms arbitration and timingPass status and controlPerform cache update alertingInterfaces to modules remain the samee.g. IBM S/370
![Page 26: William Stallings Computer Organization and A hit td](https://reader033.vdocument.in/reader033/viewer/2022060104/629276296323f3763a1e0267/html5/thumbnails/26.jpg)
Operating System IssuesOperating System Issues
Simultaneous concurrent processesSchedulingSynchronizationMemory managementReliability and fault tolerance
![Page 27: William Stallings Computer Organization and A hit td](https://reader033.vdocument.in/reader033/viewer/2022060104/629276296323f3763a1e0267/html5/thumbnails/27.jpg)
IBM S/390 Mainframe SMPIBM S/390 Mainframe SMP
![Page 28: William Stallings Computer Organization and A hit td](https://reader033.vdocument.in/reader033/viewer/2022060104/629276296323f3763a1e0267/html5/thumbnails/28.jpg)
S/390 Key componentsS/390 - Key components
Processor unit (PU)CISC microprocessorFrequently used instructions hard wired64k L1 unified cache with 1 cycle access time
L2 cacheL2 cache384k
Bus switching network adapter (BSN)Bus switching network adapter (BSN)Includes 2M of L3 cache
Memory cardMemory card8G per card
![Page 29: William Stallings Computer Organization and A hit td](https://reader033.vdocument.in/reader033/viewer/2022060104/629276296323f3763a1e0267/html5/thumbnails/29.jpg)
Cache Coherence and MESI ProtocolMESI Protocol
Problem - multiple copies of same data in different cachesCan result in an inconsistent view of memoryWrite back policy can lead to inconsistencyWrite through can also give problems unless caches monitor memory traffic
![Page 30: William Stallings Computer Organization and A hit td](https://reader033.vdocument.in/reader033/viewer/2022060104/629276296323f3763a1e0267/html5/thumbnails/30.jpg)
Software SolutionsSoftware Solutions
Compiler and operating system deal with problemOverhead transferred to compile timeDesign complexity transferred from hardware to
ftsoftwareHowever, software tends to make conservative d i idecisions
Inefficient cache utilization
Analyze code to determine safe periods forAnalyze code to determine safe periods for caching shared variables
![Page 31: William Stallings Computer Organization and A hit td](https://reader033.vdocument.in/reader033/viewer/2022060104/629276296323f3763a1e0267/html5/thumbnails/31.jpg)
Hardware SolutionHardware Solution
Cache coherence protocolsDynamic recognition of potential problemsRun timeMore efficient use of cacheTransparent to programmerDirectory protocolsy pSnoopy protocols
![Page 32: William Stallings Computer Organization and A hit td](https://reader033.vdocument.in/reader033/viewer/2022060104/629276296323f3763a1e0267/html5/thumbnails/32.jpg)
Directory ProtocolsDirectory Protocols
Collect and maintain information about copies of data in cacheDirectory stored in main memoryRequests are checked against directoryAppropriate transfers are performedCreates central bottleneckEffective in large scale systems with complex interconnection schemes
![Page 33: William Stallings Computer Organization and A hit td](https://reader033.vdocument.in/reader033/viewer/2022060104/629276296323f3763a1e0267/html5/thumbnails/33.jpg)
Snoopy ProtocolsSnoopy Protocols
Distribute cache coherence responsibility among cache controllersCache recognizes that a line is sharedUpdates announced to other cachesSuited to bus based multiprocessorIncreases bus traffic
![Page 34: William Stallings Computer Organization and A hit td](https://reader033.vdocument.in/reader033/viewer/2022060104/629276296323f3763a1e0267/html5/thumbnails/34.jpg)
Write InvalidateWrite Invalidate
Multiple readers, one writerWhen a write is required, all other caches of the line are invalidatedWriting processor then has exclusive (cheap)
til li i d b thaccess until line required by another processorUsed in Pentium II and PowerPC systemsState of every line is marked as modified, exclusive, shared or invalidMESIMESI
![Page 35: William Stallings Computer Organization and A hit td](https://reader033.vdocument.in/reader033/viewer/2022060104/629276296323f3763a1e0267/html5/thumbnails/35.jpg)
Write UpdateWrite Update
Multiple readers and writersUpdated word is distributed to all other processors
Some systems use an adaptive mixture of both solutions
![Page 36: William Stallings Computer Organization and A hit td](https://reader033.vdocument.in/reader033/viewer/2022060104/629276296323f3763a1e0267/html5/thumbnails/36.jpg)
MESI State Transition DiagramMESI State Transition Diagram
![Page 37: William Stallings Computer Organization and A hit td](https://reader033.vdocument.in/reader033/viewer/2022060104/629276296323f3763a1e0267/html5/thumbnails/37.jpg)
ClustersClusters
Alternative to SMPHigh performanceHigh availabilityServer applications
A group of interconnected whole computersg p pWorking together as unified resourceIllusion of being one machineu o o b g o aEach computer called a node
![Page 38: William Stallings Computer Organization and A hit td](https://reader033.vdocument.in/reader033/viewer/2022060104/629276296323f3763a1e0267/html5/thumbnails/38.jpg)
Cluster BenefitsCluster Benefits
Absolute scalabilityIncremental scalabilityHigh availabilitySuperior price/performance
![Page 39: William Stallings Computer Organization and A hit td](https://reader033.vdocument.in/reader033/viewer/2022060104/629276296323f3763a1e0267/html5/thumbnails/39.jpg)
Cluster Configurations -Standby Server No Shared DiskStandby Server, No Shared Disk
![Page 40: William Stallings Computer Organization and A hit td](https://reader033.vdocument.in/reader033/viewer/2022060104/629276296323f3763a1e0267/html5/thumbnails/40.jpg)
Cluster Configurations -Shared DiskShared Disk