william stallings computer organization and architecture chapter 11 cpu structure and function
TRANSCRIPT
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William Stallings Computer Organization and Architecture
Chapter 11CPU Structureand Function
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CPU Structure
CPU must: Fetch instructions Interpret instructions Fetch data Process data Write data
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Registers
CPU must have some working space (temporary storage)
Called registersNumber and function vary between
processor designsOne of the major design decisionsTop level of memory hierarchy
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User Visible Registers
General PurposeDataAddressCondition Codes
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General Purpose Registers (1)
May be true general purposeMay be restrictedMay be used for data or addressingData
Accumulator
Addressing Segment
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General Purpose Registers (2)
Make them general purpose Increase flexibility and programmer options Increase instruction size & complexity
Make them specialized Smaller (faster) instructions Less flexibility
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How Many GP Registers?
Between 8 - 32Fewer = more memory referencesMore does not reduce memory references
and takes up processor real estateSee also RISC
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How big?
Large enough to hold full addressLarge enough to hold full wordOften possible to combine two data
registers C programming double int a; long int a;
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Condition Code Registers
Sets of individual bits e.g. result of last operation was zero
Can be read (implicitly) by programs e.g. Jump if zero
Can not (usually) be set by programs
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Control & Status Registers
Program CounterInstruction Decoding RegisterMemory Address RegisterMemory Buffer Register
Revision: what do these all do?
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Program Status WordA set of bits Includes Condition CodesSign of last resultZeroCarryEqualOverflow Interrupt enable/disableSupervisor
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Supervisor Mode
Intel ring zeroKernel modeAllows privileged instructions to executeUsed by operating systemNot available to user programs
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Other Registers
May have registers pointing to: Process control blocks (see O/S) Interrupt Vectors (see O/S)
N.B. CPU design and operating system design are closely linked
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Example Register Organizations
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Foreground Reading
Stallings Chapter 11Manufacturer web sites & specs
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Instruction Cycle
RevisionStallings Chapter 3
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Indirect Cycle
May require memory access to fetch operands
Indirect addressing requires more memory accesses
Can be thought of as additional instruction subcycle
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Instruction Cycle with Indirect
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Instruction Cycle State Diagram
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Data Flow (Instruction Fetch)
Depends on CPU design In general:
Fetch PC contains address of next instruction Address moved to MAR Address placed on address bus Control unit requests memory read Result placed on data bus, copied to MBR, then to IR Meanwhile PC incremented by 1
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Data Flow (Data Fetch)
IR is examinedIf indirect addressing, indirect cycle is
performed Right most N bits of MBR transferred to MAR Control unit requests memory read Result (address of operand) moved to MBR
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Data Flow (Fetch Diagram)
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Data Flow (Indirect Diagram)
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Data Flow (Execute)
May take many formsDepends on instruction being executedMay include
Memory read/write Input/Output Register transfers ALU operations
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Data Flow (Interrupt)
Simple Predictable Current PC saved to allow resumption after interrupt Contents of PC copied to MBR Special memory location (e.g. stack pointer) loaded
to MAR MBR written to memory PC loaded with address of interrupt handling routine Next instruction (first of interrupt handler) can be
fetched
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Data Flow (Interrupt Diagram)
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Prefetch
Fetch accessing main memoryExecution usually does not access main
memoryCan fetch next instruction during
execution of current instructionCalled instruction prefetch
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Improved Performance
But not doubled: Fetch usually shorter than execution
Prefetch more than one instruction?
Any jump or branch means that prefetched instructions are not the required instructions
Add more stages to improve performance
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Pipelining
Fetch instructionDecode instructionCalculate operands (i.e. EAs)Fetch operandsExecute instructionsWrite result
Overlap these operations
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Timing of Pipeline
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Branch in a Pipeline
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Dealing with Branches
Multiple StreamsPrefetch Branch TargetLoop bufferBranch predictionDelayed branching
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Multiple Streams
Have two pipelinesPrefetch each branch into a separate
pipelineUse appropriate pipeline
Leads to bus & register contentionMultiple branches lead to further pipelines
being needed
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Prefetch Branch Target
Target of branch is prefetched in addition to instructions following branch
Keep target until branch is executedUsed by IBM 360/91
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Loop Buffer
Very fast memoryMaintained by fetch stage of pipelineCheck buffer before fetching from memoryVery good for small loops or jumpsc.f. cacheUsed by CRAY-1
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Branch Prediction (1)
Predict never taken Assume that jump will not happen Always fetch next instruction 68020 & VAX 11/780 VAX will not prefetch after branch if a page
fault would result (O/S v CPU design)
Predict always taken Assume that jump will happen Always fetch target instruction
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Branch Prediction (2)
Predict by Opcode Some instructions are more likely to result in a
jump than thers Can get up to 75% success
Taken/Not taken switch Based on previous history Good for loops
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Branch Prediction (3)
Delayed Branch Do not take jump until you have to Rearrange instructions
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Branch Prediction State Diagram
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Foreground Reading
Processor examplesStallings Chapter 11Web pages etc.