Wireless Network vs. ASICUniversity of Tehran

Department of Electrical and Computer Engineering

ASIC Course – Spring 2006

Instructor: Dr. S. M. Fakhrai

Presented by: Mohammad Ali TootoonchianThis is a class presentation. All data are copy righted to

respective authors as listed in the references and have been used here for

educational purpose only

Outline

• Wireless Network Overview

• Wireless Network vs. ASIC Issues• Low Power ASIC Design for Sensor Network • Wireless Network Implementation vs.

Codesign• ASIC Application in Wireless Network

• Conclusion

• References

Wireless Network Overview[8]

• WLAN : Wireless Local Area Network• Wireless Sensor Network

• WMAN: Wireless Metropolitan Area Network• WPAN: Wireless Personal Area Network• WWAN: Wireless Wide Area Network

Figure1: Wireless Protocol Area Coverage[4]

Wireless Network Overview

Figure2: Wireless Protocol Application [4]

Low Power Design in Wireless Sensor Network

• WiseNET: An Ultralow-Power Wireless Sensor Network Solution [1]• Introduction• Network Architecture

• WiseMAC Protocol• Wireless Network Architecture• Reducing Power Consumption

• Hardware and Software Codesign• WiseNET Node Architecture

Low Power Design in Wireless Sensor Network

• Introduction• Consists of many energy-

autonomous micro-sensors

• Sensor Node Characteristics

• Monitors local environment,

• Locally processing and storing the collected data

• Not require maintenance.• Long Lifetime ranges

Figure3: Sensor Node Architecture[5]

Network Architecture: WiseMAC Protocol

• Reducing power consumption requires optimization across all layers

• This solution consumes about 100 times less power

• Preamble Sampling

Network Architecture: Wireless Network Architecture

• The infrastructure mode • Mobile nodes communicate through base stations• Particularly its relative simplicity.• Base stations do not have power restrictions.

• The ad hoc mode• There is no base station infrastructure.• Successive hops transport a packet.• Higher versatility and potentially lower power

consumption.• Can be deployed quickly and in remote areas.

• Hybrid Mode

Network Architecture: Wireless Network Architecture

Figure4: Infrastructure Wireless[6]

Figure5: Ad hoc Network Wireless[6]

Network Architecture: Reduce Power Consumption

• Reduce Power Main Techniques• nodes remain sleeping until they need to undertake a specific

task.• An external event also can trigger this wake-up

• With Proper design, communication will decrease network power consumption significantly

• Power Consumption Factors• Idle listening• Overemitting• Overhearing• Collisions

Hardware Software Codesign and Power Reduction

• Design the radio and protocol concurrently.• Power consumption in receive and transmit mode• Wake-up time• Bit and frame synchronization time• The presence of an receive signal strength indicator• Some way to filter incoming packets• The time to switch from receive to transmit mode or

vice versa• Receiver sensitivity and maximum transmit power• The capacity to adjust transmit power and receiver

sensitivity • Power consumption in sleep mode with a running,

accurate clock

Hardware Software Codesign

• Basic Issue• Minimize the transmit power

• Because nodes usually transmit rarely, the transmit energy is not the most important parameter to be optimized.

• Reducing energy consumption and wakeup time in receive mode.

• We added robust bit synchronization and packet filtering based on a programmable pattern

• Developed a complete sensor node SoC

Hardware Software Codesign

Figure6: Generic WiseNET SoC building blocks. In addition to the ultralow-power dual-band radio transceiver (TX and RX), the architecture includes a sensor interface with a signal conditioner and two analog-to-digital converters (ANA FE), a digital control unit based on a Cool-RISC microcontroller (μC) with on-chip low-leakage memory, several timebasis and digital interfaces, and a power management block (POW). [1]

WiseNET Node Architecture

• long-term autonomy and low average power consumption.

• Tiny to fit into all kinds of spaces and, given their high number

• Inexpensive

• SoC approach to design • Highly integrated devices • Dedicated integrated circuit.

WiseNET Node Architecture

• Design Objective• Keep the power consumption within the 1-milliwatt

range while in receive mode

• Achieve several years of autonomy by operating from a single 1.5-V AA alkaline battery

• Use a 0.18-micrometer standard digital CMOS process that has no precision analog components

• Minimize both the number of external components and the cost.

Figure7: The WiseNET SoC sensor node. Key SoC components include the dual band transceiver (RX/TX), the sensor interface with two ADCs (ANA), the power management block (POW), the control unit (μC) with an 8-bit CoolRISC processor, and the embedded low leakage memory (RAM). [1]

Wireless Network Implementation vs. Codesign

• HW/SW Codesigned Implementation of IEEE 802.16 TDMA MAC for the Subscriber Station [2]• Introduction• Network Architecture

• SS Operation• SS MAC function component

• Hardware and Software Codesign• Implementation

Wireless Network Implementation vs. Codesign

• Introduction• IEEE 802.16 MAC Subscriber station (SS)

• Send upstream packets in the uplink duration • Scheduling information specified by the Base Station (BS)

• Time-critical job needs to be implemented in HW • No timing constraints can be guaranteed in SW.

• An important factor to guarantee performance of high-speed protocol is integration between software (SW) and hardware (HW).

Network Architecture: SS Operation

• The BS assigns the radio channel to each SS • According to the scheduling policy of the

medium access control (MAC).

• Request/grant mechanism to coordinate transmissions among multiple SSs.

Network Architecture: SS MAC Component

• The Service Specific Convergence Sublayer (CS) • Provides any transformation or mapping of external network data to the MAC

Common Part Sublayer (CPS).

• The Privacy Sublayer • Pertains to authentication, secure key exchange, and encrypting.

• The MAC CPS responsible of• System access, • Bandwidth allocation, • Connection establishment, • Connection maintenance. • Receives data form the various CSs, through the MAC SAP, • Classified to particular MAC connection (associated with Connection Identifier).

• The heavy loaded jobs are as follows.• Framing: Fragmentation/Packing• Automatic repeat request(ARQ): Selective-Repeat is assumed• Encryption : DES algorithm is assumed.• CRC-32• Uplink Scheduling

Hardware and Software Codesign

• The important criteria for partitioning• SS has to be as fast as it is able to satisfy the timing request• Implementation complexity and the memory in the downlink

transmission

• Implementation Methodology:• A functional specification, • System-level partitioning, • Communication synthesis, • Virtual prototyping and implementation.

• The validation was performed using C description • The basic idea of codesign is that the behavior of a complete

system should be described abstractly in a uniform manner,

Implementation

• MAC board will be interfaced with laptop computer using PCMCIA interface (VHDL)

• MAC board contains • StrongARM SA-1110 processor operated by

Montavista Linux, • SW implementation codes are developed as

loadable kernel module,

• Single Xilinx VirtexTM-II FPGA • HW implementation codes are written by VHDL.

Implementation

Packet Classifier

MAC Control MAC QoS Control

TX Buffering RX ARQ RX nonARQ

Interface Buffer

TX Fragmentation

TX ARQ

Control

TX Framing

TX Encryption

TX CRC Generator

RX Decryption

TX CRC Check

TX Buffering

CPUMemory

Serial Port

PHY

MAC HW

FPGA & FLASH & dpRAM

DRAM (32bit)

CPLD

EEPROM

Memory(16bit)

PCMCIA(16bit)

Buffer (32bit)

Figure8: HW/SW functional partitioning and architecture of MAC board [2]

ASIC Application in Wireless Network

• A design and implementation of ASIC for high-quality VoIP terminal over wireless LAN[3]• Introduction• VoIP Architecture• ASIC Design• ASIC Implementation

ASIC Application in Wireless Network

• Introduction• The lower quality of VoIP service compared

with circuit-based network is an open problem to be solved for the wider applications of all IP networks.

• For the enhancement of quality of voice for VolP applications, • Wideband speech codec technology was the

first consideration for better quality of media source itself.

VoIP over Wireless LAN Architecture

• The features of G.729EV provide. • G.729EV is bit-level interoperability with

legacy G.729 core codec, • Frame size of G.729 is very short as 10ms

• It gives the easier interoperability with the mobile phone.

• Its scalability for the capacity of terminals and bandwidth.

VoIP over Wireless LAN Architecture

Figure8: Overall architecture of ASIC [3]

GPIO

UART

Wideband Speech I/F

SSP

AAC

SCI

COMMOM MAC

OFDM

RTCWDTTimer 0/1System

Controller

Reset/ Clock gen.

Internal Memory

External Interface

DMACProcessor

Bus Matrix

VICCLCD

AHB

APB

ARM (inst)

ARM (data)

DMAC

CLCD

ASIC Design

• ASIC Characteristics• High-performance RISC core with DSP features

• not the use of additional DSP core as shown • 16-channel DMA Controller

• for transferring data at high speed,• Interrupter Controller, • AHB I/O decoder, • CLCD Controller, • Reset and Clock Controller, • Elastic Buffer,• APB (Advanced Peripheral Bus),• Timers

• Free Running• Periodic Timer

WMAC Implementation

• WMAC QoS• The excessive packet delay and loss between AP and terminal.

• IEEE8O2.1lie standard provides 1 solution by using the differentiated queue management with priority based on class of service.

• WMAC Design• PLCP interface, • Interrupt control and • Management part

• Processes management data of WMAC and WPHY. • Data transmission part

• Transmit controller, • Transmit FIFO, • Transmit data pump, • Data multiplexer,

• Data reception part includes • Receive controller, • Receive FIFO,• Receive data pump

• WMAC Codesign

ASICTerms Specifications

Core Processor ARM926EJ-S@200MHz

Bus Clock Upto 100MHz

Internal Memories 32k TCM, 64K SRAM

Network interface IEEE 802.11 a/b/g

Audio Sampling Max 48KHz

External Memory Interface 64 MB SRAM/SDRAM/FLASH

Graphic Interface STN/TFT LCD Controller

Process / Package 0.18 um CMOS / 316 pin BGA

Dimension 27 x 27 mm

Conclusion

• Nowadays Wireless Protocol play a main role in communication world industry.

• Based on protocol specification, developed application and specific constraint design attributes change significantly• Power• Time• Area• Bandwidth• Signal Integrity

• Codesign goals and objective should be satisfy protocol specification, application request and user constraints.

• ASIC Design and implementation

References• Papers

[1]:”WiseNET: an ultralow-power wireless sensor network solution”; Enz, C.C.; El-Hoiydi, A.; Decotignie, J.-D.; Peiris, V.;Computer Volume 37,  Issue 8,  Aug. 2004

[2]:”HW/SW codesigned implementation of IEEE 802.16 TDMA MAC for the subscriber station”; Nak Woon Sung;Computer and Information Science, 2005. Fourth Annual ACIS International Conference on 2005

[3]:”A design and implementation of ASIC for high-quality VoIP terminal over wireless LAN”;Do Young Kim; Jong Won Park;Advanced Communication Technology, 2006. ICACT 2006. The 8th International Conference Volume 3,  20-22 Feb. 2006

• WebSites:[4]:http://www.eurecom.fr/~nikaeinn/adhocNetworks/

Wireless_Technologies.pdf[5]:http://www.isoc.org/pubs/int/cisco-1-1.html[6]:http://www.crc.ca/en/html/crc/home/mediadesk/eye_on_tech/2005/

issue2/devices_that_sense[7]:http://www.merl.com/ projects/sensornet/[8]:ttp://www.tutorial-reports.com/