wolfgang kühn, univ. giessen delevopment tools beyond hdl
TRANSCRIPT
Wolfgang Kühn, Univ. Giessen
Overview
Introduction FPGA Design Challenges VHDL Tools with higher abstraction level Handel-C
Features Differences to VHDL
Advantages Drawbacks
Possible applications
Wolfgang Kühn, Univ. Giessen
Common Prejudice …..
FPGAs are good for applications which involve simple algorithms which can be executed in parallel require high speed (few ns level) response to real time
events do not need frequent redesigns (expert knowledge
required !)
DSPs are good for applications which involve complex algorithms with many arithmetic operations are less demanding in real time requirements require programming in C / C++ because sometimes even a
physicst needs to change part of the code
Wolfgang Kühn, Univ. Giessen
Function Industry’s Fastest DSP Processor Core
Xilinx Virtex-II
Virtex-II Pro
8 x 8 Multiply Accumulate (MAC)
4.8 billion MAC/s 0.5 Tera MAC/s
1 Tera MAC/s
FIR Filter- 256 taps, linear phase- 16-bit data/coefficients
9.3 MSPS600 MHz
180 MSPS180 MHz
300 MSPS300 MHz
Complex FFT- 1024 point, 16-bit data
10.2 s600 MHz
1 s*140 MHz
1 s**150 MHz
* Using 96 embedded multipliers in the largest Virtex-II device (XC2V8000) ** Using 96 embedded multipliers and 176 Block Ram in V-II PRO (XC2V125)
FPGA / DSP Performance (3/2003)
Example: XILINX Virtex-II and Virtex-II Pro
Wolfgang Kühn, Univ. Giessen
Translate
Map
Place & Route
Typical FPGA Design Flow
Plan & Budget HDL RTLSimulation
Synthesizeto create netlist
FunctionalSimulation
Create Bit File
Attain Timing Closure
TimingSimulation
Implement
Create Code/Schematic
Wolfgang Kühn, Univ. Giessen
XILINX Tools for Digital Signal Processing
Generate:- VHDL/Verilog- IP cores
® XST®
Leonardo
Spectrum®
Synplify®
Synthesis
Simulink®
DSP Modeling
MATLAB®
Automatic Translation
ISE® 4.1i
Implementation& Verification
Wolfgang Kühn, Univ. Giessen
MATLAB
MATLAB™, the most popular system design tool, is a programming language, interpreter, and modeling environment Extensive libraries for math functions, signal
processing, DSP, communications, and much more Visualization: large array of functions to plot and
visualize your data and system/design Open architecture: software model based on base
system and domain-specific plug-ins
Wolfgang Kühn, Univ. Giessen
Simulink
Simulink™ - Visual data flow environment for modeling and simulation of dynamical systems Fully integrated with the MATLAB engine Graphical block editor Event-driven simulator Models parallelism Extensive library of parameterizable functions
Simulink Blockset - math, sinks, sources DSP Blockset - filters, transforms, etc. Communications Blockset - modulation, etc.
Wolfgang Kühn, Univ. Giessen
Traditional Simulink FPGA Flow
GAP
System Architect
FPGA Designer
Verify Equivalence
HDL
Synthesis
Implementation
Download
Timing Simulation
In-Circuit Verification
Functional Simulation
System Verification
Simulink
Wolfgang Kühn, Univ. Giessen
XILINX System Generator
HDLSystem Generator
MATLAB/Simulink
System Verification
•VHDL
•IP
•Testbench
•Constraints FileSynthesis
Implementation
Download
Timing Simulation
In-Circuit Verification
Functional Simulation
Wolfgang Kühn, Univ. Giessen
Handel-C ( http://www.celoxica.com )
Handel-C is a language for programming applications Handel-C is not an HDL. It is not C used as an HDL Handel-C is meaningful to both s/w and h/w
engineers Focus of describing solutions to problems as
algorithms VHDL/Verilog focus on describing the structure of
a system capable of performing an algorithm. Hardware design means controlling space (parallelism)
and time (sequential processing) The par command gives control over space The Single clock assignment rule gives control
over time
Wolfgang Kühn, Univ. Giessen
Handel-C Core Language Features
Standard ISO-C (ANSI-C) Control commands: if, while, switch etc. Functions, structures, pointers
Extensions for hardware implementation par{…} construct - specifies spatial-parallel architecture Single cycle assignment – specifies temporal architecture Arbitrary widths on variables, expressions etc. Type-checked bit-width inference system Recursive macro expansion system Multiple clock domains with automatic metastability
resolution Powerful bit manipulation operators Signals, channels, interfaces to pins, external IP cores RAMs/ROMs and external pin connections
Wolfgang Kühn, Univ. Giessen
Timing is predictable Designer has control over timing Simple model: assignments take one clock cycle Cycle-accurate, fast simulator
Parallelism is deterministic Language extensions include parallel processing and
communications between parallel elements Parallelism based on sound mathematical formalism
Changes are predictable Changes in Handel-C code produce predictable changes in
hardware Enables fast iterative refinement
Wolfgang Kühn, Univ. Giessen
Hardware/Software Co-Design
Enables development of complete systems, ideal for: Board-level prototyping Reconfigurable SoC designs Hybrid CPU & FPGA devices
Design kit (DK1) facilitates co-design with: Instruction set simulators VHDL simulators External C test benches
Enables hardware/software partitioning decisions later in the design cycle
Rapid conversion of software algorithms into custom hardware
Wolfgang Kühn, Univ. Giessen
DK1 Design Suite Features
Compiler Output is: Optimised Deterministic Target specific
Targets Xilinx and Altera net lists directly (EDIF)
RTL VHDL output
Generation of IP cores (Handel-C, EDIF, VHDL)
Inclusion of IP cores as ‘black boxes’
GUI for integrated project management, code editing and source level debugging
Fast simulation/debug
Handel-C Simulate
Compile
Configure
1
A
D
Q 1
Q 4
E N B
R eg is te r
Netlist
Place And
Route
FPGA Vendor’s Tools
Wolfgang Kühn, Univ. Giessen
Conclusions
Exploiting the power of modern FPGAs gets increasingly difficult using only „traditional“ HDL design methods
1 Million Gate XILINX Spartan III costs only 12 $ !!! New areas of application beyond traditional FPGA domains
require higher levels of abstraction Tools such as Handel-C look promising Experience with real designs needed