working 225 v over-voltage protection cell with tunable trigger and holding voltages for latch-up...

2834 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 60, NO. 9, SEPTEMBER 2013

Working 225 V Over-Voltage Protection Cell WithTunable Trigger and Holding Voltages

for Latch-Up ImmunityEdward John Coyne

Abstract— This paper describes the challenges encounteredand solutions found to be the problem of developing over-voltage protection for 225 V circuit applications with measuredtunable trigger voltages of 100–300 V, measured tunable holdingvoltages for latch-up immunity of 50–240 V, and correspondingstrengths of 8.0–2.4 A Transmission Line Pulse (TLP). The deviceis engineered using technical computer-aided design and theperformance is measured with dc characterization, unpoweredTLP, powered and unpowered Electrostatic Discharge (ESD),as well as a 225 V product placement with a 1500-h HighTemperature Operating Life lifetime reliability monitor. The finalcell enables both 225 V powered and unpowered protection fromhigh voltage switching transients and ESD events.

Index Terms— Over-voltage protection, reduced surface field(RESURF), silicon controlled rectifier (SCR), technical computer-aided design (TCAD), ultrahigh voltage circuit.

I. INTRODUCTION

EMERGING products operating at the 225 V power supplynode have revealed a new level of destructive over-

voltage events that need to be solved to achieve true robust-ness. For the initial high-voltage products, circuit functionalityis demonstrated when operating under controlled conditions.Bench test evaluations, however, soon identified destructiveover-voltage fast transient pulses, with 10-ps rise times thatwere being generated externally to the product.

Associated with every circuit application are parasitic capac-itances and inductances originating from the package bondwires, to the external power supply. For lower voltage prod-ucts, the power and oscillations arising from these parasiticelements are difficult to measure, let alone cause damage. At225 V, this power is, however, destructive and can be triggeredby standard applications such as power supply switching, orvoltage probing.

A product-based solution for this problem and other poten-tial Electrostatic Discharge (ESD) events is a two-step methodof developing an over-voltage protection cell, and modifyingthe circuit design where possible to dampen the over-voltagepulses. Beneficial modifications to the circuit design includeincreasing the safe operating area between the 225 V powersupply and the Double diffused Metal Oxide Semiconductor

Manuscript received May 15, 2013; revised June 21, 2013; accepted June 25,2013. Date of publication July 11, 2013; date of current version August 19,2013. The review of this paper was arranged by Editor G. Dolny.

The author is with the Analog Devices, Process Development, Limerick16949, Ireland (e-mail: [email protected]).

Color versions of one or more of the figures in this paper are availableonline at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TED.2013.2271812

Fig. 1. Transmission Line Pulse (TLP) measurement of the 300 V p-DMOSand n-DMOS off-state breakdown voltage that allows for a greater operatingwindow >225 V power supply. Irreversibly damage occurs at the breakdownvoltage that ultimately defines the ESD strength of the device.

breakdown voltage, which is increased from 270 to 300 Vto allow for greater tolerance (Fig. 1). Extra capacitancescan be connected to the power supply node to absorb anddampen high-voltage oscillations before they move outsidethe safe operating area. Depending on the flexibility of thedesign, resistances can be connected in series with the DMOS,such that the displacement current potential drop across theseresistances reduces the voltage loading at the DMOS itself.

Complimentary to those design changes, the over-voltageprotection snapback cell had to be designed to prevent allthe external voltages from exceeding the breakdown voltageof the internal circuitry and hold at a voltage greater thanthe dc power supply of the pin it is protecting. To addressthe challenges presented by the range of high-voltage nodes(125–225 V) accommodated within this process, it is necessaryto develop a single device with an adjustable trigger andholding voltage to meet the unique requirements of the hostcircuit [1]–[3].

II. TECHNICAL COMPUTER-AIDED DESIGN

A. n-p-n

The starting point for the design of the protection cell is ann-p-n bipolar, which has an established record for snapbackESD protection over low to medium voltage ranges [3]. Theinternal breakdown voltage of the n-p-n during normal oper-ation can be divided into the vertical and lateral components

0018-9383 © 2013 IEEE

COYNE: WORKING 225 V OVER-VOLTAGE PROTECTION CELL 2835

Fig. 2. Diagram showing one-half of a symmetric n-p-n/SCR with a floatingbase. Grounded polysilicon and metal 1 field plates create a RESURF actionthat allows the depletion region to spread laterally to achieve the high-voltageoperation. The dual EPI n-well implant prevents vertical punch-through of thep-n-p.

of the reverse-biased collector—base junction. In order forthe lateral breakdown voltage to withstand voltages in excessof the high operating conditions of the host circuit, it isnecessary to use reduced surface field (RESURF) action fieldplating. This implies that the active reverse-biased collector—base junction must be extended parallel to the surface oxide,where a field plate can be formed with polysilicon and metal 1interconnects. To avoid a lateral punch-through mechanismacross the lateral n-p-n, the base is defined by a central p-wellimplant used to support the low-doped EPI in separating theemitter from the collector (Fig. 2).

B. Silicon Controlled Rectifier

For low-voltage pins, the n-p-n can be converted to a siliconcontrolled rectifier (SCR) through the use of a p+ contactdiffusion at either the emitter or collector of the n-p-n bipolar.This p+ forms the emitter of the p-n-p, where the base region isdefined by the n-well and the collector by the p-type EPI. Thisdevice design ensures that the base of the p-n-p is the collectorof the n-p-n and the base of the n-p-n is the collector of thep-n-p (Fig. 2). To avoid a vertical punch-through across thisp-n-p, the net dose of the n-well implant must be increased.Increasing this dose, however, would restrict the RESURFaction that defines the lateral breakdown voltage. Therefore,to increase the depth while limiting the peak concentration,a split EPI is used with a double n-well implant, where thecombined vertical depth is in excess of 6 μm.

III. DEVICE OPERATION—TCAD

A. Snapback Curve—Trigger Voltage

The snapback operation of the device is simulated bysweeping the n-p-n collector voltage to the trigger point andthen switching over to a forced current mode to move up thesnapback curve (Fig. 3).

Fig. 3. Electrothermal simulation of the n-p-n snapback curve. The n-p-nbipolar has an internal trigger voltage of 300 V. At 170 V, with a 2-mAconduction current, the secondary breakdown drops the holding voltage to5–10 V.

P – EPI Drift Length, L

PWELL NWELL

SOI

Fig. 4. TCAD image showing the lateral n-p-n electron current densityconduction path under the base n-well and along the SOI boundary.

The highest electric field that initiates impact ionization atthe breakdown voltage is at the corner of the Poly and M1 fieldplating. The generated hole carriers are swept to the base andelectrons to the collector. The hole current raises the potentialin the floating base until the emitter—base junction is forwardbiased at 0.7 V and the n-p-n turns on (Fig. 4).

Physical observations of the trigger voltage that cannotbe accounted for with 2-D technical computer-aided design(TCAD) simulations are that all high-voltage DMOS devicesare irreversibly damaged at the trigger point of 300 V, whicheffective defines their ESD rating. A number of physicalprocesses account for this, including the fact that the inherentlylarge layout of the DMOS device has parasitic capacitancesassociated with it. These capacitances in conjunction withthe high trigger voltage result in a large amount of storedenergy. At the breakdown voltage, the sudden appearanceof a conduction path results in the rapid discharge of that


N P N

1e19

1e15

1e07

Fig. 5. TCAD generated lateral cutline of the protection cell oxide interfaceshowing the electron density as a function of position for different stages alongthe snapback curve. At low current densities, the n-p-n structure is identifibale.Above a current density of 2.1 e+6 A cm−2 the free carrier concentration,however, exceeds the dopant concentration and the n-p-n structure disappears.

capacitance through a single point that leads to a surge inpower that destroys the device. In addition to this, at thebreakdown voltage, there is a high voltage across the devicewith a low current; this condition leads to current crowdingat the center once the parasitic n-p-n bipolar is turned on.This current crowding enhances the thermal heating in thatlocation that leads to further current crowding and hence arunaway mechanism [4], [5].

B. Snapback Curve—Holding Voltage

In these simulations, once the trigger point has been passed,the n-p-n bipolar is turned on and the holding voltage snapsback to a value required to sustain impact ionization thatgenerates a base current as defined by the Kirk effect. Conven-tionally for power supply applications, the gain of the n-p-nis engineered to ensure the holding voltage exceeds the powersupply of the pin it is protecting. For high-voltage applications,a new problem, however, emerges when protecting high-voltage pins. In order for this process to achieve a high-voltagerating, the implants have a low dose and are thermally drivento allow the depletion region to spread and hence dilute theelectric fields. The low doping concentration means that forconduction current densities in excess of 2.1e+6 A cm−2, theinjected free carrier concentration starts to exceed the dopingconcentration that defines the device (Fig. 5). Therefore, thejunctions that create the MOS or bipolar structure would nolonger exist and hence conventional methods for turning offthe device would be limited. At this point, the device behaveslike a resistor and all external control using base currents orgate biases are gone [6], [7].

C. Snapback Curve—Design Challenges

From this device analysis in conjunction with measurementsof existing high-voltage DMOS structures; two primary prob-lems are identified.

Fig. 6. Measured TLP results showing the low-voltage diode adjustabletrigger voltage in steps of 7.5 V. Once the protection cell is triggered, the SCRis turned on and snaps back to a holding voltage of 45–55 V and conductsup to 5.5 A.

1) How to turn on the devices without irreversible damage.2) How to turn off the device by controlling the holding

voltage for power supply applications when all MOS andbipolar junctions disappear at high currents.

These problems have to be solved while engineering thedevice so there is a layout control of the trigger, and holdingvoltages, as well as the ultimate ESD strength of the device.

IV. PROBLEM 1: LAYOUT ADJUSTABLE

TRIGGER VOLTAGE

To ensure the survival of the protection cell at the triggervoltage, it is necessary to reduce the energy dissipation in bothtime and area by ensuring the trigger event is resistive and notfocused to one point.

A. Low-Voltage Diodes

Low-voltage diodes can impact ionize and conduct currentwithout irreversible damage in breakdown mode, where thisbreakdown voltage can be incrementally increased by placingthe diodes in series [8]. This current can then be injected intothe base of the n-p-n to turn on the over-voltage protectioncell before internal impact ionization. The low-voltage diodesare engineered using an n+ and p+ contact diffusions in ann-well and have an individual breakdown voltage of 7.5 V.Thirty-four of these diodes in series achieve a combinedbreakdown voltage of 255 V that is designed to be lessthan the internal breakdown of the internal circuitry. TLPmeasurements confirm the over-voltage protection can triggerwithout damage and can conduct currents of 5.5 A with aholding voltage of 45–55 V (Fig. 6). A practical limitationof this solution is that a measureable diode leakage currentexists <225 V power supply that would restrict potentialapplications.

B. Punch-Through

Engineering a punch-through breakdown mechanism inter-nally to the device can also be used to reduce the turn-ontime and ensure the current is uniformly distributed acrossthe junction boundary. The RESURF-assisted lateral depletion


Fig. 7. Measured TLP results showing the layout adjustable trigger voltageachieved using the p-n-p punch-through mechanism. The trigger voltage variesfrom 100 to 300 V, and can take currents up to 7.8 A for layout separationof 25–11 μm between the p+ emitter and n-well boundary.

spreading through the reverse-biased collector—base regionof the protection cell can be engineered to reach the p+diffusion and cause an electrical short. This mechanism can bea layout adjusted by extending the position of the p+ implantto the position of the depletion region for a given triggervoltage. Experimental measurements successfully demonstratean adjustable trigger voltage over the range 100–300 V forlayout separation between the p+ emitter and n-well boundaryof 25–11 μm. The trigger mechanism is nondestructive and thedevice conducts 8 A at a holding voltage of 25–55 V (Fig. 7).This solution does not suffer from leakage currents and canallow layout control of ∼13 V μm−1 that is well withinmanufacturing tolerances.

V. PROBLEM 2: LAYOUT ADJUSTABLE HOLDING VOLTAGE

A. Emitter—Base Impedances

For applications where a low holding voltage is required,the over-voltage protection provides a robust device that cantake 6 A with a holding voltage of 45–55 V. For powersupply protection, this low holding voltage, however, willcause a latchup mechanism to drain the power supply andcause the associated dc thermal damage [9]–[11]. To solve thisproblem, a method of turning off the device or increasing theholding voltage beyond the power supply of 225 V must beengineered. Previous TCAD simulations established the factthat the current densities in excess of 2.1e+6 A cm−2 aresufficient to inject enough free carriers to exceed the dopingconcentration and hence the junctions that define the devicedisappears. Therefore, a method had to be determined forcontrolling the protection cell currents external to the device.

A bipolar operating in BVcbo mode is equivalent to a diodeby grounding the base terminal, and floating the emitter. Whenthe diode eventually breaks down, impact ionization injectsmajority carriers into the base and collector regions to createthe current that we see externally to the device. This diodewill not snapback to a lower holding voltage and will insteadincrease according to the ON-state resistance of the device.

eZbZ

N

IbN

P

Ib1

Ie

Ib2

Fig. 8. Circuit diagram showing that by adjusting the ratio of the externallydefined emitter and base impedances the opeation of the device can changebetween a BVcbo diode operation with a high holding voltage, and BVceobipolar operation with a low holding voltage.

If the base terminal is now floating and the emitter is directlyshorted to ground, the bipolar will operate in BVceo mode.This device will snapback to a lower holding voltage as definedby the gain of the bipolar. From these extremes, it is possible tochange the holding voltage of the same device by controllingthe externally defined impedances at the emitter and baseterminals (Fig. 8).

B. Emitter—Base Ohmic Impedances

The elements used to define the impedance for both the baseand emitter terminals can be transient dependent or ohmicin nature. To ensure consistent electrical characteristics, itis advantageous to ensure that the external impedances areohmic in nature and create a holding voltage greater thanthe power supply. For ohmic impedance, standard discreteresistances such as thin film or polysilicon would limit theultimate ESD strength as they are connected in series. The beststructure for supporting high transient currents and dissipatingthe subsequent power is a metal line. To achieve the requiredresistance, it is, however, necessary to increase the length andto save on area; this can be drawn in the form of a spiral(Fig. 8). This is the same design as an inductor and wouldcreate transient-dependent impedance. To solve this problem,the metal spiral resistor is reproduced onto a second metallayer and connected such that the current spirals to the centeron one level and back out on the second level. Therefore, atany given point, there are equal and opposite currents alongthe spiral to produce opposing magnetic fields that reduce thenet inductance of the coil. This provides a noninductive ohmicresistor that is capable of surviving ESD events that can beconnected to the base or emitter terminals (Fig. 9).

TLP electrical measurements for a fixed base resistance of37 � and a varying emitter resistance of 3.2–125 � confirman adjustable holding voltage ranging from 90 to 240 V. The240 V holding voltage is compatible with 225 V power supply


Fig. 9. Layout of the emitter—base resistors. Each resistor consists of twometal levels with a countercurrent flow on each level to cancel the inductivemagnetic fields.

Fig. 10. Measured TLP snapback curves with corresponding external emitterresistances (�) with a fixed base resistance of 37 � for holding voltagesranging from 90 to 240 V.

circuit applications and is capable of conducting 2 A beforedamage (Fig. 10). Effective dc electrical measurements of thesame device using a curve tracer with an oscillation frequencyof 50 Hz also confirms that the device dc triggers at 260 Vand snaps back to a minimum dc holding voltage of 245 V(Fig. 11).

Physical analysis of the high holding voltage protection cellpostfailure observe that the point of failure is in the activesilicon and therefore confirms that the largest potential dropis supported internally to the silicon with no damage to theexternal ohmic metal coils.

C. Emitter—Base Transient Impedances

Replacing the ohmic resistors with transient dependentimpedance such as capacitors or inductors provides an alter-native method to further differentiate between transient overvoltage events and the steady dc power supply. If an inductoris connected to the base terminal and an ohmic resistor to theemitter, then a fast transient current will see higher impedanceat the base relative to lower impedance at the emitter. Thisimpedance ratio will favor the activation of the bipolar to

Fig. 11. Optical image of the 50-Hz curve tracer snapback curve for the highholding voltage protection cell. It confirms an effective dc trigger voltage of260 V and a dc holding voltage of 245 V.

create a low holding voltage that can take a high currentand therefore provide a robust ESD strength. A dc supply,however, will only see the ohmic impedance of the inductorcoil that is designed to be a lower relative to the emitterterminal. This impedance ratio will bias the device towarddiode action and produce a high holding voltage. Similarly, alarge capacitor connected to the emitter terminal will providea low impedance path for fast transients relative to a resistiveelement connected to the base. This will bias the device as abipolar to produce a low holding voltage and high ESD rating.The dc supply, however, will see infinite emitter impedancerelative to the base and favor diode action to produce a highholding voltage that prevents the device from remaining on.Replying on the transient impedance to define the holdingvoltage has the weakness that the operation of the devicewould vary for different ESD events with varying capability.

An alternative method for using the impedance ratio atthe emitter—base terminals to distinguish between transientand continuous voltage supplies is to use a timer circuit.This timer circuit consists of a series of n-MOS transistorsconnected to the base terminal of the over-voltage protectionand an ohmic impedance to the emitter terminal. Duringnormal operation, the n-MOS are off and therefore the baseterminal is effective open with high impedance. In the eventof an over-voltage surge, the over-voltage protection SCRcell will turn on and conduct a current through the emitterimpedance. The low impedance of the emitter relative to thebase will ensure that the device operates with a low holdingvoltage. The low holding voltage allows the device to take8 A before irreversible damage. After the ESD event, thedevice will remain on and provide a resistive path for thepower supply to ground. The potential drop across the emitterimpedance, however, can be used to power an RC timer circuitconnect to the gates of the n-MOS and after a defined period,the threshold voltage is reached and the n-MOS turns on toprovide a low-impedance path relative to the emitter terminal.This impedance ratio will bias the device as a diode and resultin a high holding voltage that will prevent the power supplyfrom keeping the device on and therefore turn it off until thenext ESD event.


Fig. 12. TLP measurement across the power supply rails of a 225 V productwith the over-voltage protection cell connected. The protection cell triggersat 265 V, snaps back to 245 V and conducts up to 2.4 A before damage. Thecurrent before the protection cell trigger is a result of the internal parallelcircuitry.

VI. CONCLUSION

From simulation to product placement, this paper describesa working over-voltage protection for the 125 to 225 Vpower supply node. Development work has identified two keyproblems of triggering the device without irreversible damage,and controlling the holding voltage when the free carrier con-centrations exceed the dopant defined junctions. To solve theseproblems; two working tuneable trigger mechanisms withmeasured physical results are described, and three workingmethods of controlling the holding voltage by defining externalimpedances that differentiate between a transient over-voltageevents and the steady dc power supply are described. Thecomplete protection cell is fully characterized as a standalonedevice and with product placement to produce the followingresults.

1) 12-pA leakage current at 225 V.2) 1.2-pF two terminal capacitance at 225 V.3) Layout adjustable trigger voltage ranging from 100 to

300 V.4) Layout adjustable holding voltage ranging from 50 to

240 V.5) Minimum ESD strength of 6 A, or 8-KV Human Body

Model (HBM) for low holding voltages.6) Minimum ESD strength of 2.4 A, or 3-KV HBM for

high holding voltage.

Evaluation of the protection cell within a 32-channel, 14-bitDigital to Analog Converter having full scale outputs up to225 V in a single packaged, confirms that the product passes.

1) 225 V output shorted to ground.2) 0 V output shorted to 225 V power supply.3) Robustness tests over a temperature range −40 °C– °C.

4) HBM ESD testing of 2 KV unpowered.5) HBM ESD testing of 1-KV powered (rating is due to

the additional transient loading from the power supply).6) Passes FICDM to 1 KV.7) High Temperature Operating Life reliability monitors of

the product and over-voltage protection cell for 1500 hwith zero failures.

8) TLP evaluation of the product across the power supplyrails without the protection cell recorded a damagevoltage of 290 V. With the protection cell, the devicetriggered at 265 V, snaps back to a holding voltage of245 V, and conducts up to 2.4 A (Fig. 12).

REFERENCES

[1] J. Liu, L. Lin, X. Wang, H. Zhao, H. Tang, Q. Fang, A. Wang, L. Yang,H. Xie, S. Fan, B. Zhao, G. Zhang, and X. Wang, “Tunable low-voltage dual-directional ESD protection for RFICs,” in Proc. IEEE RWS,Jan. 2011, pp. 279–282.

[2] J. A. Salcedo, J. J. Liou, and J. C. Bernier, “On the design of tunablehigh-holding-voltage LVTSCR-based cells for on-chip ESD protection,”in Proc. 7th Int. Conf. Solid-State Integr. Circuits Technol., vol. 2.Oct. 2004, pp. 798–803.

[3] J. Schneider, M. Wendel, and K. Esmark, “Tunable bipolar transistor forESD protection of HV CMOS applications,” in Proc. EOS/ESD Symp.,Sep. 2006, pp. 214–221.

[4] S. P. Gaur, D. H. Navon, and R. W. Teerlinck, “Transistor designand thermal stability,” IEEE Trans. Electron Devices, vol. 20, no. 6,pp. 527–534, Jun. 1973.

[5] R. P. Arnold and D. S. Zoroglu, “A quantitative study of emitterballasting,” IEEE Trans. Electron Devices, vol. 21, no. 7, pp. 385–391,Jul. 1974.

[6] C. G. Thornton and C. D. Simmons, “A new high current modeof transistor operation,” IRE Trans. Electron Devices, vol. 5, no. 1,pp. 6–10, Jan. 1958.

[7] H. A. Schaft, “Second-breakdown—A comprehensive review,” Proc.IEEE, vol. 55, no. 8, pp. 1272–1288, Aug. 1967.

[8] S.-L. Jang, M.-S. Gau, and J.-K. Lin, “Novel diode-chain triggeringSCR circuits for ESD protection,” Solid-State Electron., vol. 44, no. 7,pp. 1297–1303, 2000.

[9] G. Meneghesso, A. Tazzoli, F. A. Marino, M. Cordoni, and P. Colombo,“Development of a new high holding voltage SCR-based ESD protectionstructure,” in Proc. IEEE IRPS, Apr./May 2008, pp. 3–8.

[10] C.-T. Wang, T.-H. Tang, and K.-C. Su, “Latch-up free ESD protectiondesign with SCR structure in advanced CMOS technology,” in Proc.IEEE IRPS, Apr. 2011, pp. 4C.3.1–4C.3.4.

[11] J. Lutze, S. Venkatesan, and S. Poon, “Dramatic increases in latchupholding voltage for sub-0.5 μm CMOS using shallow S/D junctions,”IEEE Electron Device Lett., vol. 15, no. 11, pp. 443–445, Nov. 1994.

Edward John Coyne received the Doctorate degreeon femtosecond laser processing of semiconductormaterials.

His current research interests include silicon-germanium and high voltage processes, as well asintegrated diffractive optics.

working 225 v over-voltage protection cell with tunable trigger and holding voltages for latch-up...

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