VHDL 360©

by: Mohamed Samy Samer El-Saadany

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VHDL 360 © 2

Objective

• Modeling more complicated logic using sequential statements

• Skills gained:– Identify sequential environment in VHDL– Model simple sequential logic

VHDL 360 © 3

Outline

• Process Description • Data Objects• Sequential Statements

– Case Statement– IF Statement

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Statements

• VHDL has concurrent statements and sequential statements

• Concurrent statements are executed in parallel with respect to each other, we explained some of them in Module 1*

• Sequential statements are executed in sequence with respect to each other.

• Sequential statements should be written inside a “process”

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Module 1: Create your first model for a simple logic circuit

Process Description

Process ( <sensitivity_list> ) -- process declarations begin -- process bodyend process;

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Architecture behave of example1 is Begin process (x,y) -- Every time "x" or "y" value is changed, the process will be executed begin

myOutput <= x nand y; end process; End behave ;

Example 1:

Syntax:• Process declarations: defines variables, subprograms…etc to be used in process body

• Process body: defines implementation details of input/output relationship in a sequential manner

• <sensitivity_list>: List of signals/ports that cause the process to be executed whenever there is a change in their values

Sequential Assignments• Statements inside a “process” are read sequentially and executed

when the “process” suspends– Signal assignment statement like “F <= A” causes a transaction to be

scheduled– This means; the current value of A is read and scheduled to drive F when the

process suspends.

• “Process” suspends in two situations– When “end process” is reached– When a “wait” statement is reached

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process (. . .) -- Assume that initially A = '1' while G, F, Z and X = 'U' Begin Z <= A; -- Signal assignment, schedule a change/transaction, -- however the value of Z still equals 'U' G <= '1'; F <= G; -- G is not yet updated, so F is assigned the old value of G X <= F; -- Similarly, X is assigned the old value of F

G <= '0'; -- overrides the previous scheduled transaction, -- however the value of G still equals 'U' Z <= G; end process ; -- Process suspends => Signals update with scheduled transactions -- G = '0', F = 'U', Z = 'U', X = 'U'

Example 2:

Sequential Assignments

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Example 3:

Architecture behave of fulladder is signal temp : std_logic;

Begin process (In1, In2, CarryIn) begin

temp <= In1 XOR In2; Sum <= temp XOR CarryIn;

CarryOut <= (In1 AND In2) OR (CarryIn AND temp);end process; End behave ;

There’s a problem here!

Data Objects

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• VHDL offers different data objects:– Constants

• Used to store values that can’t be changed during simulation time

– Signals• Used to model connections• Signals can be

– External (Ports) used as an interface for the entity to the outside world (Declared in Entity)

– Internal used inside the architecture to connect different logic parts (Usually declared in architecture)

• Assigned using “<=”– Outside a process, its value is updated when their signal

assignment is executed.– Inside a process, its value is updated after the process suspends

– Variables• Used for computations• Variables are declared inside a process or sub-programs• Assigned using “:=”

– Value is updated immediately

signal <sig_name> : <sig_type>;

Signal Declaration

constant <con_name>: <con_type>;

Constant Declaration

variable <var_name> : <var_type>;

Variable Declaration

Objects Scope

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• Each object in VHDL has a scope following the below rules:– Objects declared in package are available to all units using that package– Objects declared in an entity are available to all architectures of that entity– Objects declared in an architecture are available to all statements in that architecture– Objects declared in a process are available only within that process

Entity architecture1

architecture3

architecture2

process1

process2

Data Objects Example

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architecture behav of mydut is -- Signals scope is the whole architecture signal x, y : std_logic := 'U'; -- Initialization (Not an assignment) signal sigbus : std_logic_vector(7 downto 0) := "01011110"; begin process() -- No sensitivity list, Is this a problem?

-- Variables are declared inside a process -- Variables scope is limited to the process

variable z : std_logic := '1'; variable varbus : std_logic_vector(3 downto 0) := "0001"; begin x <= '1'; -- Signal assignment, schedule a change,

-- however the value of x still equals 'U'

sigbus <= "00110101"; z := '1'; -- Variable assignment takes effect immediately

varbus := "1101"; sigbus (3 downto 0) <= varbus and "1010"; -- overrides the previous scheduled change, -- however sigbus still equals "01011110" x <= z and '0'; z := '0'; y <= z xor '0'; end process ; -- Process suspends => x = '0', y = '0' and sigbus = "00111000" end architecture;

Skills Check

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process (a,b) variable var1: integer;begin var1 := a + b; temp <= var1; q <= temp; end process;

• Complete the below table with the values of var1, temp & q when the below code is executed where each column represents a new value of a & b

a,b1,2

a,b2,3

a,b5,2

calculate update(after suspend)

calculate update(after suspend)

var1 3

temp 4

q 6

Golden rules of thumb– Variables are updated immediately– Signals are updated after the process suspends

Skills Check (Soln.)

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• Complete the below table with the values of var1, temp & q when the below code is executed where each column represents a new value of a & b

a,b1,2

a,b2,3

a,b5,2

calculate update(after suspend)

calculate update(after suspend)

var1 3 5 5

temp 4 4 5

q 6 6 4

Golden rules of thumb– Variables are updated immediately– Signals are updated after the process suspends

process (a,b) variable var1: integer;begin var1 := a + b; temp <= var1; q <= temp; end process;

Skills Check (Soln.)

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• Complete the below table with the values of var1, temp & q when the below code is executed where each column represents a new value of a & b

a,b1,2

a,b2,3

a,b5,2

calculate update(after suspend)

calculate update(after suspend)

var1 3 5 5 7 7

temp 4 4 5 5 7

q 6 6 4 4 5

Golden rules of thumb– Variables are updated immediately– Signals are updated after the process suspends

process (a,b) variable var1: integer;begin var1 := a + b; temp <= var1; q <= temp; end process;

Skills Check

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Example using variables Example using signals

architecture VAR of EXAMPLE is signal trigger: integer := 0; signal result: integer := 0; begin process(trigger) variable variable1: integer :=1; variable variable2: integer :=2; variable variable3: integer :=3; begin variable1 := variable2; variable2 := variable1 + variable3; variable3 := variable2; result <= variable1 + variable2 + variable3; end process;end VAR;

architecture SIG of EXAMPLE is signal trigger: integer := 0; signal result: integer := 0;begin process(trigger) signal signal1: integer :=1; signal signal2: integer :=2; signal signal3: integer :=3; begin signal1 <= signal2; signal2 <= signal1 + signal3; signal3 <= signal2; result <= signal1 + signal2 + signal3; end process;end SIG;

One of the below examples has an error, find the error

Catch me If

you can!

Sequential Statements

Now let’s introduce sequential statements– Case statement – If statement– loop statements – Wait statement

Think Hardware

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Case Statement

case <expression> is when <choice> =>

-- list of sequential statementswhen <choice> =>

-- list of sequential statementswhen others =>

-- list of sequential statements end case;

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Architecture rtl of mux_case is begin process (a,b,c,d,sel) is begin

Case sel is When "00" =>

f <= a; When "01" =>

f <= b; When "10" =>

f <= c; When "11" =>

f <= d; when others => -- is "when others" a must?

f <= a; End case; End process; End architecture;

Example 4:

Syntax:• Makes several conditions on the same signal

– <expression> can be a signal or a variable– <choice> constants representing one of possible <expression>

values.– “When others” is a must if not all values of <expression> are

covered• Each branch of a Case statement can have any

number of sequential statements

Sel(1:0)

bF

a

c

d

Case Statement

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Architecture rtl of mux_case is begin process (a,b,c,d,sel) is begin

Case sel is When "00" =>

f <= a; When "01" =>

f <= b; When "10" =>

f <= c; When "11" =>

f <= d; when others =>

f <= a; End case; End process; End architecture;

Example 4:

Syntax:

Sel(1:0)

bF

a

c

dDo we need all these signals?

• Makes several conditions on the same signal– <expression> can be a signal or a variable– <choice> constants representing one of possible <expression>

values.– “When others” is a must if not all values of <expression> are

covered• Each branch of a Case statement can have any

number of sequential statements

case <expression> is when <choice> =>

-- list of sequential statementswhen <choice> =>

-- list of sequential statementswhen others =>

-- list of sequential statements end case;

Exercise 1 • The below code is 2x4 Decoder; Complete it by doing the following:

– Declare F as an output port– Add necessary signals to sensitivity list– Add Case statement with all needed branches to create a 2x4 decoder

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Fa

42

library IEEE; use IEEE.std_logic_1164.all; entity decoder2x4 is

port(a: in std_logic_vector(1 downto 0); -- Declare F as an output port<here>

); end entity; Architecture behave of decoder2x4 is Begin

process(<here>) -- Add necessary signals to sensitivity listbegin

-- Add Case statement with all needed branches to create a 2x4 decoder<here>

end process;

End Architecture;

Sequential Statements

• Sequential Statements– Case statement – If statement– loop statements – Wait statement

Think Hardware

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IF StatementIf <condition> then -- list of sequential statementselsif <condition> then -- list of sequential statements

…else

-- list of sequential statementsend if;

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Library ieee; use ieee.std_logic_1164.all;Entity d_ff is Port( d, clk, rst : in std_logic; Q, nQ : out std_logic);end entity;Architecture behav of d_ff is signal Q_int: std_logic;Begin process(clk, rst) begin If (rst = '1') then Q_int <= '0'; elsif rising_edge(clk) then Q_int <= d; end if; end process; Q <= Q_int; nQ <= not (Q_int); end behav;

Example 5:

Syntax:• Executes a list of sequential statements when

the corresponding condition evaluates to true– <condition> Boolean expression that evaluates to

either TRUE or FALSE• The branches order is important as they imply

a priority

Since rst has higher priority over the clk edge

D Flip Flop with asynchronous reset

rising_edge() : defined for std_logic type

Exercise 2 • The below code is D Flip-flop with synchronous reset; Complete it by doing

the following:– Add necessary signals to sensitivity list– Add necessary condition to model the rising edge of the clock– Add nested If statement to model the synchronous reset

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Library ieee; use ieee.std_logic_1164.all;Entity d_ff is Port( d, clk, rst : in std_logic; Q, nQ : out std_logic);end entity;Architecture behav of d_ff is signal Q_int: std_logic;Begin process(...) -- Add necessary signals to sensitivity list begin If (...) then -- Add necessary condition for a rising edge clock ... -- Add a nested If statement to model the synchronous reset end if; end process; Q <= Q_int; nQ <= not (Q_int); end behav;

IF Statement

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LIBRARY ieee; USE ieee.std_logic_1164.all;USE ieee.std_logic_arith.all;

ENTITY add_sub IS port (a, b : in integer; result : out integer; operation: in std_logic); -- add or subtractEND ENTITY add_sub;

ARCHITECTURE behave OF add_sub IS BEGIN process (a, b, operation) begin

if (operation = '1') then -- Add when operation = '1' result <= a + b; else -- Subtract otherwise result <= a - b; end if; end process;END ARCHITECTURE behave;

Example 6:

Exercise 3 • The below code is a simple comparator; Complete it by doing the following:

– Declare 2 bits output port called “result”– Add necessary conditions to model “equal to” and “greater than” Comparisons– Add another “elsif” branch for “smaller than” comparison

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LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; ENTITY comparator IS port(a, b: in std_logic_vector(7 downto 0); -- Declare a 2 bits output port called "result“

); END ENTITY; ARCHITECTURE behave OF comparator ISBEGIN process (a, b) begin if (...) then -- equality result <= "00"; elsif (...) then -- greater than result <= "01"; ... -- Add another "elsif" branch for "smaller than" comparison else -- covers other cases result <= "11"; end if; end process; END ARCHITECTURE;

Contacts

• You can contact us at:– http://www.embedded-tips.blogspot.com/

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