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Aldec – The Design Aldec – The Design Verification CompanyVerification Company

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History - Background

• Founded 1984• Privately Held, revenue funded• Employees 200+• Leading EDA Verification Technologies

• RTL Simulation• HDL STARC Linting Software• Hardware assisted

Acceleration/Emulation • IP Cores• Specialty Solutions• DO-254 Verification Tools• Actel® Prototyping

• Over 30,000 Licenses World-Wide• Several Key Technology Patents• Office Locations:

• Japan, China, France, India• Distribution Channel

Aldec holds an estimated

30% market share in non-OEM simulator sales to FPGA designers.

Aldec wins a majority of competitive engagements. Consistently winning in

technology, flexibility and value.

Aldec holds an estimated

30% market share in non-OEM simulator sales to FPGA designers.

Aldec wins a majority of competitive engagements. Consistently winning in

technology, flexibility and value.

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Product Portfolio

Active-HDL™Graphical Design Entry + Simulator + Multi FPGA Vendor Flow Manager

HDL Language Support: VHDL, Verilog®, EDIF, SystemC and SystemVerilog Operating System Support: Windows® XP and Vista 32/64 bit support

Riviera-PRO™ASIC Simulator + Assertions+ OVM, ESLHDL Language Support: VHDL, Verilog®, EDIF, SystemC, SystemVerilog, SVA and PSLOperating System Support: Windows® XP and Vista 32/64 bit, Linux® 32/64 bit and Sun® Solaris

ALINT™ALINT is a highly optimized design rule checker, which detects design errors in ASIC/FPGA designs. HDL Language Support: VHDL and/or Verilog®Operating System Support: Windows® XP and Vista 32/64 bit and Linux® 32/64 bit

HES™ HES (Hardware Emulation System) All-IN-One Hardware-Assisted Verification System providing Emulation, Acceleration and Prototyping HDL Language Support: VHDL, Verilog®, EDIF and SystemCOperating System Support: Windows® XP and Vista 32/64 bit and Linux® 32/64 bit

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Customers

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A Few of our Industry PartnersA Few of our Industry Partners

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Active-HDL™Active-HDL™

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Better Performance, More Features, Lower Price

Big Brand

The Simulation Performance Standard

Feature OPTIONAL Upgrades

Hidden Costs “Option Upgrade Fees”

25 years in EDA

Comparable & Better Performance

More Features Included

“Low/Minimal Upgrade Fees”

Lower License Prices

Licensing Advantages

Other RTL SimulatorsAldec Simulators

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Aldec Cross-Platform Language Support

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Aldec Simulation Flow

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Active-HDL

• Common-Kernel Mixed Language Simulator, support VHDL, Verilog®, SystemVerilog (Design & Assertions), SystemC & EDIF

• HDL Design Tools: Design entry, Design Creation, Code2Graphics™, Block and State Diagram, Waveform editor, stimulus generation, Language templates & auto-complete, scripting, legacy design support.

• Design Flow Manager: use popular third-party tools throughout the design flow within the same FPGA environment.

• Debugging: Code execution tracing, Waveform/Compare, Memory Viewer, Xtrace, Advanced Dataflow and Profiler.

• Coverage: Code Coverage, Toggle & Functional Coverage.

• Additional Interfaces: DSP/HDL algorithm MATLAB® and Simulink® Interfaces & Zuken CADSTAR PCB Design

• Assertion and Coverage(OPTION) SystemVerilog PSL & OVA support. Dedicated Assertion viewer, coverage, breakpoint editor.

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Active-HDL Configurations

Features Desktop Master (DM)

Designer Edition

Plus Edition (PE)

Expert Edition (EE)

VHDL IEEE 1076

Verilog HDL IEEE 1364

SystemVerilog IEEE 1800 (Design)

Verilog PLI/VPI

EDIF200

Language Interface Wizard (PLI/VPI/VHPI/DPI)

SystemVerilog IEEE DPI w/Wizard

System 2.2 IEEE 1666/OSCI 2.2/TLM 2.0 Option

MATLAB® Co-simulation Option

Xilinx® SecureIP Support VHDL

Synopsys SmartModels®, SWIFT™ Interface Option

SpringSoft® Verdi™ PSD mode Interface Option

ALINT™ with Basic Rule Library Option

Statement/Branch/Conditional/Toggle Coverage Option

Waveform Viewer (AWF and ASDB)

C++ Debugger

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Riviera-PRORiviera-PROTMTM

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Complete Verification Suite

• VHDL, Verilog, SystemVerilog and SystemC support.

• Assertion support (OVA, PSL, SVA, VTL).

• Transaction Level Modeling support.

• New, improved Graphical User Interface with Tcl scripting.

• Command line mode of operation.

• Advanced Debugging and Analysis (post-simulation debug, enhanced waveform, code and functional coverage, dataflow)

• OS Platform independent library support(Linux, including 64-bit, Windows)

• SLP-Verilog simulation provides significant performance gains

• Open IP Protection (simulation of encrypted sources)

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Simulation Engine Improvements

• SLP engine allowing dramatic reduction of simulation time forVerilog RTL, gate-level and timing design descriptions.

• New VHDL Simulation Optimization algorithms.

• Improved support for SystemVerilog standard (classes, DPI, functional coverage, etc.)

• Support for the most recent VHDL standard (IEEE Std 1076-2008).

• Direct interface to compiled SystemC code (Native SystemC interface), bypassing the cumbersome and slow PLI/VHPI interfaces in mixed Verilog/VHDL/SystemC simulations.

• Riviera-PRO simulates IP encrypted with 256-bit key, such as XILINX® Secure IP.

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Assertion-Based Verification

• Support of SVA, PSL and OVA assertions allows implementation of new design verification methods: Easy access to all parts of design under verification (white box

verification), Self-checking Intellectual Property (IP), System protocol checkers, Functional coverage verifying quality of verification algorithm.

• Verification units can be specified in separate files, mixed with HDL units in the same file, or placed in HDL file as special comments.

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Functional Coverage

• SystemVerilog assertions, PSL (Property Specification Language) and OVA (Open Vera Assertion) are supported allowing users to define sequences and properties for cover directives for functional coverage.

• Functional Coverage results are saved to Aldec Coverage Database (ACDB) format for easy management, restoring and merging.

• Coverage results can be viewed directly waveform window, as well as dedicated coverage viewer window for easy debugging.

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C/C++/SystemC Support

• C++ compilers, such as gcc or Microsoft® Visual C++® are supported.

• ccomp command allows easy compilation of PLI, VHPI, DPI or SystemC code.

• addsc command makes compiled SystemC code accessible in Verilog or VHDL code.

• scgenmod command exports HDL module interface to a SystemC file that allows instantiation of VHDL/Verilog in SystemC.

• Simultaneous debugging of C code and HDL code is supported in one, common framework (no application switching required).

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MATLAB® Co-simulation

• MATLAB® interface allows scalar and array data exchange with MATLAB during HDL simulations in Riviera-PRO:

To generate complicated stimulus in a testbench, To describe functionality of some design units at a high level of

abstraction, To post-process simulation data (e.g. compute Fast Fourier

Transform of the DSP block output), To visualize simulation data (statistical analysis, spectral analysis,

etc.)

• Extensive set of procedures and functions supporting this interface is available in VHDL and Verilog.

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Riviera-PRO Configurations

Features AHDL-EE LV LVT LVT-SV

VHDL IEEE 1076

Verilog HDL IEEE 1364

SystemVerilog IEEE 1800 (Design)

System 2.2 IEEE 1666/OSCI 2.2/TLM 2.0

SystemVerilog IEEE 1800-2005 (Assertions)

SystemVerilog IEEE 1800 (Verification)

Verilog Programming Language Interfaces (PLI/VPI)

MATLAB® Co-simulation

Xilinx® SecureIP Support VHDL

Synopsys SmartModels®, SWIFT™ Interface

SpringSoft® Verdi™ PSD mode Interface

ALINT™ with Basic Rule Library

Profiler (Performance Metrics)

SFM (Server Farm Manager) Option

Statement/Branch/Conditional/Toggle Coverage

Integrated Source Level C/SystemC Debugger

Linux x86/x86_64 x86

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ALINT™ALINT™

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Enhanced Plug-ins Rules

• Aldec (basic plug-in) ALDEC_VHDL ALDEC_VLOG

• STARC (best industry practices by Semiconductor Technology Academic Research Center, Japan)

STARC_VHDL STARC_VLOG

• DO-254/ED-80 (special for safety critical avionics designs) DO254_VHDL DO254_VLOG

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ALINT™

• New rules in existing plug-ins (ALDEC, STARC, DO-254).

• New optional plug-in for RMM (Reuse Methodology Manual)

• Extended support for FPGA Vendor Primitives (Altera, Xilinx).

• Enhanced linting engine (CDC, TestBench features).

• New productivity tools in GUI (wizards, design quality reports).

• Number of corrections and bug fixes.

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HESHES

HHardwareardware EEmulationmulation SSystemystem

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HES Environment

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HES Ecosystem

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Hardware Supported

• Off-the-shelf FPGA boards High speed prototyping High capacity

• Immediate Advantages Reuse for acceleration Reuse for emulation Better Return on Assets Reduces capital spending

DINIDN9000K10PCIcapacity up to: 10M ASIC gates

DINIDN8000K10capacity up to: 24M ASIC gates

ALDECHES5XLX660EXcapacity up to: 4M ASIC gates

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HES Interfaces

• Acceleration Direct link to Aldec simulators kernel PLI interfaces for 3rd party simulators SystemC/C++ bit-level, cycle accurate

• Emulation SCE-MI for transaction level testbenches SystemC/C/C++ for virtual modeling Vector based interface for bit level emulation

• Prototyping C/C++ to connect virtual models and high-level testbenches

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Design Verification Manager (DVM) Features

Multi-HDL support (Verilog, SystemVerilog, VHDL, SystemC, C/C++)

Static and Dynamic debug options Supports excluding instances from

hardware by using Black-Box feature Incremental and block design synthesis Automatic ASIC clock conversion to

FPGA Automatic partitioning and

multiplexing of interconnections FPGA implementation flow management Console mode for scripting (TCL) Seamless integration with all HDL

simulators (PLI, VHPI, etc.); direct link with the Aldec simulator

kernel (performance!) HES-API available for C-testbench SDRAM, DDR and other external

memories support

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Transaction-LevelSCE-MI Emulation

Software Side (host workstation) Hardware Side (emulator)

SCE-MI Infrastructure

DUTTransactor 1

Transactor 2

UTC Model

UTC Model

RTC Model

UTC Model

C/C++ kernelsuch as SystemC

Clock/ResetGenerationand Control

Message PortProxy 1

Message PortProxy 2

Message PortProxy 3

Message Port 1

Message Port 2

Message Port 1

The picture is taken fromSCE-MI Reference Manual version 2.0

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DVM Configurations

Features Pototyping (Proto)

Acceleration (Xcell)

Emulation (Elite)

Design Verification Manger [DVM™]

Automatic Design Partitioning w/ LVDS Signal Multiplexing

Blackbox Functionality (Excludes modules)

Static Debugging Probes

Static Debugging Probes w/ Xilinx ChipScope™ Pro

Static Debugging Probes w/ Aldec LA (ALA for SCE-MI)

Dynamic Probes (for SCE-MI)

Clock Conversion and Analysis

Memory Model Mapping (maps to on-board memory)

Prototyping API and function library (interface with C++)

HDL Co-Simulator Interface (Aldec/CDNS/MG/SNPS)

SCE-MI 2.0 HW/SW Infrastructure (SCE-MI C++ API)

C/C++/SC Testbench Wrapper

OVL Assertions Support

Vector Based Emulation

Multi-FPGA Boards Support Option Option