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Section B

A Step-By-Step Description of the Synplicity Flow

Andy Miller © Copyright 2000 Xilinx- All Rights Reserved

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Synplicity Flow - Start New Project


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Synplicity Flow - Start New Project

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2

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4

Set a New file location to be your SysGen working directory

2

Select...File->New

3 Click “OK”

4 Double-click on “ProjectFile” to accept it.


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Synplicity Flow - Add SysGen Files

1

2

3

4

5

Now we add the System Generatorfiles to the new Synplicity Project.

2

Select.. File->Add File.

3 Because you completed Step2 on the previous page, a listof SysGen VHD files will appear in this window.

4

Note that the default HDLis Verilog. Click on the down arrow and select *.VHD.

5

If they did not, then navigateto where you told SysGen to put them with the SysGen GUI.

Select the “Add All” button and watch them appear in thelower window.

1


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Synplicity Flow - Add SysGen Files1 Now we add the System Generator

VHDL descriptions of any modulethat cannot be mapped to a COREGeneratorTM core.

These files are stored in:$Matlab12/toolbox/xilinx/sysgen/vhdl

2Select the “Add All” button - thisit is the quickest way to get all the components you need in one go!

NOTE: You will also see componentsthat you do not need; the synthesistool ignores everything except theFIFO core, which I will mentionon the next foil.


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Synplicity Flow - Order the Files1

2 Note that you must move the conv_pkg using the same click and drag technique so that it occupies the second position in the list.

….. Sometimes I wonder if synthesis really is easier!


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Synplicity Flow - Compile the design1

Select RUN -> Compile to seeif the synthesis tool is happy with the files and their order.

At this stage, you may get anERROR from the xlfifo_core.vhdfile if you forgot to delete it.

Simply delete it and hit F7, or repeat Step 1.

2


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Synplicity Flow - Select Device1 Now you are almost ready to synthesize the design; you just need to choose the target

device and identify where the output files will be placed. Select “Impl Options.”

Choose the target family.(Note that only Xilinx Virtex/E/II and Xilinx Spartan-II will work.)

Choose the part.

Choose the speed grade.(Note -6 = slowest; -8 = fastest)

Choose the package.

Select the Options/Constraints tab.

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6


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Synplicity Flow - Target the OutputSelect to where the target files are going to be written.1

2 Select “OK.”


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Synplicity Flow - Synthesize the design

Now Synthesize the design by hitting the RUN button.

1


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- Watch how it speeds along :o)

As Synplicity is running, it indicates what it is doing.It can sometimes be in the mapping phase for a long time.


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Synplicity Flow - View the RTL diagram

When Synplicity has completed the design, click on thisicon to view the RTL (Register Transfer Level) view of the design. This is a logicalrepresentation of the design, and there is normally a 1-to-1 correlation between theblocks within the Simulink diagram and the Sythensis diagram.


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View the Technology Mapped ResultNow click on this icon to see how Synplicity has actually mapped the design.It will be at this stage that you can sometimes notice the effect of NOT choosingto use CORE Generator Cores.

If you use COREGen cores, you will not be able to navigate into the hierarchy using this icon.

Xlmult: This is a COREGen Core, and it cannot be traversed with the hierarchy viewer because the EDIF has been created by CORE Generator. The Synthesis tool treats this block as a black box.


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View the Technology Mapped Result

Now click on this icon to see how Synplicity has actually mapped the design.At this stage, you can also sometimes notice the effect of NOT choosingto use CORE Genenerator Cores.

If you use COREGen cores, you will not be able to navigate into the hierarchy using this icon.

(Press your “Page Down” key to end the presentation.)

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