X-ISCKERReconfigurable Platform for the Emulation of RISC and CISC Architectures

Jose Pablo PinillaUniversidad Pontificia Bolivariana

Bucaramanga, Colombiajose.pinilla@upb.edu.co

Alfredo GualdrónUniversidad Pontificia Bolivariana

Bucaramanga, Colombiaalfredo.gualdron@upb.edu.co

Abstract—This is a project planned to illustrate the structure and operational foundations of Central Processing Units, through the implementation of a configurable system with two processors, one RISC (Reduced Instruction Set Computing) and one CISC (Complex Instruction Set Computing), on an FPGA (Field Programmable Gate Array), along with a programming and monitoring user interface software.

Index Terms—Computer Architecture, RISC, CISC, FPGA, Embedded Processors.

I. INTRODUCTION

Computer organization and computer architecture design courses rely mostly on commercial microcontrollers that can be used in application projects. But being commercial implies that those are closed designs, meaning their documentation leaves organization details unmentioned. Another educational option is the use of simulation programs, which can be very detailed but lack the applicability of an Integrated Circuit (IC).

X-ISCKER or Reduced/Complex Instruction Set Computing Key Educational Resource is a software-hardware platform that combines the applicability of a microcontroller IC with the detailed functionality and monitoring capabilities of a processor simulator. It is based on the development of two basic architectures, one RISC and one CISC, in Verilog HDL for any FPGA, an IDE (Integrated Development Environment) software and a thorough documentation of their functionality.

Fig. 1. X-ISCKER Platform.

The user is able to emulate any of the two architectures in an FPGA while monitoring its state during the execution of any program written in its corresponding assembly language. The IDE is capable of “assembling and linking”, programming, and

debugging functionalities for the two processors, called RISCKER and CISCKER. A stand-alone application of the processors is also available, without the IDE-FPGA communication. The final stage of development for the platform is “Reconfiguration”. The availability of all source code is an invitation to modify the provided architectures.

Figure 1 is a diagram of the X-ISCKER platform including the communication module.

II. RISCKER PROCESSOR

A RISC processor instruction set and organization is designed so that it represents this architecture’s characteristics, such as: A large amount of registers, few Instructions of the same width and logical-arithmetic operations only between registers.

This processor’s structure is similar to the Multi-cycle MIPS described by Patterson and Hennessy [1] in order to facilitate the change between this system and a commercial MIPS-based processor in terms of code compatibility and structural behavior. An approximation of the design is shown in figure 2, highlighting the main units and signals, while an overview of the main characteristics for its operation can be seen on table 1.

Fig. 2. RISCKER Observer.

TABLE I. RISCKER PROCESSOR

III. CISCKER PROCESSOR

This CISC processor is based on the instruction set of the Motorola (now Freescale) HC08 and HC11 series which symbolizes the characteristics of CISC Architecture, with features like: Small set of registers with specific purposes, several addressing modes and therefore a large amount of instructions with different widths. Figure 3 contains a diagram that represents the main units and signals of this processor, whereas table 2 shows its main characteristics comparable to the ones of the RISCKER processor.

Fig. 3. CISCKER Observer

IV. X-ISCKER PLATFORM

The X-ISCKER platform has three main functions identified as Emulation, Application, and Reconfiguration. These functions make use of all the capabilities and resources provided. Figure 4 shows the GUI (Graphic User Interface) of

the X-ISCKER IDE main window where secondary tools can be accessed.

TABLE II. CISCKER PROCESSOR

A. Emulation

Emulation allows the user to monitor the behavior of the implemented processor in the FPGA through a serial communication of the processors state during the execution of any programmed algorithm. Both tasks, programming and monitoring, are made through the X-ISCKER IDE, which provides an Assembler interface, the X-ISCKER Programmer and the X-ISCKER Observer. Figures 2 and 3 are screenshots of the X-ISCKER Observer tool for the RISC and CISC architectures correspondingly.

B. Application

The platform is aimed to application projects in which the programmer is already familiarized with the organization of the processors. The X-ISCKER IDE performs the assembling functions of the two assembly languages while the Programmer tool is used with an HDL description of the chosen processor without the emulation functions, letting the hardware run at higher frequencies and use less FPGA resources.

C. Reconfiguration

The main target of the project is to provide a prototyping tool for different processor topologies by adding, removing, changing or mixing the features of any of the two given architectures. This is done in order to promote design propositions and give a better introduction to computer architecture trends, such as DSP (Digital Signal Processing), dynamic instruction sets and multi-core computing as well as different types of parallelism (Data-level, Thread-level and Instruction-Level Parallelism).

Fig. 4. X-ISCKER IDE.

V. STUDENTES EXPERIENCE

Throughout the days following the presentation of the X-ISCKER platform to the academic evaluators and the engineering community at the UPB (Universidad Pontificia Bolivariana), there was positive feedback and more importantly the students showed interest on the further development of this platform. According to previous definition of future projects related to the X-ISCKER platform, the development of a multi-platform assembler is proposed as a course project for the Informatics Engineering students taking the Computer Architecture course at the UPB. This is a development guided by the developers of the platform where information voids were filled with further documentation and where students were required to understand the operation of the RISCKER processor in order to develop a fully operational assembler using Java. A step by step description of this

development is posted on the Computer Architecture course web page for Informatics Engineers[2], and all finished and tested results are linked to the X-ISCKER site.

This experience shows that the X-ISCKER platform is not only useful for digital circuit designers but also for software designers, covering a wide range of research areas where students can start developing their ideas.

VI. SUMMARY

Today’s architectures have grown to be more complex due to compatibility-guided development and the addition of necessary advanced features, making them “difficult to explain and impossible to love” [1]. This demands a very solid introduction of computer architecture trends and evolution, by empirically studying the principles from which modern processors are ruled and allowing the designer to test its models according to their knowledge and application requirements.

The X-ISCKER platform delivers the Verilog HDL description of two processors, an IDE software and the documentation that will allow new learners to familiarize with computer architecture foundations, and computer designers to come up with custom embedded processor solutions to their applications.

The source files for the X-ISCKER platform and related further development will be kept available at the ADT (Advanced Digital Technologies) students’ research group of the UPB website [3]..

REFERENCES

[1] D. Patterson and J. Hennessy, “Computer Organization and Design”, Morgan Kaufmann Publishers, 2005.

[2] H. A. Becerra (2012, Oct 1), “Proyecto ENSAMBLADOR X-ISCKER”, Available: https://sites.google.com/site/22012archcompupb/proyecto-ensamblador-x-iscker

[3] A. Gualdrón and J. P. Pinilla (2012, Jul 2), “Semillero ADT - XISCKER”, Available: http://semilleroadt.upbbga.edu.co/xiscker

[4] S. G. Shiva, “Computer Organization Design and Architecture”, 4th Edition, CRC Press, 2008.