x-wall mx-128; x-wall mx-192; x-wall mx-256 x-wall mx-128c; x … mx... · 2014. 6. 23. · 2.0...

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X-Wall MX Specification Rev 2.1 Sept212010.doc Enova Technology Corporation Confidential Copyright © 2010. Enova Technology Corporation. All rights reserved. Page 1 of 28 X-Wall MX-128; X-Wall MX-192; X-Wall MX-256 X-Wall MX-128C; X-Wall MX-192C; X-Wall MX-256C Serial ATA Real-time Full Disk Encryption Processor Specification Rev. 2.1 Revision History Rev No. Description Author Rev. Date 1.0 Initial release. C. Y. Chiu, R. Wann, L. Lee 01/23/2007 1.1 Revised x58 & x59 API Command. C. Y. Chiu 05/24/2007 1.2 Add key byte information related to API command; Modify API programming. C. Y. Chiu, R. Wann 06/06/2007 1.3 Add 1.8V and 3.3V Power Consumption; Add BOM of circuit layout; General document editing. C. Y. Chiu L. Lee R. Wann 07/19/2007 1.3.1 Revise cfgXWall on page 17 under CCR; General document editing. C. Y. Chiu R. Wann 08/07/2007 1.3.2 Redefine Pin24; Pin43; Pin45, Pin46, Pin50 Update Typical Application Schematics L. Lee R. Wann 08/30/2007 1.4 Correction of AES key order convention; Reflect ECN 001 MX10092007; Sync2PHY connects to VDD3.3V C. Y. Chiu R. Wann 01/25/2008 1.5 Update MX Reference Schematics; Revise definition of Pin 13; Revise definition of Pin 37; C. Y. Chiu Butz Huang R. Wann 06/18/2008 1.5.1 Update signal routing and typical BOM Butz Huang 07/01/2008 1.5.2 Updating Packaging Information R. Wann 07/15/2008 1.6 Document changes required at Pin#44 ‘pmMode’ (page 7) to work with Silicon Image SATALink SPIF 215A USB/SATA bridge controller B. Huang C. Y. Chiu R. Wann 0723/2008 1.7 Redefine Pin#17 Sync2Phy & Pin#34, 51; Redefine Operating Temperature; C. Y. Chiu R. Wann 02/06/2009 1.8 Add SATA signal layout; Add PCB parameters with differential signals on page 13; Document changes required to work with Oxford OXUF934DSB bridge controller on page 8 & 9; C. Y. Chiu R. Wann 06/24/2009 1.9 Add patent, layout, and contact Information R. Wann 07/29/2010 2.0 Update Pin#21 CfgHost definition on page 8 in RED. C. Y. Chiu 08/17/2010 2.1 Update SEEPROM protocols on page 15; Select Atmel & Microchip 24LC02B on page 9; R. Wann 09/21/2010 Intentionally left blank Asia Pacific North America Enova Technology Corporation Enova Technology 1 st Floor, #11, Research & Development 2 nd Rd. 1918 Junction Avenue Science-based Industrial Park, Hsin-Chu City San Jose, California 95131, USA Taiwan 30076, Republic of China P +1 408.679.2949 P +886 3 577 2767 F +886 3 577 2770 http://www.enovatech.com www.enovatech.net ; [email protected] ; www.enovatech.com ; [email protected]

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Page 1: X-Wall MX-128; X-Wall MX-192; X-Wall MX-256 X-Wall MX-128C; X … MX... · 2014. 6. 23. · 2.0 Update Pin#21 CfgHost definition on page 8 in RED. C. Y. Chiu 08/17/2010 2.1 Update

X-Wall MX Specification Rev 2.1 Sept212010.doc

Enova Technology Corporation Confidential Copyright © 2010. Enova Technology Corporation. All rights reserved. Page 1 of 28

X-Wall MX-128; X-Wall MX-192; X-Wall MX-256

X-Wall MX-128C; X-Wall MX-192C; X-Wall MX-256C Serial ATA Real-time Full Disk Encryption Processor

Specification Rev. 2.1

Revision History Rev No. Description Author Rev. Date

1.0 Initial release. C. Y. Chiu, R. Wann, L. Lee

01/23/2007

1.1 Revised x58 & x59 API Command. C. Y. Chiu 05/24/2007 1.2 Add key byte information related to API command; Modify

API programming. C. Y. Chiu, R.

Wann 06/06/2007

1.3 Add 1.8V and 3.3V Power Consumption; Add BOM of circuit layout; General document editing.

C. Y. Chiu L. Lee

R. Wann

07/19/2007

1.3.1 Revise cfgXWall on page 17 under CCR; General document editing.

C. Y. Chiu R. Wann

08/07/2007

1.3.2 Redefine Pin24; Pin43; Pin45, Pin46, Pin50 Update Typical Application Schematics

L. Lee R. Wann

08/30/2007

1.4 Correction of AES key order convention; Reflect ECN 001 MX10092007; Sync2PHY connects to VDD3.3V

C. Y. Chiu R. Wann

01/25/2008

1.5 Update MX Reference Schematics; Revise definition of Pin 13; Revise definition of Pin 37;

C. Y. Chiu Butz Huang

R. Wann

06/18/2008

1.5.1 Update signal routing and typical BOM Butz Huang 07/01/2008 1.5.2 Updating Packaging Information R. Wann 07/15/2008 1.6 Document changes required at Pin#44 ‘pmMode’ (page 7) to

work with Silicon Image SATALink SPIF 215A USB/SATA bridge controller

B. Huang C. Y. Chiu R. Wann

0723/2008

1.7 Redefine Pin#17 Sync2Phy & Pin#34, 51; Redefine Operating Temperature;

C. Y. Chiu R. Wann

02/06/2009

1.8 Add SATA signal layout; Add PCB parameters with differential signals on page 13; Document changes required to work with Oxford OXUF934DSB bridge controller on page 8 & 9;

C. Y. Chiu R. Wann

06/24/2009

1.9 Add patent, layout, and contact Information R. Wann 07/29/2010 2.0 Update Pin#21 CfgHost definition on page 8 in RED. C. Y. Chiu 08/17/2010 2.1 Update SEEPROM protocols on page 15; Select Atmel &

Microchip 24LC02B on page 9; R. Wann 09/21/2010

Intentionally left blank Asia Pacific North America Enova Technology Corporation Enova Technology 1st Floor, #11, Research & Development 2nd Rd. 1918 Junction Avenue Science-based Industrial Park, Hsin-Chu City San Jose, California 95131, USA Taiwan 30076, Republic of China P +1 408.679.2949 P +886 3 577 2767 F +886 3 577 2770 http://www.enovatech.com www.enovatech.net; [email protected]; www.enovatech.com; [email protected]

Page 2: X-Wall MX-128; X-Wall MX-192; X-Wall MX-256 X-Wall MX-128C; X … MX... · 2014. 6. 23. · 2.0 Update Pin#21 CfgHost definition on page 8 in RED. C. Y. Chiu 08/17/2010 2.1 Update

X-Wall MX Specification Rev 2.1 Sept212010.doc

Enova Technology Corporation Confidential Copyright © 2010. Enova Technology Corporation. All rights reserved. Page 2 of 28

Table of Content Table of Content ....................................................................................................... 2 Introduction .............................................................................................................. 3

How does it work?........................................................................................................... 3 Key Management ............................................................................................................ 4 Key Benefits .................................................................................................................... 4 Features .......................................................................................................................... 4 System Requirement....................................................................................................... 5 Ordering Codes............................................................................................................... 5

X-Wall MX Pin Definitions........................................................................................ 6 Pin Assignment ............................................................................................................... 6 Pin Definition and Description ......................................................................................... 7

Electrical Characteristics ...................................................................................... 10 Absolute Maximum Ratings .......................................................................................... 10 DC Characteristics .........................................................................................................11

PCB Layout Guidelines.......................................................................................... 11 Typical Application Schematics ......................................................................................11 Typical Bill of Materials (BOM) ...................................................................................... 12 Component Placement.................................................................................................. 13 PCB Trace Routing ....................................................................................................... 13

SATA Signal Layout ................................................................................................13 PCB Parameters of Differential Signals ..................................................................14

X-Wall MX Interface for Key Loading.................................................................... 15 AES Key Ordering Convention...................................................................................... 15 X-Wall MX 2-wire Serial Interface Basic ....................................................................... 16 X-Wall MX Configuration Protocol through 2-wire Serial Interface................................ 16 X-Wall MX API Configuration Protocol through SATA interface .................................... 20

X-Wall MX API Commands......................................................................................21 X-Wall MX API Configuration Protocol...................................................................23

Power-On Sequence .............................................................................................. 25 X-Wall MX Configuration Management................................................................. 27

Hardware Packaging..................................................................................................... 27 Firmware Release ......................................................................................................... 27 Hardware Version Control, Outline, and Dimension...................................................... 27

Page 3: X-Wall MX-128; X-Wall MX-192; X-Wall MX-256 X-Wall MX-128C; X … MX... · 2014. 6. 23. · 2.0 Update Pin#21 CfgHost definition on page 8 in RED. C. Y. Chiu 08/17/2010 2.1 Update

X-Wall MX Specification Rev 2.1 Sept212010.doc

Enova Technology Corporation Confidential Copyright © 2010. Enova Technology Corporation. All rights reserved. Page 3 of 28

Introduction The patented1 X-Wall® MX family ASIC (Application Specific Integrated Circuit) is the 7th generation of X-Wall real-time Full Disk Encryption technology. It is engineered specifically to encrypt/decrypt entire SATA hard drive including boot sector and operating system without performance degradation. The cryptographic engine of the X-Wall MX is NIST (National Institute of Standards and Technology) and CSE (Communications Security Establishment) certified hardware AES (Advanced Encryption Standard) algorithm. Certain X-Wall MX processors are currently pending review of an FIPS 140-2 certification process. How does it work?

X-Wall MX, an SATA to SATA cryptographic bridge chip, sits between motherboard host SATA and the device SATA hard drive, encrypting entire SATA drive with wire speed performance while providing up to 256-bit AES hardware strength. System performance with X-Wall MX engaged is unaffected. X-Wall MX can be operated with SATA 1.0a and SATA 2.6 compliant disk drives 2 with a sustained cryptographic throughput of 150MB/sec. The performance-optimized AES hardware engine performs all encryption and decryption. There are no extra software components, eliminating entirely the memory and interrupt overheads. X-Wall MX requires no device driver and is independent from and invisible to all known Operating Systems including embedded OS. As long as the drive is SATA 1.0a and SATA 2.6 compliant, X-Wall MX will work in

1 US patents 7,136,995; 7,386,734; and Application 11/282,175. Taiwan & PR China patent 625110. 2 SATA 3Gbit drives can be operated on the X-Wall MX without performance degradation.

Page 4: X-Wall MX-128; X-Wall MX-192; X-Wall MX-256 X-Wall MX-128C; X … MX... · 2014. 6. 23. · 2.0 Update Pin#21 CfgHost definition on page 8 in RED. C. Y. Chiu 08/17/2010 2.1 Update

X-Wall MX Specification Rev 2.1 Sept212010.doc

Enova Technology Corporation Confidential Copyright © 2010. Enova Technology Corporation. All rights reserved. Page 4 of 28

the system. Once authenticated, its operation is completely transparent to all users. There is no complex GUI involved therefore your regular computing behavior is unchanged. Key Management Key Management with X-Wall MX can be versatile, which includes PIN/Password through Pre-boot authentication, TPM1.2, CAC/PIV Smartcard, Fingerprint, Single Sign On, or USB type external key token. One or more factor authentications are applicable through either built-in two-wire serial interface or API (Application Programming Interface) through SATA bus. As the entire SATA hard drive is encrypted, there is no possibility of any secret being left unprotected on the drive, including password and “Secret Key.” In an X-Wall MX protected system (drive), there is no simple way to read the data without the right “Secret Key.” Only YOU have the right Key to unlock your data. The X-Wall MX technology is compatible with all system designs incorporating SATA hard drive technologies. Key Benefits

FIPS 140-2 certification review pending Offers wire speed performance at sustained3 150MB/sec on all cryptographic strengths Operating System independent Provides iron-clad security through hardware-based NIST & CSE certified cryptographic AES engine

in both ECB and CBC mode of operation Simplify engineering design for security targets Configurable host and device SATA ports Multiple key load allows key swapping for drive deployment & repurposing

Features

Built-in Power-On-Self-Test (POST) ability to ensure product reliability POST includes cryptographic function tests Patented Crypto/Bypass mode switching capability4 Versatile Key Management through either serial interface or built-in API (Application Programming

Interface) 100% hardware AES (both ECB and CBC mode of operation) cryptographic engine producing

sustained 150MB/sec real-time performance Very low power consumption (<400mW under continuous burst) 80-pin TQFP small form factor RoHS & Lead-free compliant 5 (Five) years warranty for defective part Military grade operating temperature from -45 to +90

3 Please reference to test reports at

http://www.enovatech.net/support/download/X-Wall%20MX%20Test%20Report_Part%202.pdf. 4 Crypto/Bypass mode switching is an important technology that allows read/write of clear/cipher text data

off the SATA drive at designer’s discretion over unique application. Consult Enova Technology engineering support for this enhanced feature.

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Enova Technology Corporation Confidential Copyright © 2010. Enova Technology Corporation. All rights reserved. Page 5 of 28

System Requirement All Microsoft Windows Operating Systems Linux OS with SATA support All embedded OS with SATA support SATA 1.0a & SATA 2.6 compliant hard drives

Ordering Codes

Stock Keeping Unit Description Mode of Operation

(crypto mode)

X-Wall MX-128 SATA real-time full disk encryption

processor with AES 128-bit strength

ECB

X-Wall MX-192 SATA real-time full disk encryption

processor with AES 192-bit strength

ECB

X-Wall MX-256 SATA real-time full disk encryption

processor with AES 256-bit strength

ECB

X-Wall MX-128C SATA real-time full disk encryption

processor with AES 128-bit strength

CBC

X-Wall MX-192C SATA real-time full disk encryption

processor with AES 192-bit strength

CBC

X-Wall MX-256C SATA real-time full disk encryption

processor with AES 256-bit strength

CBC

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X-Wall MX Specification Rev 2.1 Sept212010.doc

Enova Technology Corporation Confidential Copyright © 2010. Enova Technology Corporation. All rights reserved. Page 6 of 28

X-Wall MX Pin Definitions Pin Assignment All X-Wall MX family ASIC shares the same pin assignment and pin definition. Upgrading from a lower strength, for instance, from an X-Wall MX-128 to an X-Wall MX-256 is as easy as replacing the chip and the actual Secret Key.

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Pin Definition and Description PHY INTERFACE

NAME PIN* DIR TYPE DESCRIPTION RxPA RxNA

66 65

I Received differential input signals for channel A (channel #0).

TxPA TxNA

62 61

O Differential serial output transmitted signals for channel A (channel #0).

RxPB RxNB

68 67

I Received differential input signals for channel B (channel #1).

TxPB TxNB

72 71

O Differential serial output transmitted signals for channel B (channel #1).

ResRef 74 I/O Reference register, terminated to pin VSSREFREF through 2.7K±1% ohms.Total 9

CLOCK AND PLL CONTROL PINS

NAME PIN DIR TYPE DESCRIPTION I Crystal/reference clock input XTALI

XTALO 38 39 O

Crystal output

RefClkSel_0 RefClkSel_1

45 46

I Reference clock frequency selection RefClkSel Frequency (MHz) 0 0 25 0 1 75 1 0 150 1 1 Reserved

PLLEna 42 I PLL enabled for normal operation. If it is asserted LOW, then the PLL is powered down.

PLLTest 37 I Default No Connect, which selects 400 KHz speed of the 2-wire serial interface; Pull high to 3.3V to enable 100 KHz speed of the 2-wire serial interface.

Total 6 FEATURE SETTING PINS

NAME PIN DIR TYPE DESCRIPTION ByPassN 9 I Hardware traps for cryptographic engine enabling. Connecting to GND

enables bypass mode operation.

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X-Wall MX Specification Rev 2.1 Sept212010.doc

Enova Technology Corporation Confidential Copyright © 2010. Enova Technology Corporation. All rights reserved. Page 8 of 28

PmMode 44 I Built-in API command through Port Multiplier (PM) mode selection. When it is asserted HIGH, X-Wall MX will use control port address 0F (15) for API. If it is asserted LOW, then the X-Wall MX will use port address 0E (14) for API. Normally, disk access occupies port 0E (14). Don’t care if command x58 and x59 are being utilized. In the case that Silicon Image SPIF215A USB/SATA bridge controller is utilized to connect with the X-Wall MX chip, the SPIF215A will issue Software Reset command to port 0F (15) at initialization. As X-Wall MX by default, utilizes port 0F (15) for built-in API command thus it does not respond to the Software Reset command, causing a freezing condition. To solve that, grounding Pin#44 ‘pmMode’ to select port 0E (14) for API command so that port 0F (15) of X-Wall MX will respond to SPIF215A ‘s Software Reset command and will be ready for regular disk access. Also reference to the X-Wall MX reference schematics for proper implementation. In the case that Oxford OXUF934DSB bridge controller is utilized to operate with the X-Wall MX, the OXUF934DSB issues Software Reset command to port x0F (15) at initialization. As X-Wall MX by default, utilizes port x0F for built-in API command thus it does not respond to the Software Reset command, causing a freezing condition. To solve that, grounds Pin#44 ‘pmMode’ (the default is NC) to select port x0E (14) for MX API command. More, set CfgHost of X-Wall MX to 0 (the default is 1). In addition, if the CfgHost=0, the OXUF934DSB disables HDD_POWER by GPIO#8. The firmware modification of the controller is required for proper power management, or manage power through different source.

Total 2 CONTROL AND INDICATOR SIGNALS

NAME PIN DIR TYPE DESCRIPTION SysReset 18 I Hardware master reset.

Sync2PHY 17 I Use (asserted HIGH) PHY sync mode for data transfer. TlrDspErr 12 I Tolerate disparity errors of ALIGN primitives during OOB. PSCROff 16 I Turn off (HIGH) primitive scrambler for transmit. DSCROff 15 I Turn off (HIGH) data scrambler for transmit/receive. SSCOff 14 I Turn off (HIGH) SSC mode for transmit.

POSTOff 13 I Default No Connection. Pull high to 3.3V turns OFF Power-On-Self-Test feature of cryptographic engine. Suggest leaving as default.

KeyErr 24 O A HIGH at this pin indicates that the AES Secret Key is missing. The X-Wall MX enters into Bypass mode. A LOW at this pin indicates that the AES Secret Key presents and the X-Wall MX is in Crypto mode operation.

34 51

No Connect.

BistErr 23 O If BIST is set to logical ONE, a HIGH at this pin indicates that the build-in-self-test (BIST) in PHY has failed.

EngErr 22 O A HIGH at this pin indicates that the Power-On-Self-Test for the X-Wall MX Cryptographic Engine has failed.

DatXfer 43 O A low-active signal. A LOW at this pin indicates that X-Wall MX has detected data transfer activities on its channels.

CfgHost 21 I Internally pull-high. Selecting host/device for channel#0 and channel#1. Please read in conjunction with Pin# 44 ‘pmMode’.

cfgHost Channel#0 Channel#1 1 MX Ch#0 behaves like a

Device that needs to be connected to a Host.

MX Ch#1 behaves like a Host that needs to be connected to a

Device. 0 MX Ch#0 behaves like a Host MX Ch#1 behaves like a Device

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Enova Technology Corporation Confidential Copyright © 2010. Enova Technology Corporation. All rights reserved. Page 9 of 28

Total 14 TWO-WIRE SERIAL INTERFACE

NAME PIN DIR TYPE DESCRIPTION SDAH 48 I/O 2-wire Serial data. Pull high to 3.3V through 1.5KOhm resistor. See also

typical application schematics. SCLH 47 I/O 2-wire Serial clock. Pull high to 3.3V through 1.5K Ohm resistor.

See also typical application schematics. Total 2 * Select 24LC02B EEPROM through either Atmel or Microchip.

JTAG TEST PINS

NAME PIN DIR TYPE DESCRIPTION TCK 5 I Test clock. TDI 3 I Test data input. TDO 4 O Test data output. TMS 6 I Test mode select. TRST 7 I Test reset. Total 5

DEBUG INTERFACE

NAME PIN DIR TYPE DESCRIPTION IDDQEn 1 I When asserted HIGH, SataPhy is placed into iDDQ test mode, whereby all

PLLs are disabled. This input is used for leakage current testing. The power on reset signal (pOR) must be asserted high prior to taking an iDDQ measurement. When negated LOW, all PLLs resume to normal functional state.

Bist 2 I Turn on (HIGH) build-in-self-test mode of PHY. LbEn 25 I PHY loop back mode enabled for testing.

lbEn cfgHost Loop back mode 1 0 Far-end 1 1 Near-end 0 - Normal operation

TestIO TestC TestE

50 77 78

NCI I

Select test modes for scan tests and functional tests.

testIO testC testE MODE 0 0 0 Normal operation 0 0 1 Scan test #1 0 1 0 Scan test #2 0 1 1 Functional tests 1 0 0 PHY transmit LFTP (D30.3)1 0 1 PHY transmit MHTP (D24.3)1 1 0 PHY transmit HFTP (D10.2)1 1 1 PHY transmit LBP

Total 6 POWER GROUND

NAME PIN DIR TYPE DESCRIPTION VDD18ANA 57

76 Analog 1.8V power supply for all PLLs of Serial ATA PHY.

VSSANA 58 75

Analog ground of VDD18ANA.

VDDSATA 60 56 53

Digital 1.8V supply for Serial ATA PHY core.

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VSSSATA 59 55 54

Digital ground of VDDSATA.

VSSRESREF 73 Analog ground returned for the external resistor reference. Connect a reference resistor between this pin and pin ResRef.

VDDP 63 69

1.8V analog power supply for Serial ATA PHY high speed I/O

VSSP 64 70

Analog ground for Serial ATA PHY high speed I/O.

VDD33XW 19 41 79

Digital 3.3V supply for chip I/O.

VDD18XW 11 28 36 49

Digital 1.8V supply for chip core.

VSS33XW 20 40 80

Digital ground for chip I/O.

VSS18XW 8 10 26 27 33 35 52

Digital ground for chip core.

VDD18PLL 29 1.8V digital power supply for PLL core. VSS33PLL 32 Analog ground for PLL. VAA33PLL 31 Analog 3.3V supply for PLL. VSS18PLL 30 Digital ground for PLL core.

Total 36

Electrical Characteristics This section contains electrical specifications for the X-Wall MX. Please note, however, stressing conditions beyond the “Absolute Maximum Ratings” may cause permanent damage to the X-Wall MX device. Operating beyond the “operating conditions” is not recommended and extended exposure beyond “operating conditions” may adversely affect life and reliability of the X-Wall MX device. Absolute Maximum Ratings

Value Symbol Parameter

Min Max

Unit

Ts Storage Temperature -55 +125 oC

Ta Operating Temperature -45 +90 oC

VDD33 3.3V Digital Supply Voltage -0.5 3.6 V

AVDD33 3.3V Analog Supply Voltage -0.5 3.6 V

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VDD18 1.8V Digital Supply Voltage -0.5 1.93 V

AVDD18 1.8V Analog Supply Voltage -0.5 1.93 V

VIN_IO33 Input Signal Voltage

(Apply to 3.3V I/O pins)

-0.5 5 V

VO_IO33 Output Signal Voltage

(Apply to 3.3V I/O pins)

-0.5 VDD33 V

DC Characteristics Operating Conditions: VDD33=AVDD33=3.3V (±9.09%),

VDD18=AVDD18=1.8V (±7.22%), GND=0V

Value Symbol Parameter

Min Max

Unit

VDD33 3.3V Digital Supply Voltage 3.0 3.6 V

AVDD33 3.3V Analog Supply Voltage 3.0 3.6 V

VDD18 1.8V Digital Supply Voltage 1.67 1.93 V

AVDD18 1.8V Analog Supply Voltage 1.67 1.93 V

IVDD33 3.3V Supply current (IVDD33 + IAVDD33) 12 12 mA

IVDD18 1.8V Supply current (IVDD18 + IAVDD18) 205 219 mA PCB Layout Guidelines Typical Application Schematics In a typical add-on card design, the X-Wall MX is connected to two SATA connectors, a Mini-USB key interface, and LED indicators. For the detailed circuit layout files and Bill of Materials, please visit our website to download the latest revision. For special feature implementation such as built-in API source codes and related features, make a request with Enova Engineering at [email protected].

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Enova Technology Corporation Confidential Copyright © 2010. Enova Technology Corporation. All rights reserved. Page 12 of 28

Title

Size Document Number Rev

Date: Sheet of

X-Wall MX Ref erence Design 0.2

X-Wall MX

A3

1 1Friday , January 25, 2008

D1

LED

D2LED

R8330

R11100K

TxPB

+3.3V

+3.3VJ2SATA

1234567

C180.1uF

J1SATA

1234567

C320.1uF

C150.1uF

FB1Ferrite

FB2Ferrite

C22 0.01uFC23 0.01uF

C24 0.01uF

R5330

C25 0.01uF

Enova Confidential!

+3.3V

C26 0.01uFC27 0.01uF

C28 0.01uFC29 0.01uF

R72.7K_1%

C100.1uF

FB3Ferrite

C110.1uF

FB5Ferrite

U4X-Wall MXTQFP80

TD

I3

TD

O4

VD

D33

XW19

VSS

33XW

20

TC

K5

TM

S6

TR

ST7

VSS

18XW

8

VD

D18

XW11

TlrD

spEr

r12

PO

STO

ff13

SSC

Off

14

DS

CR

Off

15

PSC

RO

ff16

VSS

18XW

10B

yPas

sN9

Syn

c2PH

Y17

SyS

Res

etN

18

VSS33XW40

XTALO 39

XTALI 38

PLLTest 37

VSS33PLL32

VAA33PLL 31

VSS18PLL 30

VDD18PLL 29

VSS18XW33

VDD18XW 36

LbEn25

VSS18XW35

NC24

NC.134

BistErr 23

VSS18XW27

EngErr 22

Cf gHost 21

VDD18XW 28

TxNA61

TxPA62

VDDP63

VSSP64

RxNA65

RxPA66

RxNB67

RxPB68

VDDP69

VSSP70

TxNB71

TxPB72

VSSRESREF73

ResRef74

VSSANA75

VDD18ANA76

VDD33XW79

VSS33XW80

TestC77

TestE78

IDD

QE

n1

Bis

t2

VD

DS

ATA

60

VSS

SAT

A59

SDAH

48

SC

LH47

VSS

ANA

58

VD

D18

ANA

57

VD

DS

ATA

56

VSS

SAT

A55

VSS

SAT

A54

VD

DS

ATA

53

VDD

18X

W49

Tes

tIO50

VSS1

8XW

52

NC

.251

Ref

Clk

Sel_

146

Ref

Clk

Sel_

045

Pm

Mod

e44

Dat

Xfe

r43

PLL

ENa

42

VDD

33X

W41

VSS18XW26

+3.3V

+1.8V

R333

R433

R21.5K

R11.5K

U224LC02

A01

A12

SCL 6A23

GND4

WP 7

SDA5

VCC8

+1.8V

C30

30pF

C31

30pF

C160.1uF

VDD3_3VDD3_3

24C_A0

Y125MHz

24C_A2

C40.1uF

R61MEG

24C_A1

C130.1uF

+1.8V

TxNA

X-Wall MX

24C_SCL

24C_SDA

R124.7k

C340.1uF

+3.3V

C140.1uF

+1.8V

C190.1uF

C200.1uF

+1.8V

TxPA

RxNB

C120.1uF

C90.1uF

KEY STORAGE

BypassN (JP2)CLOSE: BYPASS MODEOPEN: ENCRYPTION MODE

JP2JUMPER

1 2

RxNA

C350.1uF

RxPA

+1.8V +3.3V

C210.1uF

FB4Ferrite

FB6Ferrite

C170.1uF

+3.3V

VDD1_8

VDD3_3

+C710uF

C80.1uF

+C210uF

C10.1uF

+C310uF

C50.1uF

U1

AIC117-33/SOT223

VOUT2

ADJ1

VIN3

U3

AIC1117-18/SOT223

VOUT2

ADJ1VIN

3

+C610uF

+5VJP1POWER CONNECTOR

5V1GND 2GND 312V 4

RxPB

C330.1uF

1. The C22, C23, C24, C25, C26, C27, C28 and C29 are the MLCC type and are in 0402 dimension.

2. FB1, FB2, FB3, FB4, FB5 and FB6 are 30ohm at 100MHz

X-Wall MX Reference Design

To HDD

TxNB

To HOST

D3LED

R9330

Typical Bill of Materials (BOM)

Item Quantity Reference Part

1 1 CON1 Mini-USB 5P/B type

2 26 C1,C2,C3,C5,C6,C7,C8,C12, 0.1uF/0603

C13,C17,C20,C21,C23,C26,

C27,C28,C31,C33, C34,C35,

C44,C49,C50, C55,C60,C62

3 9 C4,C10,C16,C22,C25,C32, 0.01uF/0603

C48,C56,C61

4 11 C9,C11,C18,C19,C24,C29, 10uF/0805

C30,C46,C47,C53,C58

5 2 C15,C14 33PF/0603

6 8 C36,C37,C38,C39,C40,C41, 0.01uF/0402

C42,C43

7 2 C57,C45 68uF/20V/TANT D type

8 2 C59,C54 1uF/0603

9 1 D1 LED_Yellow/0603

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10 1 J1 SATA 22P 180° DIP Female

11 1 J2 SATA 22P 180° DIP male

12 6 LB1,LB2,LB3,LB4,LB5,LB6 100 ohm/100MHz/0805

13 2 R45,R23 4.7k/0603

14 1 R29 330/0603

15 1 R30 1M/0603

16 1 R31 2.7K 1%/0603

17 1 R35 340 1%/0603

18 1 R38 150 1%/0603

19 1 R39 100K/0603

20 1 R41 100 1%/0603

21 1 R44 165 1%/0603

22 2 R47,R46 0/0603

23 2 R53,R52 1.5K/0603

24 1 U1 X-WALL MX/TQFP80

25 1 U2 ATMEL 24C02B 8P/SOIC

26 1 X1 25MHz DIP

27 2 Q1, Q2 LM1117-ADJ/SOT 223

Component Placement

For each power pin, add one bypass capacitor, which should be placed closely to the power pin. The DC blocking capacitors on SATA signal traces (C14, C15, C16, C17, C18, C19, C20 and C21)

should be placed closely to X-Wall MX. R3 should be placed closely to X-Wall MX. The Crystal circuits should be placed closely to X-Wall MX.

PCB Trace Routing The X-Wall MX SATA signals routing can become really tricky thus deserves careful attention. The following bullets serve as a general guideline when the signal routing is attempted. Noted, however, this guideline does not cover the entire horizon of a complete design other than dealing with X-Wall MX specifically.

SATA Signal Layout

To route the ResRef and VSSRESREF signals, DO NOT connect these signals to the ground and no other signals traces are routed near by these traces. Use 20mil trace width to route these traces and keep them as short as possible.

The SATA TX signal pairs and SATA RX signal pairs MUST HAVE matching trace length. The difference of two line traces in either TX signal pairs or RX signal pairs should be restricted to below 150 mils.

No other signals should be routed near by these SATA traces on ANY layers. There should be

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no more than one via on these traces; and there should be no stub on these traces. Recommend to use DIP type SATA connector to avoid using more than one via. Keep these traces as short as possible. A solid ground plane should be placed directly underneath these traces to have better signal quality.

The SATA TX signal pairs and SATA RX signal pairs MUST HAVE 100Ω differential impedance. To achieve aforementioned impedance value, Please refer to the paragraph of “PCB Parameters of Differential Signals.“

Do not route SATA traces underneath the crystal circuits or any other chips that employ high clocking.

PCB Parameters of Differential Signals

(Assume 1oz cooper density) Type Material (dielectric

Constant) PCB thickness Dielectric

thickness Trace width Trace spacing

2-layer5 FR4 (4.2) 1.6 mm 57 mil SATA : 7mil USB : 12mil

SATA : 5mil USB : 5mil

4-layer FR4 (4.2) 1.6 mm 4.3 mil SATA : 5mil USB : 6mil

SATA :10mil USB : 8mil

5 The layout engineer MUST follow this note precisely for a 2-layer PCB architecture is not a standard micro strip transmission line structure. There is a definite requirement to the spacing between the differential trace and the nearby cooper plane of the same layer. For PCB parameters specified above, this defined spacing is 8mil for SATA and is 9mil for USB.

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X-Wall MX Interface for Key Loading There are two methods to deliver Secret Key to X-Wall MX. The first method is to deliver Secret Key through a built-in 2-wire serial interface. Both master and slave modes are supported. The second method is to deliver Secret Key via built-in API through SATA interface. The API protocol is further explained later in this design guide. Selection of various Key Loading methods is automatic, and is controlled by an embedded micro-controller.

The 2-wire serial interface is boot-trapped as a bus master by default. X-Wall MX built-in micro-controller will automatically generate bus master protocol seeking for external EEPROM devices (bus address 1010000b) connected to the serial interface for Secret Key. If the 2-wire bus master is so chosen, then the only thing designers need to do is to provide external EEPROM device with correct Secret Key content. After X-Wall MX has completed loading the Secret Key, it will switch the 2-wire serial interface to slave mode. The designers can then verify X-Wall MX’s status using an external bus master.

If an external serial EEPROM device at bus address 1010000b was not found, X-Wall MX automatically switches its 2-wire serial interface to slave mode, awaiting commands and data from an external bus master. The designers can then use an external bus master to configure X-Wall MX and to deliver the Secret Key. Or designers can configure X-Wall MX and deliver Secret Key through SATA interface using API protocol. The following protocols reflect a correct key reading process while the X-Wall MX is at Master mode utilizing an SEEPROM (24LC02B) produced by either Atmel or Microchip at power on reset. W: 0xa2 -- select device address 0x51h but no response.

W: 0xa0, 0x00, 0x00h -- select device address 0x50h and data address

W: 0xa0, 0x87, 0x87 -- select device address 0x50h and data address

R: 0xa1, 0x00 -- read Cryptographic Operation Register address 0x87h

W: 0xa0, 0x00 -- select device address 0x50h data address 0x00h

R: 0xa1 -- <32 bytes of key are clocked in>; read 256-bit key AES Key Ordering Convention Through out this document, the AES Key ordering will follow the convention stated in FIPS-197. That is, the least significant bit of a key sequence is the first input bit; the least significant byte is the first input byte, and so on. When denoting the key in symbols, the least significant bit is put to the left of the sequence. Therefore a 128-bit key sequence can be denoted as

Key128 = b0, b1, b3, …, b127 ,

Or if it can be grouped in byte array or double word array as

Key128 = a0, a1, a2,…, a15 ,

and

Key128 = w0, w1, w2, w3 ,

Where an = b8n, b8n+1,…, b8n+7 and wn = a4n, a4n+1, a4n+2, a4n+3. For example, if

Key128 = 2b, 7e, 15, 16, 28, ae, d2, a6,ab, f7, 15, 88, 09, cf, 4f, 3c , then

w0 = 2b, 7e, 15, 16

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w1 = 28, ae, d2, a6

w2 = ab, f7, 15, 88

w3 = 09, cf, 4f, 3c

X-Wall MX 2-wire Serial Interface Basic The bus interface has two bus wires. The first one, namely SDAH, is used for transmitting and receiving serial bit data. The second one, namely SCLH, is used for transmitting (master mode) and receiving (slave mode) clock pulses. By combining those two signals the START, repeated START, and STOP conditions are created, which are then used for constructing entire bus protocol. Listed below are signal-timing specification of SDAH and SCLH.

SDAH

t

tf tf

tHIGH

tLOW

tHD:STA tHD:DAT

r tBUF

t tSPSU:DAT tHD:STA

SCLH

ttSU:STA SU:STO S P Sr S

PARAMETER SYMBOL MIN. MAX. UNITSCL clock frequency fSCL 0 400 kHz Hold time (repeated) START condition (S). After this period the first clock pulse is generated.

tHD:STA 0.6 - μs

LOW period of the SCL clock tLOW 1.3 - μs HIGH period of the SCL clock tHIGH 0.6 - μs Set-up time for a repeated START condition (Sr) tSU:STA 0.6 - μs Data hold time tHD:DAT 0 0.9 μs Data set-up time tSU:DAT 100 - ns Rise time for both SDA and SCL signals tr 20+0.1Cb 300 ns Fall time for both SDA and SCL signals tf 20+0.1Cb 300 ns Setup time for STOP condition (P). tSU:STO 0.6 - μs Bus free time between a STOP and a START condition. tBUF 1.3 - μs Pulse width of spikes, which must be suppressed by the input filter.

tSP 0 50 ns

Cb: total capacitance of one bus line if pf. X-Wall MX Configuration Protocol through 2-wire Serial Interface Only slave mode protocol (that is, X-Wall MX 2-wire interface is configured as bus slave) will be described

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here since there is nothing designers need to do in master mode. First of all, we need to learn some of X-Wall MX internal register sets especially the following ones. The hexadecimal numbers preceding register names are addresses to the external 2-wire serial interface bus master. 0x80 Chip Command Register (CCR)

Bit 7 6 5 4 3 2 1 0 Name xwCmd7 xwCmd6 xwCmd5 xwCmd4 xwCmd3 xwCmd2 xwCmd1 xwCmd0Type WO WO WO WO WO WO WO WO Reset 0 0 0 0 0 0 0 0

The Chip Command Register provides a way for users to configure X-Wall MX through API from a Serial ATA host adaptor or through two wires serial interface from an external master. Currently the following commands have been defined and disclosed. Although Chip Command Register is read/write, the read operation is utilized to reset this register to the “nop” command by clearing all bits in CCR.

Name Code Description nop 0000_0000 No operation. X-Wall MX will not response to this command.

softRst 0000_0001 The soft reset command will reset all register settings to their default values. cfgXWall 0000_0100 If executed, X-Wall MX re-configures itself using the latest input settings.

Otherwise, it remains at previous active state. selKeys 0000_1ned Select number of keys (n = 0 for one key, n = 1 for two keys), encryption key (e

= 0 for the 1st key, e = 1 for the 2nd key), and decryption key (d = 0 for the 1st key, d = 1 for the 2nd key).

0x81 Command Parameter-1

Bit 7 6 5 4 3 2 1 0 Name para7 para6 para5 para4 para3 para2 para1 Para0 Type WO WO WO WO WO WO WO WO Reset 0 0 0 0 0 0 0 0

0x82 Command Parameter-2

Bit 7 6 5 4 3 2 1 0 Name para7 para6 para5 para4 para3 para2 para1 para0 Type WO WO WO WO WO WO WO WO Reset 0 0 0 0 0 0 0 0

0x83 Command Parameter-3

Bit 7 6 5 4 3 2 1 0 Name para7 para6 para5 para4 para3 para2 para1 para0 Type WO WO WO WO WO WO WO WO Reset 0 0 0 0 0 0 0 0

0x84 Chip Status Register (CSR)

Bit 7 6 5 4 3 2 1 0 Name intXwRdy sspdMode - - - - xwBusy cfgXwRdyType RO RO - - - - RO RO Reset 0 0 - - - - 0 0

intXwRdy a ‘1’ indicates that X-Wall MX has finished power on initialization and is ready to accept command.

sspdMode a ‘1’ shows that X-Wall MX is currently in suspend mode. When it is in suspend mode, Link layer of both host and device interfaces will remain in the IDLE state until suspend mode is

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unlocked. API will be un-available and the only way to unlock it is through the two wires serial interface.

xwBusy if xwBusy bit is set, the X-Wall MX is not able to accept any new command. cfgXwRdy a ‘1’ means that X-Wall MX configuration has been successfully completed. 0x85 Cryptographic Configuration Register (CCFR)

Bit 7 6 5 4 3 2 1 0 Name AS_1 AS_0 - - - KS_2 KS_1 KS_0 Type RO RO - - - RO RO RO Reset na Na - - - na na na

AS_1, AS_0, KS_2, KS_1, and KS_0 define the cryptographic algorithm been used and the associated key strength of the cryptographic engine according to the following table:

AS_1 AS_0 KS_2 KS_1 KS_0 Algorithm & Strength 1 0 0 1 0 AES CBC 128 1 0 0 1 1 AES CBC 192 1 0 1 0 0 AES CBC 256 0 1 0 1 0 AES ECB 128 0 1 0 1 1 AES ECB 192 0 1 1 0 0 AES ECB 256 0 0 - - - BYPASS

0x86 Key Entry Mode/Status Register

Bit 7 6 5 4 3 2 1 0 Name detRom detKTN - K_LD1 K_LD0 K_GD1 K_GD0 K_EXP Type RO RO - RO RO RO RO RO Reset na na - 0 0 0 0 0

detRom X-Wall MX has detected, through the 2-wire serial interface, the existence of an external

program ROM. detKTN X-Wall MX has detected that an external key token is attached on the 2-wire serial interface. K_LD1 will be ‘1’ if loading KEY #1 has completed. Otherwise, it will have logic value ‘0’. K_LD0 will be ‘1’ if loading KEY #0 has completed. Otherwise, it will have logic value ‘0’. K_GD1 will be ‘1’ if loading KEY #1 has completed and content is good. Otherwise, it will be ‘0’. K_GD0 will be ‘1’ if loading KEY #0 has completed and content is good. Otherwise, it will be ‘0’. K_EXP will be ‘1’ if KEY scheduling has completed. Otherwise, it will have logic value ‘0’. 0x87 Cryptographic Operation Register (COR)

Bit 7 6 5 4 3 2 1 0 Name POSTOff - - - - N_KEY E_KEY D_KEY Type RO - - - - RO RO RO Reset NA - - - - 0 0 0

POSTOff when it is asserted HIGH, will bypass the Power-On-Self-Test (POST) procedure N_KEY indicate the number of Secret Key from which X-Wall MX is currently armed with (0 for one

Key, and 1 for two Keys). Note that, when X-Wall is only armed with one Key, Key #0 is the default location to store Key bytes. If Key #1 is selected under one Key condition, X-Wall MX will enter into the bypass mode.

E_KEY selects the Secret Key used for encryption operation according to the following table:

N_KEY E_KEY Encryption Key Selected 0 0 X-Wall MX is armed with one Secret Key and Key #0 location is

selected

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0 1 X-Wall MX is armed with one Secret Key and Key #1 location is selected (bypass mode)

1 0 X-Wall MX is armed with two Secret Keys and Key #0 is selected 1 1 X-Wall MX is armed with two Secret Keys and Key #1 is selected

D_KEY selects the Secret Key to be used for decryption according to the following table:

N_KEY D_KEY Decryption Key Selected 0 0 X-Wall MX is armed with one Secret Key and Key #0 location is

selected 0 1 X-Wall MX is armed with one Secret Key and Key #1 location is

selected (bypass mode) 1 0 X-Wall MX is armed with two Secret Keys and Key #0 is selected 1 1 X-Wall MX is armed with two Secret Keys and Key #1 is selected

X-Wall MX will take bus address 1010000b (0x50 in hex code) when it is boot trapped as a bus slave. An external 2-wire serial interface bus master should program X-Wall MX using procedurals equivalent to the following.

1. Prepare Secret Key with correct format and sizes; 2. Select number of Secret Keys to be loaded and which Secret Keys shall be used for encryption and

decryption respectively; 3. Write Key bytes. The starting addresses of the first and the second Secret Keys are 0x00 and 0x40,

respectively; (Bytes start from address 0x00 to address 0x7F are temporary storage buffer whose contents will be destroyed after cfgXWall command has been completed.)

4. Configure Secret Keys (conduct Key expansion) after all key bytes have been loaded; 5. Release bus.

X-Wall MX supports multiple key loads6. However, if the Secret Key wasn’t re-configured, X-Wall MX will use the previous Secret Keys (or bypass if there is none).

STEP INSTRUCTIONS COMMENTS 1 key_size <= (CCFR & 0x07) << 3; Calculate Key size 2 write_byte(0x50,0x80,0x08); Write command selKeys3 page_write(0x50,0x00, Write Key bytes key_byte[0],key_byte[1],…,key_byte[key_size-1]); 4 write_byte(0x50,0x80,0x04); Write command cfgXWall5 free_bus(); Stop Serial Clock

Page Write Protocol

6 X-Wall MX is capable of reading a 2nd or more Secret Key sets within the same power on cycle. After the

new Secret Key set is enabled, the previous Secret Key set is discarded. This feature can be best utilized over the drive re-purposing stage as pulling the Secret Key renders the entire disk content illegible.

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S T A R T

STOP

M S B

L S B

W R I T E

R/

W

SDA LINE

WORD ADDRESS

DEVICE ADDRESS

A C K

ACK

ACK

DATAN+1 DATAN+K DATAN

ACK

A C K

Figure 1. A page-write protocol: (page_write(device_address, start_address, data_byte#1, data_byte#2,…,

data_byte#n);)

Byte Write Protocol

S T A R T

S T O P

M S B

LSB

WRITE

WORD ADDRESS

DEVICE ADDRESS

R/

W

SDA LINE

A C K

DATA

A ACK

CK

Figure 2. A byte-write protocol: (write_byte(device_address, word_address, data_byte);)

Byte Read Protocol

S T A R T

STOP

MS B

L S B

R/

W

SDA LINE

WORD ADDRESS

DEVICE ADDRESS

NO

ACK

A C K

DATA

ACK

ACK

START

MSB

LSB

R/

W

DEVICE ADDRESS

W R I T E

READ

Figure 3. A byte-read protocol: (byte_read(device_address, word_address);) X-Wall MX API Configuration Protocol through SATA interface

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X-Wall MX API mode is accomplished by two methods: 1.) act as a Port Multiplier with a single device port to allow registers access; and 2.) use two vendor specific commands.

1. X-Wall MX acts as a Port Multiplier with a single device port (known as ‘pmMode’) – set pin pmMode to either ‘0’ (port 14) or ‘1’ (port 15) and follow exactly the same procedure as described in the “Serial ATA II: Port Multiplier” specification. That is, designers must specify the port field of the ‘Register - Host to Device FIS’ as either port #14 or port #15 for any Read (0xE4) and Write (0xE8) command to be able to access to X-Wall MX General Status and Control Registers (GSCR) under Vendor Unique section. The X-Wall MX will only respond at the port address that is been specified in the pmMode setting. If a real Port Multiplier is to be used along with the X-Wall MX, make sure to set the pmMode=0 (for X-Wall MX to take port #14) as a standard Port Multiplier shall take port address #15. Failure to configure the port address may cause port conflict, leading to incorrect API programming flow.

2. Use two vendor specific commands namely x58 and x59 to allow API access (known as ‘Vendor Specific’) – the vendor specific Read command (0x58) and Write command (0x59) allow access to X-Wall MX’s General Status and Control Register (GSCR) under Vendor Unique section. The implementation follows the same procedure as being described in #1. Irregardless of pmMode setting, the X-Wall MX will always respond to 0x58 and 0x59 commands.

Note that methods described above in #1 and #2 follow the same programming flow7 but with different command opcodes. For better clarity in reading, ‘pmMode’ Read/Write commands (0xE4/0xE8) are specifically colored in bold red while ‘Vendor Specific’ Read/Write commands (0x58/0x59) are specifically colored in bold blue. Designers can choose to implement either ‘pmMode’ or ‘Vendor Specific’ commands but never mix them up.

X-Wall MX API Commands

If a host adaptor wants to read register content from X-Wall MX, it should issue a ‘Register – Host to Device FIS’ with corresponding fields having the following values:

Register 7 6 5 4 3 2 1 0 Features RegNum Features (exp) na Sector Count Reserved (0) Sector Count (exp) na Sector Number Reserved (0) Sector Number (exp) na Cylinder Low Reserved (0) Cylinder Low (exp) na Cylinder High Reserved (0) Cylinder High (exp) na Device/Head na PortNum Command 0x58/0xE4

where RegNum indicates the double word register address to be read, and PortNum has value 0xF. If the command is successfully received and executed, then X-Wall MX will issue a ‘Register – Device to Host FIS’ with corresponding fields having the following values:

Register 7 6 5 4 3 2 1 0 Error 0

7 The programming guide is available upon specific request.

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Sector Count Value[7:0] Sector Count (exp) na Sector Number Value[15:8] Sector Number (exp) na Cylinder Low Value[23:16] Cylinder Low (exp) na Cylinder High Value[31:24] Cylinder High (exp) na Device/Head Reserved (0) Status BSY(0) DRDY(1) DF(0) na DRQ(0) 0 0 ERR(0)

Upon encountering an error, X-Wall MX shall send a ‘Register – Device to Host FIS’ having the following values in corresponding fields: Register 7 6 5 4 3 2 1 0 Error Reserved (0) ABRT(0) REG Port Sector Count Reserved (0) Sector Count (exp) na Sector Number Reserved (0) Sector Number (exp) na Cylinder Low Reserved (0) Cylinder Low (exp) na Cylinder High Reserved (0) Cylinder High (exp) na Device/Head Reserved (0) Status BSY(0) DRDY(1) DF(0) na DRQ(0) 0 0 ERR(1)

If a host adaptor wants to write to X-Wall MX’s internal registers, it must issue a ‘Register – Host to Device FIS’ with corresponding fields having the following values: Register 7 6 5 4 3 2 1 0 Features RegNum Features (exp) na Sector Count Value[7:0] Sector Count (exp) na Sector Number Value[15:8] Sector Number (exp) na Cylinder Low Value[23:16] Cylinder Low (exp) na Cylinder High Value[31:24] Cylinder High (exp) na Device/Head na PortNum Command 0x59/0xE8

where RegNum indicates the double word register address to be written, PortNum has value 0xF, and “Value” carries bytes of the double word. If the command is successfully received and executed, then X-Wall MX will issue a ‘Register – Device to Host FIS’ with corresponding fields having the following values: Register 7 6 5 4 3 2 1 0 Error 0 Sector Count Reserved (0) Sector Count (exp) na Sector Number Reserved (0) Sector Number (exp) na Cylinder Low Reserved (0) Cylinder Low (exp) na

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Cylinder High Reserved (0) Cylinder High (exp) na Device/Head Reserved (0) Status BSY(0) DRDY(1) DF(0) na DRQ(0) 0 0 ERR(0)

Upon encountering an error, X-Wall MX shall send a ‘Register – Device to Host FIS’ having the following values in corresponding fields: Register 7 6 5 4 3 2 1 0 Error Reserved (0) ABRT(0) REG Port Sector Count Reserved (0) Sector Count (exp) na Sector Number Reserved (0) Sector Number (exp) na Cylinder Low Reserved (0) Cylinder Low (exp) na Cylinder High Reserved (0) Cylinder High (exp) na Device/Head Reserved (0) Status BSY(0) DRDY(1) DF(0) na DRQ(0) 0 0 ERR(1)

X-Wall MX API Configuration Protocol

X-Wall MX API uses the same register sets and storage buffer described in the 2-wire Serial Interface section. However, since both ‘pmMode’ and ‘Vendor Specific’ commands read or write four bytes (a double word) at a time, their addresses (RegNum) are different from those had been used in 2-wire Serial Interface Protocol. In general, the API register number can be derived from the two wire serial interface byte address using the equation below:

RegNum = 0xC0 + int(byte_address_of_the_two_wire_serial_interface / 4),

Where int(.) will take the integer part of the division. Therefore, the double word at RegNum = 0xE0 contents parameter-3, parameter-2, parameter-1, CCR , and the double word at RegNum = 0xE1 contents COR, KESR, CCFR, CSR ( the most significant byte first). We refer the double word at RegNum = 0xE0 to the Command dword; the double word at RegNum = 0xE1 to the Status dword.

A Serial ATA host adaptor should program X-Wall MX API for key loading using procedurals equivalent to the following. 1. Read the capability (algorithm and encryption strength, as indicated in CCFR) X-Wall MX supports; 2. Prepare Secret Key with correct format and sizes; 3. Select number of Secret Keys to be loaded and which Secret Keys shall be used for encryption and

decryption; 4. Write key bytes. The starting addresses of the first and the second Secret Keys are 0xC0 and 0xC8,

respectively. Note that dwords starting from address 0xC0 to address 0xDF are temporary storage buffer whose contents will be destroyed after cfgXWall command has been completed.

5. Configure Secret Keys (conduct Key expansion) after all key bytes have been loaded;

X-Wall MX supports multiple key loads which is also applicable with API programming.

STEP INSTRUCTIONS COMMENTS

1 key_size <= (CCFR & 0x07) << 3; Calculate Key size 2 write_xwall(0xE0, 0x08, 0x00, 0x00, 0x00); Write command selKeys3 for ( j = 0; j < key_size/4; j = j + 1 ) Write Key bytes write_xwall( 0xC0 + j , key_byte[4j],

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key_byte[4j+1], key_byte[4j+2], key_byte[4j+3]); 4 write_xwall(0xE0, 0x04, 0x00, 0x00, 0x00); Write command

cfgXWall.8 Note Tasks read_xwall and write_xwall have following syntax:

read_xwall (regNum, data_byte0, data_byte1, data_byte2, data_byte3)

input [4:0] regnum; output [7:0] data_byte0; output [7:0] data_byte1; output [7:0] data_byte2; output [7:0] data_byte3; begin

dev_head = dev_head OR 0x0F ; feature = regNum ;

send read PM command FIS (or x58 & x59 command) to X-Wall MX receive status register FIS from X-Wall MX

data_byte0 = sec_count ; data_byte1 = sec_num ; data_byte2 = cyl_low ; data_byte3 = cyl_high ;

end write_xwall (regNum, data_byte0, data_byte1, data_byte2, data_byte3)

input [4:0] regnum; input [7:0] data_byte0; input [7:0] data_byte1; input [7:0] data_byte2; input [7:0] data_byte3;

begin dev_head = dev_head OR 0x0F ; feature = regNum ; sec_count = data_byte0; sec_num = data_byte1; cyl_low = data_byte2; cyl_high = data_byte3;

send write PM command FIS (or x58 & x59 ATA command) to X-Wall MX receive status register FIS from X-Wall MX

end

8 Note that you must write this command to physically enable the X-Wall MX crypto mode operation. If the

feature of repeated toggling between Crypto mode and Bypass mode is desirable, the switching back to Crypto mode from the previous Bypass mode will always require a WRITE command to the cfgXWall command to actually enable the Crypto function.

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Power-On Sequence After power on (SysReset negated LOW and released HIGH), the Serial ATA PHY module requires about 6μs for internal PLLs to become fully functional. The PHY then will exchange OOBs on both channels. After the OOB sequence has completed with no error, the X-Wall MX is then ready for Serial ATA transactions. After power on, X-Wall MX will perform Power-On-Self-Test and if an external Secret Key is available on the 2-wire Serial Interface, then X-Wall MX will load the key via the interface. After the Secret Key has been loaded and expanded, the X-Wall MX is ready for cryptographic operations. This sequence is completed far before the Serial ATA interface has finished exchanging OOBs. If the Secret Key were to be loaded via an external 2-wire Serial bus master or a Serial ATA host adaptor using built-in API, it is advised that the designers must make sure the key load sequence completes before any Serial ATA data transfer occurs for corrupted data might occur if SATA data transfer occurs before key load sequence is able to complete.

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X-Wall MX Configuration Management Hardware Packaging

TQFP (Thin Quad Flat Package) provides low profile with 1.0mm body thickness, suitable for space

concerned applications. Package size 10×10mm and lead-count 80 are offered for portable, lightweight

and low profile applications. All Enova X-Wall MX chips comply with RoHS and Lead-free

specification.

Features 1. 10mm by 10mm body size with 80 lead-counts;

2. Copper lead-frame;

3. Low profile 1.0mm body thickness;

4. JEDEC MS-026/ACE standard outlines;

Firmware Release

Hard coded version 1.1.0 released for ROM integration within a silicon.

Hardware Version Control, Outline, and Dimension

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Dimension [mm] Symbol

min NOR MAX

e 0.4 BSC

b 0.13 0.18 0.23

D1 10.00BSC

D , E 12.00BSC

A 1.20

A1 0.05 0.15

A2 0.95 1.00 1.05

L 1.00(REF)

L1 0.45 0.60 0.75

X-Wall MX top marking:

Enova – Trademark

X-Wall MX-mmm, trademark and product SKU

where mmm represents 3 to 4 digits as follows:

- 256, AES ECB 256-bit

- 256C, AES CBC 256-bit

- 192, AES ECB 192-bit

- 192C, AES CBC 192-bit

- 128, AES ECB 128-bit

- 128C, AES CBC 128-bit

XXXXXXXXXXXX–S

| 8 Lot No. | 4 date code | 2 version control|

8 digits for wafer lot number;

4 digits yyww (yy represents year and ww

represents week) for manufacturing date code;

2 digits –S for version control where S

represents serial mixed signal design;

US Patent No.: granted US patents listing.