xcell 18 newsletter (q3 95) · 5 from the fawcett compliance no simple task secondly, and more...
TRANSCRIPT
Issue 18Third Quarter 1995
GENERALFawcett: PCI Compliance ......................... 2Guest Editorial: Chuck Fox on
Developing New PLD Solutions ........... 3New Xilinx Internet Web Site .................. 6Financial Results ...................................... 6Customer Success Story ........................... 7New Product Literature ............................ 8Upcoming Events ..................................... 8Xilinx Ireland Comes On-Line ................. 9Training Class Supports XACTstep ........... 9Component Availability Chart ......... 10-11Alliance Program Chart .................... 12-13Alliance Contact Chart .......................... 13Development Systems Chart ................. 14Programming Support Charts:
XC7200, XC7300, XC1700 ............ 15-17
PRODUCTSNew XC4000E Family ...................... 18-19XC8100 Enters Production ............... 20-21XC6200 Architecture Announced .... 22-23
DEVELOPMENT SYSTEMSImproved EPLD Synthesis Support ... 25-26XACTstep, Advanced System ................ 26
HINTS & ISSUESHDL Synthesis Design Guide .......... 27-29Overshoot and Undershoot ................... 30Low-Pass Filtering of Noisy Inputs ........ 30XC4000E:
Examining RAM Capabilities ...... 31-33Building FIFO Memories ............. 34-35
Mixing 3.3 Volt and 5 Volt Devices ..... 35“Hold” is a Four-Letter Word ................ 36Acquiring Application Notes
and Design Files ................................ 37Questions & Answers ....................... 38-39Technical Support Facilities .................. 393Q95 Fax Response Form ..................... 40
The ProgrammableLogic CompanySM
Inside This Issue:
T H E Q U A R T E R L Y J O U R N A L F O R X I L I N X P R O G R A M M A B L E L O G I C U S E R S
R
XCELLGENERAL FEATURES
Ireland Facility On-LineXilinx’s new 100,000 square foot facility inDublin, Ireland is now processing allEuropean orders...
See Page 9
PRODUCT INFORMATION
XC8100 FamilyThe first Xilinx one-time-programmable FPGA family, basedon MicroVia technology, entersproduction.
See Page 20
XC6200 FamilyThe new XC6200 SRAM-based FPGAarchitecture is the first FPGAspecifically designed to implementreconfigurable coprocessors inembedded system applications.
See Page 22
XC4000E FamilyWith a myriad of new features, the
XC4000E FPGA family increasesperformance over the existingXC4000 family by up to 50%...
See Page 18
Introducing three newFPGA Families!Introducing three newFPGA Families!
FROM THE FAWCETT
PCI Compliant ≠ PCI SuitableBy BRADLY FAWCETT Editor
R
XCELLPlease direct all inquiries,comments and submissions to:
Editor: Bradly Fawcett
Xilinx, Inc.2100 Logic DriveSan Jose, CA 95124Phone: 408-879-5097FAX: 408-879-4676E-Mail: [email protected]
©1995 Xilinx Inc.All rights reserved.
XCELL is published quarterly forcustomers of Xilinx, Inc. Xilinx, theXilinx logo and XACT are registeredtrademarks; all XC-designatedproducts, UIM, HardWire and XACT-Performance are trademarks; and“The Programmable Logic Company”is a service mark of Xilinx, Inc. Allother trademarks are the property oftheir respective owners.
2
Continued on page 5
The rapid adoption and proliferationof the PCI (Peripheral Component Inter-connect) bus has been one of the com-puter market’s major success stories of thepast year.
Originally defined by Intel, PCI hasbecome an industrywidestandard controlled by aconsortium — the PCISpecial Interest Group,or PCI SIG. The high-performance PCI buscan handle the through-put demands of data-intensive applicationssuch as multimedia andhigh-speed networking.
Full compliance to the PCI SIG specifi-cation is a must for systems and boardsthat will be sold in the general market-place where interoperability among mul-tiple vendors is required.
To achieve high throughput and ensureinteroperability between a wide variety ofboards and host systems, the PCI specifi-cation includes a strict definition of itselectrical interface. IC components thatcan meet the performance, loading anddrive requirements of this electrical inter-face are said to be “PCI-compliant.” Bysubmitting the appropriate paperwork,component suppliers that are members ofthe PCI SIG can have their compliantdevices added to an “Integrators List” thatis available to other PCI SIG members.
Market Pressures andMarketing Tactics
PCI-related designs are a large potentialmarket for high-density CPLDs and FPGAs.The flexibility of a programmable ap-proach is attractive in a PC card marketcharacterized by changing market needsand short product life cycles. These de-
vices are, in fact, finding their way intomany prototype and production PCI de-signs. Thus, programmable logic vendorsare working hard to establish themselvesas suppliers to this market. One tactic is tosubmit as many devices as possible forinclusion on the PCI SIG’s Integrators List,and then, based on their inclusion on thelist, advertise these devices as being “PCIApproved” (or a similar designation).
Designers of PCI boards and systemsare advised to be leery of these claims.First, the PCI SIG does not guarantee thecompliance of any device or offer anyform of approval; submissions to the PCISIG are strictly on the “honor system” andare not verified independently. (In fact,the component section of the IntegratorsList specifically states that functional test-ing is not required to be listed. The PCISIG disclaims responsibility for any errorsin the listings.) The Integrators List is
considered confidential to PCI SIG mem-bers and is for their convenience only.Again, inclusion on the Integrators Listdoes not constitute any endorsement orapproval by the PCI SIG.
...being ‘PCI-
compliant’ does not
necessarily mean these
devices are suitable for
use in a PCI
application.
R
GUEST EDITORIAL
3
Developing New PLD Solutionsby CHUCK FOX Vice President, Product Marketing
By the end of 1995, Xilinx will have introduced more new programmable logicdevice family solutions in the last 18 months than in our prior ten-year history. Whyso many? Why now? As with most semiconductor products, the answer to bothquestions stems from the convergence of technology and market needs.
Technology and MarketsFirst, there is the “push factor” of rapid advancements in IC fabrication
technology. It took the industry nearly a decade to migrate from 2.0 micronto 1.0 micron technology. Yet, the move from 1.0 to 0.5 micron has taken lessthan five years (and 0.35 micron technology is only a year or so away). Theseshrinking IC geometries, along with larger wafer sizes, additional layers ofmetal interconnect, new software technologies and new packaging technolo-gies have allowed dramatic increases in device density and performance.Equally dramatic price reductions have followed.
Advances in IC processing technology have accelerated the development ofnew programming structures. Xilinx is the only PLD company that is providingcost-effective and reliable SRAM, antifuse, EPROM and FLASH processes nowavailable in volume production.
These technology shifts, of course, influence PLD architectural development.What conventional wisdom assumed was impossible yesterday may be feasibletoday. For example, the shift from two-layer to three-layer metal processes alters the“logic vs. routing” trade-offs in FPGA design (as evident in the new XC8100, XC5200,and XC6200 FPGA family architectures). Thus, advances in process technology leadto new programmable logic architectures.
Just as influential is the “pull factor” of increasinglycompetitive end-use markets. Today’s electronic systemmarket is characterized by global competition andchanging industry standards, resulting in higher-performance products with shorter life cycles.
Design methodologies are changing; higher levels ofdesign abstraction and automated tools are required tomeet the twin challenges of increased complexity anddecreased time-to-market.
Inspiration + Ability = New ArchitecturesThus, our new product offerings reflect the goal of
every electronics design: leverage advancing technology to best match users’ needs.In some cases, this takes the form of evolutionary improvements to current products,such as enhancing the popular XC4000 FPGA architecture to create the XC4000Efamily. In other cases, it involves new product development to take full advantage ofnew technologies or to address new markets; for example, the XC5200 architectureleverages 3-layer metal technology to lower FPGA costs, thereby expanding FPGA
Continued on the next page
Xilinx is the only PLD company
that is providing cost-effective and
reliable SRAM, antifuse, EPROM and
FLASH processes now available in
volume production.
4
GUEST EDITORIAL
usage in high-volume applications.Why so many PLD architectures? CPLDs
and FPGAs are being used in an amaz-ingly wide variety of logic applications,ranging from simple interface logic toreconfigurable computing arrays. WhilePLD use in communications, industrial andperipheral control applications continuesto expand, increasing PLD capabilities anddecreasing prices are opening up newmarkets in PC and consumer applications.Different applications have differentneeds. Different users have different pref-erences. No single technology or architec-ture can meet all those needs and desires.
The SRAM-based XC2000, XC3000A/XC3100A, XC4000E and XC5200 architec-tures remain the best FPGA architecturesfor “glue logic” applications. Each has aslightly different mix of attributes. TheXC3100A family offers the best raw speed,
the XC4000E provides the largest densitiesand feature set (including on-chipmemory), and the XC5200 delivers thelowest cost per gate. We will continue toenhance these architectures and improvethese product families. The new XC6200FPGA architecture, with its built-in proces-sor interface, targets a different type ofapplication — reconfigurable coprocessing(although it will undoubtedly find its wayinto other applications as well). TheXC8100 FPGAs are ideal for those applica-
Continued from the previous page
tions requiring “instant-on” operation, theincreased security of a one-time-program-mable solution, or a more “ASIC-like,”synthesis-friendly design flow.
Some applications fit better with aCPLD-type architecture. The XC7300 fam-ily, featuring industry-leading perfor-mance, continues to expand with therecent additions of the XC73144 andXC7336Q. A revolutionary, new, in-systemprogrammable architecture, based on flashmemory technology, will be introducedlater this year.
Industry LeadershipWhy now? It has always been our
corporate goal to be the leading supplierof programmable logic. Simply put, wewant to fulfill all of our users’ high-densityprogrammable logic needs. As Xilinx andthe programmable logic market grew inthe late 1980s and early 1990s, we becamethe leading PLD supplier and could affordto make substantial investments in re-search and development. The new prod-ucts appearing now are the result of yearsof development. As the largest and mostsuccessful supplier of programmable logic,we have the engineering resources toexplore different approaches and supportmultiple development efforts. With therecent acquisition of FPGA-software-sup-plier NeoCAD, we are setting the standardfor leading-edge development software tosupport multiple component families.
High-density PLDs are rapidly becom-ing a critical, strategic technology forleading electronic systems companies. Abroad product line supported by a power-ful, unified suite of development toolsgives the user the best of both worlds —the choice of the most-appropriate PLDarchitecture, and no need to purchase andlearn a new set of design tools. We thinkthis is crucial to being not only your pro-grammable logic supplier, but also yourprogrammable logic partner.
The high-performanceXC7336Q is just one of thenew products introduced byXilinx in the first half of 1995.
A broad product line supported by apowerful, unified suite of development toolsgives the user the best of both worlds — the
choice of the most-appropriate PLDarchitecture, and no need to purchase and
learn a new set of design tools.
5
FROM THE FAWCETT
Compliance No Simple TaskSecondly, and more importantly, being
“PCI-compliant” does not necessarily meanthese devices are suitable for use in a PCIapplication. Electrical compliance onlyguarantees that the device meets the bareminimum electrical characteristics. It doesnot guarantee that the device has the logiccapacity, functionality and overall speedto effectively implement a PCI interfacedesign—the device may or may not besuitable for a real-world design.
For example, the PCI specificationallows a 10 pF maximum load on a bussignal (except the clock signal, which isallowed a 12 pF maximum load), as wellas a maximum trace length of 1.5 inchesfrom the card edge connector to limittrace capacitance. Taken together, thesetwo factors imply that each bus signalattaches to only one IC pin per board(that is, a signal coming from the connec-tor can have only one destination).
Practically speaking, all the interfacelogic would need to be implemented in asingle device in a fairly small package(such as a quad flat pack) so that all thepins can be close to the connector. Asimple PCI interface typically requiresabout 100 I/O, about 4,000 usable gates,and well over 100 registers. The need fora single-chip solution eliminates a lot ofthe smaller PALs and CPLDs that havefound their way on to the Integrators Listand are advertised as “PCI-compliant” bytheir manufacturers.
The internal architectures of somedevices do not easily meet the needs ofPCI interface design. For example, manyPCI bus signals are bidirectional and mustbe driven by three-state buffers. SomeFPGA and CPLD architectures limit thenumber of different output enables thatmay be present on the device. Targetinterfaces require a minimum of fouroutput enables; initiators require at least
six. This is a bare minimum. It does notinclude the output enables needed forinterrupts, controlling byte transactions, orconnecting to the back-end logic. Real-world designs require several more outputenables. Thus, devices with limited outputenable capability are not practical for PCIdesigns.
Beyond the BasicsThere are, of course, many other issues.
Can the device deliver the needed perfor-mance to operate at any frequency from 0to 33 MHz? Do the development toolsmake it easy to control circuit speed alongthe critical paths? The PCI bus has to at-tach to something — what are therequirements of the back-endinterface? Compliant electricalcharacteristics are just the first stepin selecting a programmable logicdevice for PCI interface design.Labeling a product as “PCI-compli-ant” does not ensure suitability fora particular design.
Xilinx does offer several de-vices that are both electricallycompliant and architecturally suit-able for PCI interface implementations.These include the XC3100A and newXC4000E FPGA families, as well as thehigher-density members of the XC7300EPLD family. Xilinx components havealready been used in a number of success-ful PCI designs. In fact, the PCI SIG chosea Xilinx XC3100A FPGA for a board in-cluded in their BIOS compliance test kit.
For more information about pro-grammable logic products for PCIdesigns, including application notesand reference designs, please contactus via E-mail at [email protected] or callyour local Xilinx representative.
Copies of the PCI specification can beobtained from the PCI Special InterestGroup, P.O. Box 14070, Portland, OR97214 (tel: 800-433-5177).
Continued from page 2
P.S. Our thanks to thethousands of engineers whojoined us for the Program-mable Logic Breakthrough’95 seminars this spring.We know your time is valu-able and we appreciateyour participation
Xilinx does offer
several devices that are
both electrically
compliant and
architecturally suitable.
6
Record Revenue and Another Kachina AwardXilinx revenues rose to a record $125.8 million in
the first quarter of fiscal 1996 (ending July 1, 1995).This represents a 15 percent increase from the imme-diately preceding quarter, and a 67 percent increasefrom the same quarter last year.
Once again, revenue growth was driven by in-creasing demand for high-speed XC3100 and XC4000family products. International sales constituted 36percent of total revenue; sales from Japan showed thelargest increase, benefiting from the strengthened yen.
Xilinx stock split 3-for-1 on August 11, 1995 forshareholders of record as of July 28. The stock split isindicative of the confidence of the Xilinx Board ofDirectors in the company’s ability to maintain contin-ued growth. The stock split will increase the totalnumber of outstanding shares to 70 million. It is thefirst stock split since the company went public in1990. Xilinx stock is traded on the NASDAQ exchangeunder stock symbol XLNX.
Five Consecutive KachinasIn May, market research firm In-Stat Inc. named
Xilinx as the Best Financially Managed IC Company fora record fifth consecutive year. The coveted KachinaAward was presented to Xilinx at In-Stat’s annual Semi-conductor Forum. (The Kachina Award is a statue carvedby the Hopi Indians of Arizona. According to Hopi leg-end, the Kachina is a warrior who faces great difficultiesand shows great strength.)
Separate awards are presented for IC companies thatdo and do not own their own fabrication facilities. Thecompanies are ranked based on criteria such as operatingincome, net income, return on investment, inventoryturnover and sales per employee. Xilinx beat out allother “fabless” companies, including Adaptec, Altera andLattice Semiconductor. Xilinx has won this award eachyear since going public in June, 1990. No other semicon-ductor company, with or without a foundry, has receivedthis award for more than two consecutive years.
FINANCIAL RESULTS
Xilinx SpinsInternet Web Site
Many new items have been added re-cently to the Xilinx webLINX site on theWorld Wide Web, including technical applica-tion notes, FPGA and EPLD data sheets, pressreleases, training schedules, financial newsand stock quotations, and University Programnews. An interactive, on-line technical sup-port database and FTP site for file transfersare available as well.
Most Xilinx Web documents are “pub-lished” using Adobe AcrobatTM. Acrobat dis-plays documents on the screen just as theywould appear from a color printer. The Acro-bat Reader is available free on the Internet.,enabling anyone with Internet Web access toview and print high-quality Xilinx literaturedirectly from the Web.
Look for future additions such as the Xil-inx Annual Report, employment opportunitylistings as well as current and previous issuesof XCELL. Other possibilities include a searchengine to permit quicker access to all thedocuments on a given topic and real-timeorder status. Your feedback is encouraged; ifthere is a document or feature you’d like tosee on the Xilinx Web, please send an E-mailmessage to [email protected].
The Xilinx home page on the WorldWide Web can be accessed at http://www.xil inx.com.
7
CUSTOMER SUCCESS STORY
Videoconferencingwith XC5000 FPGAs
VTEL Inc. designs and manufactures high-quality, multimedia videoconferencingsystems. It is the leading provider of videoconferencing equipment for the remote educa-tion and medical industries.
The VTEL systems are based on architectures that employ multiple heterogeneousprocessor subsystems, interconnected and controlled using custom data paths and controllogic. Xilinx FPGAs provide a cost-effective, adaptable solution for implementing thiscustom hardware, and have been used in several generations of VTEL systems.
VTEL’s latest videoconferencing system uses XC5000family FPGAs, making it one of the earliest adoptersof this new FPGA family. The new design uses anXC5210 and an XC5206 device (in 240-pinand 160-pin PQFP packages, respectively)to implement specialized video andcommunication data pipelines andcontrol logic. The FPGAs contain customvideo processing control logic with multistagedata pipelines to perform high-quality video formatconversions and the adaptive overlay of video streams.Video is processed at near broadcast quality in both RGBand YUV formats.
The flexibility of the SRAM-based FPGAs facilitated the imple-mentation of custom video merge processing in order to produce supe-rior integration of multiple streams of live and control video. The FPGAs alsowere used to consolidate a large number of bus control, timing and communica-tions signal routing, and test functions. If these functions had been implemented withPALs and/or discrete logic devices, the system would have required two to three times asmany circuit boards, with the resulting increases in cost and power consumption.
Since the XC5000 development software was not yet available at the beginning of thedesign cycle, VTEL engineers took advantage of the Xilinx Unified Library and the foot-print-compatibility of the XC4000 and XC5000 families. Initially, the logic targeted for theXC5210 and XC5206 devices was designed for an XC4010 and XC4006 FPGA, respec-tively. Logic capture, simulation and printed-circuit board layout were completed in thismanner. The designs were captured and verified on a Sun workstation using theViewlogic PowerView schematic editor and ViewSim simulator. Altogether, about sixman-months of effort were required to enter, simulate and implement the designs.
Once the XC5000 library was available, the conversion to the XC5000 family partswent smoothly. After some floorplanning of the data path logic, the automatic tools of theXACT_ system produced an implementation that exceeded the performance requirementsof VTEL’s application.
The compatibility between the XC4000 and XC5000 families was exploited again dur-ing prototyping and initial system test. The XC5210 FPGA was available when the first
Continued on the next page, see VIDEOCONFERENCING
8
New Product LiteratureLearn about the newest Xilinx products and services through our extensive library of
product literature. The most recent pieces are listed below. To order or to obtain a com-plete list of all available literature, please contact your local Xilinx sales representative.
TITLE DESCRIPTION PART NUMBER
FPGAsXC4000E Overview Features & benefits #0010257-01XC6200 Overview Features & benefits #0010258-01XC8100 Overview Features & benefits #0010254-01XC8100 Advanced Information Technical Data #0010193-03
EPLDsXC7300 Family Brochure Product Overview #0010253-01
prototype systems were built, but the XC5206 was not,so it was replaced by the pin-compatible XC4006.
The anticipated improved routing capabilities of theXC5000 architecture increased the effective usablecapacity enough to allow the inclusion of additionaltest functions during the latter stages of product devel-opment. This additional functionality significantly en-hanced board-level product testing capabilities.
VideoconferencingContinued from page 7
8th Annual IEEE ASIC Confer-ence (ASIC ’95)Sept. 18-22Austin, Texas
European Design AutomationConference (EURO-DAC ’95)Sept. 18-22Brighton, United Kingdom
DSP ’95Oct. 18-20Paris, France
WESCONNov. 7-9San Francisco,California
InternationalIntegrated Cir-cuits ConferenceNov. 8-10Shanghai, China
Photonics EastOct. 22-26Philadelphia, Pennsylvania
1995 International Conferenceon Signal Processing Applica-tions and Technology and DSPWorld Exhibition (ICSPAT)Oct. 23-27Boston, Massachusetts
UPCOMING EVENTS
Look for Xilinx technical papers and/or product exhibits at these upcoming industryforums. For further information about any of these conferences, please contact KathleenPizzo (Tel: 408-879-5377 FAX: 408-879-4676).
See page 37 for alisting of new
application notes.
VTEL design engineer Richard Glass noted, “Xilinxhas provided VTEL with excellent FPGA supportthrough several generations of system designs. VTELespecially values the ease of development and flexibil-ity of the Xilinx FPGA products, which facilitates rapiddevelopment and allows incremental design improve-ment over product life cycles. By using FPGA technol-ogy, we have been able to adapt the subsystem de-signs to meet changing market requirements bothduring product development and in the field.”
9
Xilinx Ireland Comes On-LineIn keeping with the corporate goal of
increasing international sales to half oftotal revenue, Xilinx has established amajor new facility at the Citywest BusinessCampus in Dublin, Ireland. Constructionof the 100,000 square foot manufacturingfacility is scheduled to be completed latethis year.
The new facility will be used to pro-duce and distribute Xilinx products forEurope and other international markets. Itis the company’s first wholly-ownedmanufacturing facility outside of theUnited States. Besides providing additionalcapacity for a growing business, XilinxIreland provides closer access to Europeanusers, ultimately resulting in better serviceand faster response times.
The new Irish facility will replicate theactivities of the company headquarters inSan Jose, with the exception of field salesand marketing. Customer service is a keypart of the Irish operation; all Europeanorders are being received and processedin Dublin now; all international orders willbe processed there by the end of the year.
After the manufacturing and customerservice resources are in place, emphasiswill be placed on system software testingand quality analysis. Eventually, IC and
software design groups will be estab-lished. This venture is expected to createmore than 300 jobs.
Operations commenced in a temporarybuilding at the Citywest site in April,starting with the processing of all Euro-pean distributors’ orders. The first productto ship from Ireland was delivered to anItalian distributor in mid-April. XilinxIreland is now processing all Europeanand some Asian orders; production capac-ity will continue to rise throughout theyear. The company is undertaking anintensive program to achieve ISO 9002quality standards certification for theDublin facility in 1996.
Training Class Update Supports XACTstep, version 6The Xilinx training courses are being kept up-to-
date with information about the latest products. Thestandard three-day training course will be updated forXACTstepTM version 6 as well as the new XC5200 andXC4000E families as soon as the software begins pro-duction shipment. Our policy is to always base thecourse on the latest software versions available to ourentire user base.
If you have a design starting now or have an imme-diate need for training, you should attend the currentclass. The instructor will be able to point out some of
the key changes coming with the next release. Also, aone-day “update” class will be made available at thesame time as the XACTstep version production shipment.This class will be targeted at those who have used theprevious version, or who have already attended training.The XC8100 family and its supporting software are alsoslated for production release this autumn. A class will beavailable at that time. For more information, contactyour local sales office, or Xilinx Training at (408)879-5090, (800) 231-3386x1, or e-mail [email protected].
When construction is finally com-plete late this year, Xilinx Irelandwill contain 100,000 square feet ofmanufacturing and office space.
10P
INS
TYPE
CO
DE
XC
2064
XC
2018
XC
2064
LX
C20
18L
XC
3020
XC
3030
XC
3042
XC
3064
XC
3090
XC
3020
AX
C30
30A
XC
3042
AX
C30
64A
XC
3090
AX
C30
20L
XC
3030
LX
C30
42L
XC
3064
LX
C30
90L
XC
3120
AX
C31
30A
XC
3142
AX
C31
64A
XC
3190
AX
C31
95A
COMPONENT AVAILABILITY CHART
PLASTIC LCC PC44PLASTIC QFP PQ44CERAMIC LCC WC44PLASTIC DIP PD48PLASTIC VQFP VQ64
PLASTIC LCC PC68CERAMIC LCC WC68CERAMIC PGA PG68PLASTIC LCC PC84CERAMIC LCC WC84CERAMIC PGA PG84
CERAMIC QFP CQ100PLASTIC PQFP PQ100PLASTIC TQFP TQ100PLASTIC VQFP VQ100TOP BRZ. CQFP CB100CERAMIC PGA PG120
PLASTIC PGA PP132CERAMIC PGA PG132PLASTIC TQFP TQ144CERAMIC PGA PG144CERAMIC PGA PG156PLASTIC PQFP PQ160
CERAMIC QFP CQ164TOP BRZ. CQFP CB164PLASTIC PGA PP175CERAMIC PGA PG175PLASTIC TQFP TQ176CERAMIC PGA PG184
CERAMIC PGA PG191TOP BRZ. CQFP CB196PLASTIC PQFP PQ208METAL MQFP MQ208CERAMIC PGA PG223PLASTIC BGA BG225
WINDOWED BGA WB225TOP BRZ. CQFP CB228PLASTIC PQFP PQ240METAL MQFP MQ240CERAMIC PGA PG299HI-PERF. QFP HQ304
44
48
64
68
84
100
120
132
144
156160
164
175
176
184
191
196
208
223
225
228
240
299
304
= Product currentlyshipping or planned
= New since last issueof XCELL
11
XC
4003
XC
4005
XC
4006
XC
4008
XC
4010
XC
4010
DX
C40
13X
C40
13D
XC
4025
XC
4002
AX
C40
03A
XC
4004
AX
C40
05A
XC
4003
HX
C40
05H
XC
4003
EX
C40
05E
XC
4006
EX
C40
08E
XC
4010
EX
C40
13E
XC
4020
EX
C40
25E
XC
5202
XC
5204
XC
5206
XC
5210
XC
5215
XC
7236
AX
C72
72A
XC
7318
XC
7336
XC
7336
QX
C73
54X
C73
72X
C73
108
XC
7314
4X
C81
01X
C81
03X
C81
06
AUGUST 1995
12
2K/3K/4K XC5200 EPLD UNIFIED LIB.COMPANY PRODUCT NAME VERSION FUNCTION DESIGN KIT SUPPORT SUPPORT SUPPORT SUPPORT
Acugen ATGEN 2.60 Automatic Test Generation AALCA interface Aug Sharpeye 2.60 Testability Analysis AALCA interface Aug
ALDEC/Susie-CAD Active-Xilinx 2.0 Schematic Entry/Simulation Included Active-Xlx-State 2.0 Schematic State Editor/ Included
HDL Editor SimulationActive-Xlx-Syn 2.0 Schematic State Editor/ Included
HDL Editor Synthesis Sim.Aptix System Explorer 2.1 System Emulation Axess 2.1
ASIC Explorer 2.3 ASIC Emulation Axess 2.3 4K
Cadence (Valid) Concept 2.0-P7 Schematic Entry Xilinx Front End Q4 Rapidsim 4.2 Simulation Xilinx Front End Q4 Composer 4.3.3 Schematic Entry Xilinx Front End Q4 Verilog 2.2.1 Simulation Xilinx Front End Q4 FPGA Designer 3.3 Synthesis FPGA Synthesis Q4
Capilano DesignWorks 3.1 Schematic Entry/Simulation XD-1
Compass Asic Navigator Schematic Entry Xilinx Design Kit QSim Simulation X-Syn Synthesis
Data I/O ABEL 6.1 Synthesis XEPLD Fitter Synario 2.1 Schematic Entry, Synthe- SYN-LCA Sep
sis and Simulation SYN-XEPLDEscalade Design Book Design Entry
Exemplar Logic Galileo 3.04 Synthesis Included
Flynn Systems FS-ATG 2.6 Automatic Test Generation FS-High Density
IBM-EDA Boole-Dozer Synthesis
IK Technology G-DRAW 5.0 Schematic Entry GDL2XNF G-LOG 4.03 Simulation XNF2GDL
Ikos Voyager 2.10 Simulation Xilinx Tool Kit
Incases Theda 2.0 Schematic Entry Xilinx Kit
Intergraph ACE Plus 12.2 Schematic Entry Xilinx FPGA Design Kit 3K,4K AdvanSIM-1076 12.0 Simulation Xilinx FPGA Design Kit 3K,4K VeriBest Sim 14.0 Simulation Xilinx FPGA Design Kit 3K,4K Veribest DMM 14.0 Design Flow Manager Xilinx FPGA Design Kit 3K,4K VeriBest Syn 14.0 Synthesis Xilinx FPGA Design Kit 3K,4K Synovation 12.2 Synthesis SynLib 3K,4K PLDSyn 12.0 Design entry, synthesis sim. Included
ISDATA LOG/iC2 4.2 Synthesis, simulation Xilinx Mapper LOG/iC Classic 4.2 Synthesis LCA-PP
IST ASYL+ 3.21 Synthesis XNF interface
ITS XNF2LAS 1a Lasar model gen. XNF2LAS
Logic Modeling Smart Model Simulation Models In Smart Model Library (Synopsys Division) LM1200 Hardware Modeler Xilinx Logic Module
Logical Devices CUPL 4.5 Synthesis Xilinx Fitter
Mentor Graphics QuickSim II A.x_F Simulation Call Xilinx Design Architect A.x_F Schematic Entry Call Xilinx Autologic A.x_F Synthesis Xilinx Synthesis Library
MINC PLDesigner-XL 3.3 Synthesis Xilinx Design Module
Minelec Ulticap 1.32 Schematic Entry Xilinx Interface 2K,3KOrCAD SDT 386+ 1.2 Schematic Entry Call Xilinx XACT6
Capture 6.0 Schematic Entry Call Xilinx XACT6 XACT6 XACT6 XACT6VST 386+ 1.2 Simulation Call Xilinx Simulate 6.0 Simulation Call XilinxPLD 386+ 2.0 Synthesis Call OrCAD
Protel Advanced Schematic 2.2 Schematic Entry Xilinx interface
Quad Design Motive 4.0 Timing Analysis XNF2MTV
Simucad Silos III 95.100 Simulation Included
Sophia Systems Vanguard 5.31 Schematic Entry Xilinx I/F Kit
Synopsys FPGA Compiler 3.3 Synthesis Call Xilinx 3K,4K Design Compiler 3.3 Synthesis Call Xilinx VSS 3.3 Simulation Call Xilinx
ALLIANCE PROGRAM - COMPANIES & PRODUCTS - SEPTEMBER 1995
Continued
13
2K/3K/4K XC5200 EPLD UNIFIED LIB.COMPANY PRODUCT NAME VERSION FUNCTION DESIGN KIT SUPPORT SUPPORT SUPPORT SUPPORT
ALLIANCE PROGRAM - COMPANIES & PRODUCTS - SEPTEMBER 1995 (con’t)
Synplicity Synplify 2.5 Synthesis Included 3K,4K Synplify-Lite 2.5 Synthesis Xilinx Mapper 3K,4K
Teradyne Lasar 6 Simulation Xilinx I/F Kit
Tokyo Electron ViewCAD 5.0502a FLDL to XNF translator XNFGEN
Topdown Design V-BAK 1.1 XNF to VHDL translator XNF interface
transEDA TransPRO 1.2 Synthesis Xilinx Library
VEDA Vulcan 4.5 Simulation Xilinx Tool Kit
Viewlogic PROCapture 6.1 Schematic Entry Call Xilinx XACT6 PROSim 6.1 Simulation Call Xilinx XACT6 PROSynthesis 5.02 Synthesis Call Xilinx XACT6
Viewpoint VitalBridge 1.0 Vital VHDL VHDL I/F kit VeriLink 1.0 Verilog lib. back-annotation Verilog I/F kit
Visual Software Solutions StateCAD 2.4 State diagram Xilinx fitter
Zycad Paradigm XP Gate-level simulation Paradigm RP Rapid prototyping
ALLIANCE PROGRAM - PLATFORMS & CONTACTSPLATFORM
COMPANY CONTACT NAME PC SUN RS6000 HP7 PHONE NUMBER
Acugen Peter de Bruyn Kops 603-881-8821Aldec/Susie-CAD David Rinehart 702-293-2271Aptix Corporation Wolfgang Hoeflich 408-428-6200Cadence Itzhak Shapira Jr. 408-428-5739Capilano Computing Chris Dewhurst 604-522-6200Compass Design Shahid Khan 408-433-4880Data I/O Dave Kohlmeier 206-867-6802Escalade Jerry Rau 408-481-1336Exemplar Logic Stan Ng 510-337-3700Flynn Systems Mike Jingozian 603-891-1111IBM-EDA John Orfitelli 914-433-9073IK Technology Hiroyuki Kataoka +81-3-3464-5551Ikos Brad Roberts 408-366-8509Incases Richard Collins 214-373-7344Intergraph Electronics Greg Akimoff 415-691-6541ISDATA Ralph Remme +49-721-751087IST Gabriele Saucier +33-76-70-51-00ITS Frank Meunier 508-897-0028Logic Modeling Marnie McCollow 503-531-2412Logical Devices David Mot 303-279-6868Mentor Graphics Sam Picken 503-685-1298MINC Lynne Dolan 719-590-1155Minelec (Belgium) +32-02-4603175OrCAD Troy Scott 503-671-9500Protel Technology Matthew Schwaiger 408-243-8143Quad Design Tech. Vern Potter 805-988-8250Simucad Richard Jones 510-487-9700Sophia Systems Bob Armstrong 408-943-9300Synopsys Lynn Fiance 415-694-4102Synplicity Alisa Yaffa 415-961-4962Teradyne Mike Jew 617-422-3753Tokyo Electron Shige Ohtani +81-3-5561-7212TopDown Art Pisani 603-888-8811transEDA James Douglas +44-1703-255118VEDA George Sher 408-496-4516ViewLogic Preet Virk 508-480-0881Viewpoint International Ramesh Bhimarao 408-954-7370Visual Software Solutions Ricky Escoto 305-346-8890Zycad David Allenbaugh 510-623-4451
14
XILINX RELEASED SOFTWARE STATUS - AUGUST 1995PREVIOUS CURRENT VERSION BY PLATFORM
PRODUCT PRODUCT PRODUCT XILINX PART VER. PC1 SN2 AP1 HP7 LASTCATEGORY DESCRIPTION FUNCTION NUMBER REL. 6.2 4.1.X 10.4 9.01 UPDATE
XILINX INDIVIDUAL PRODUCTSCORE EPLD XC7K SUPPORT CORE IMPLEMENTATION DS-550-XXX 5.02 5.11 5.10 5.10 01/95FLOORPLANNER4 HI-DENSITY DES. KIT CORE IMPLEMENTATION ES-HD4K-SN2 N/A 5.10 N/AMENTOR2 A.1-F I/F AND LIBRARIES DS-344-XXX 5.02 5.11 5.10 5.11 05/95ORCAD2 I/F AND LIBRARIES DS-35-XXX 5.00 5.10 01/95SYNOPSYS2 I/F AND LIBRARIES DS-401-XXX 3.20 3.30 3.30 06/95VIEWLOGIC2 PROCAPTURE I/F AND LIBRARIES DS-390-XXX 5.02 5.11 05/95VIEWLOGIC2 PROSIM I/F AND LIBRARIES DS-290-XXX 5.02 5.11 05/95VIEWLOGIC2 I/F AND LIBRARIES DS-391-XXX 5.10 5.11 5.11 5.11 01/95XABEL2 ENTRY, SIM, LIB, OPT. DS-371-XXX 5.00 5.10 5.10 01/95X-BLOX1 MODULE GENERATION & OPT. DS-380-XXX 5.00 5.10 5.10 5.10 01/95VERILOG4 2K, 3K, 4K, 7K LIB. MODELS & XNF TRANS. ES-VERILOG-XXX 1.00 1.00 N/A
XILINX PACKAGESCADENCE STANDARD DS-CDN-STD-XXX 5.11 5.11 05/95MENTOR 8 STANDARD DS-MN8-STD-XXX 5.02 5.11 1.10 5.11 05/95MENTOR ADVANCED5 DS-MN8-ADV-XXX N/A 7.00 7.00 N/AORCAD BASE DS-OR-BAS-PC1 5.02 5.10 01/95ORCAD STANDARD DS-OR-STD-PC1 5.02 5.10 01/95SYNOPSYS STANDARD DS-SY-STD-XXX 5.11 5.12 5.12 06/95SYNOPSYS ADVANCED5 DS-SY-ADV-XXX N/A 7.00 7.00 N/AVIEWLOGIC BASE DS-VL-BAS-PC1 5.02 5.11 05/95VIEWLOGIC STANDARD DS-VL-STD-XXX 5.02 5.11 5.11 5.11 05/95VIEWLOGIC ADVANCED5 DS-VL-ADV-XXX N/A 7.00 7.00 7.00 N/AVIEWLOGIC/S BASE DS-VLS-BAS-PC1 5.02 5.11 05/95VIEWLOGIC/S STANDARD DS-VLS-STD-PC1 5.02 5.11 05/95VIEWLOGIC/S EXTENDED3 DS-VLS-EXT-PC1 5.02 5.11 05/95VIEWLOGIC/S ADVANCED5 DS-VLS-ADV-PC1 N/A 7.00 N/AXC5000 PRE-RLS.4 STANDARD CORE + VL LIBRARIES PR-VL-STD-XXX-5K 1.00 2.00 2.00 2.00 4/95XC5000 PRE-RLS.4 STANDARD CORE + MN8 LIBRARIES PR-MN8-STD-XXX N/A 2.00 2.00 N/AXC8000 EXTENDED 8K CORE + SYNTHESIS LIBS. DS-8000-EXT-XXX 1.00 1.00 N/A3RD PARTY STANDARD FPGA/EPLD CORE DS-3PA-STD-XXX N/A 5.10 5.10 5.10 N/A3RD PARTY ALLIANCE ADVANCED5 DS-3PA-ADV-XXX N/A 7.00 7.00 7.00 N/A
XILINX HARDWARE
DEVICE PGMR. PROM/EPLD/XC8100 PGMR. HW-130 1.0 3Q95 3Q95 N/A
THIRD PARTY PRODUCTION SOFTWARE VERSIONSCADENCE COMPOSER SCHEMATIC ENTRY N/A 4.3 4.3.3 4.3.3 N/ACADENCE VERILOG SIMULATION N/A 2.1 2.1.2 2.1.2 N/ACADENCE (VALID) CONCEPT SCHEMATIC ENTRY N/A 1.7 1.7-P4 1.7-P4 N/ACADENCE (VALID) RAPIDSIM SIMULATION N/A 4.10 4.2 4.2 N/AMENTOR DESIGN ARCHITECT SCHEMATIC ENTRY N/A 8.2_5 A.1-F A.1-F A.1-F N/AMENTOR QUICKSIM II SIMULATION N/A 8.2_5 A.1-F A.1-F A.1-F N/AORCAD SDT 386+ SCHEMATIC ENTRY N/A 1.10 1.20 N/AORCAD VST 386+ SIMULATION N/A 1.10 1.20 N/ASYNOPSYS FPGA/DESIGN COMP. SYNTHESIS N/A 3.2b 3.3a 3.3a 3.3a N/AVIEWLOGIC PROCAPTURE SCHEMATIC ENTRY N/A 6.1 5.3 5.3 N/AVIEWLOGIC PROSIM SIMULATION N/A 6.1 5.3 5.3 N/ADATA I/O ABEL COMPILER ENTRY AND SIMULATION N/A 6.1 6.0 N/ADATA I/O SYNARIO ENTRY AND SIMULATION N/A 2.1 N/A
NOTE: 1FPGA only. 2FPGA and EPLD. 3Includes ViewSynthesis v2.3.1.4Engineering software by request only. 5Integrates NeoCAD Foundry tools.
15
PROGRAMMER SUPPORT FOR XILINX XC1700 SERIAL PROMS — AUGUST 19951736A/ 1736D/ 1716L/
MANUFACTURER MODEL 1765 17128 1765D 1765L 17128D 17256D DIP8 PC20 SO8ADVANTECH PC-UPROG V2.1 V2.0 V2.0 V2.1 V2.1 X
LABTOOL-48 V1.0 V1.0 V1.0 V1.0 V1.0 X PLCC2020-01ADVIN PILOT-U24 10.53 10.76C 10.71 10.77 10.78B 10.78B X PX-20 SO-8
PILOT-U28 10.53 10.76C 10.71 10.77 10.78B 10.78B X PX-20 SO-8PILOT-U32 10.53 10.76C 10.71 10.77 10.78B 10.78B X PX-20 SO-8PILOT-U40 10.53 10.76C 10.71 10.77 10.78B 10.78B X PX-20 SO-8PILOT-U84 10.53 10.76C 10.71 10.77 10.78B 10.78B X PX-20 SO-8PILOT-142 10.73 10.76C 10.73 10.77 10.78B 10.78B AM-1736 PX-20 SO-8PILOT-143 10.73 10.76C 10.73 10.77 10.78B 10.78B AM-1736 PX-20 SO-8PILOT-144 10.73 10.76C 10.73 10.77 10.78B 10.78B AM-1736 PX-20 SO-8PILOT-145 10.73 10.76C 10.73 10.77 10.78B 10.78B AM-1736 PX-20 SO-8
AVAL PECKER-50 C C XPKW5100 C C X
B&C MICROSYSTEMS INC. Proteus-UP40 V3.4e V3.4e V3.5f V3.7f V3.7l V3.7l X AMUPLC84BP MICROSYSTEMS CP-1128 C V2.17* V2.21c* V2.34* V3.06 V3.06 FH28A FH28A + 3rd Party FH28A + 3rd Party
EP-1140 C V2.17 V2.21c V2.34 V3.06 V3.06 FH40A FH40A + 3rd Party FH40A + 3rd PartyBP-1200 C V2.17 V2.21c V2.34 V3.06 V3.06 SM48D SM20P or SM84UP 3rd Party
BYTEK 135H-FT/U V42 V51 V51 V51 TC-824DMTK-1000 V42 V51 V51 V51 TC-824DMTK-2000 V42 V51 V51 V51 TC-824DMTK-4000 V42 V51 V51 V51 TC-824D
DATA I/O UniSite/Site 40/48 V4.0 V4.1 V4.1 V4.6 V4.8 V4.8 X USBASE-PLCC USBASE-SOICUniSite/ChipSite V4.0 V4.1 V4.1 V4.6 V4.8 V4.8 X USBASE-PLCC USBASE-SOICUniSite/PinSite V4.0 V4.1 V4.1 V4.6 V4.8 V4.8 X USBASE-PLCC USBASE-SOIC2900 V2.1 V2.2 V2.2 V3.4 V3.6 V3.6 X 2900-PLCC 2900-SOIC3900 V1.5 V1.6 V1.6 V2.4 V2.6 V2.6 0101 3900-PLCC 3900-SOICAutoSite V1.5 V1.6 V1.6 V2.4 V2.6 V2.6 DIP-300-1 PLCC-20-2UniPak 2B V24 351B120ChipLab V1.1 V1.0 V1.0 V1.1 X 080801S300
DEUS EX MACHINA XPGM V1.00 V1.00 V1.00 V1.10 V1.10 Adapter 0 Upgrade to Adapter 16Adapter 0ELECTRONIC ENGIN- ALLMAX/ALLMAX+ V1.3 V1.5 V1.5 V1.5 V2.3 V2.3 XEERING TOOLS PROMAX V2.34 V2.34 V2.34 V2.34 V2.34 V2.34 X Module #4ELAN DIGITAL SYSTEMS 3000-145 C C A116
5000-145 C C A1166000 APS K2.01 K2.02 K2.01 K2.10 K2.14 K2.14 X PDi84UPLC PDi16USOI
HI-LO SYSTEMS All-03A V3.30 V3.30 V3.30 V3.30 V3.50 V3.50 X CNV-PLCC-XC1736 CVN-SOP-NDIP16RESEARCH All-07 V3.30 V3.30 V3.30 V3.30 V3.47 V3.47 PAC-DIP40 PAC-PLCC44ICE TECHNOLOGY LTD Micromaster 1000/1000E V1.1 V3.00 V3.00 V3.07 V3.00 V3.00 X AD-1736/65-PLCC
Speedmaster 1000/1000E V1.1 V3.00 V3.00 V3.07 V3.00 V3.00 X AD-1736/65-PLCCMicromaster LV V3.00 V3.00 V3.00 V3.00 V3.00 XLV40 Portable P 3Q95 P 3Q95 P 3Q95 P 3Q95 P 3Q95 XSpeedmaster LV V3.00 V3.00 V3.00 V3.00 V3.00 X
LINK COMPUTER GPHX CLK-3100 V5.08 V5.08 V5.08 X17XXB PLCC-17XX SOIC-16LOGICAL DEVICES ALLPRO-40 V2.2 X OPTPLC-208 OPTSOI-080
ALLPRO-88 V2.2 V2.3 V2.3 V2.5 V2.5 X OPTSOI-080ALLPRO-88XR V1.1 V2.3 V1.3 V2.3 V2.3 X OPTSOI-080CHIPMASTER 3000 V2.0 V2.1 V2.0 V2.3 X OPTPLC-208 OPTSOI-080CHIPMASTER 5000 V1.15 X OPTPLC-208 OPTSOI-080XPRO-1 V1.01 V1.01 V1.01 V1.01 MODXLN-173 MODXLN-173 MODXLN-173
MQP ELECTRONICS MODEL 200 C 6.45 6.45 6.45 6.46 6.46 AD13A-16SYSTEM 2600 P 3Q95 P 3Q95 P 3Q95 P 3Q95 P 3Q95 MP6PINMASTER 48 P 3Q95 P 3Q95 P 3Q95 P 3Q95 P 3Q95 X
MICRO PROSS ROM 5000 B C V1.70 V1.70 V1.80 V1.80 V1.80 Mu 40ROM 3000 U C V3.60 V3.60 V3.70 V3.70 V3.70ROM 9000 V1.5 V1.5 V1.5
NEEDHAM’S ELECTRONICS EMP20 V1.5 V1.5 V2.37 V2.37 V2.37 V2.37 04BRED SQUARE IQ-180 C V9.2 V8.2 V9.2 V9.2 V9.2
IQ-280 C V9.2 V8.2 V9.2 V9.2 V9.2Uniwriter 40 C V9.2 V8.2 V9.2 V9.2 V9.2Chipmaster 5000 C V9.2 V8.2 V9.2 V9.2 V9.2
RETNEL SYSTEMS ZAP-A-PAL C V3.8J Module #36SMS Expert B/93 A/94 A/94 A1/94 Cx/94 Cx/94 TOP40DIP TOP1PLC or
Optima B/93 A/94 A/94 A1/94 Cx/94 Cx/94 “ TOP3PLC/TOP3PLCMultisyte A/94 Cx/94 Cx/94 “ “Plus48 B/93 A/94 A/94 A1/94Sprint Plus B/93 A/94
STAG Eclipse 4.4 V2.2 V4.3 V4.10.31 V4.10.31 EPU48D EPU84PQuasar 10.76C 10.76C V10.76C V10.76C V10.78B V10.78B X AMPLCC20
SUNRISE T-10 UDP V3.31 V3.31 V3.31 V3.31 V3.31 V3.31 X X XT-10 ULC V3.31 V3.31 V3.31 V3.31 V3.31 V3.31 X X X
SUNSHINE POWER-100 V8.18 V8.18 V8.18 V8.18 V8.18 V8.18 XEXPRO-60/80 V8.18 V8.18 V8.18 V8.18 V8.18 V8.18 X
SYSTEM GENERAL TURPRO-1 V2.21F V2.21F V2.21F V2.21F V2.21F V2.21F DIP-Adapter P20-AdapterTurpro-1 F\X V2.21F V2.21F V2.21F V2.21F V2.21F V2.21F DIP-Adapter P20-AdapterAPRO C V2.14 V2.01 V2.12 S 2Q95 S 2Q95 X X
TRIBAL MICROSYSTEMS TUP-300 C V3.31 V3.31 V3.37C V3.47 V3.47 X CNV-PLCC-XC1736TUP-400 C V3.31 V3.31 V3.37C V3.50 V3.50 X “FLEX-700 C V3.31 V3.31 V3.37C V3.47 V3.47 X “
XELTEK SuperPRO 1.5B 1.7C 1.7D 1.8 2.2A 2.2A X* 20-PL/8-D-ZL-XC1736 16SO15/D6-ZLSuperPRO II 1.5B 1.7C 1.7D 1.8 2.2A 2.2A X* 20-PL/8-D-ZL-XC1736 16SO15/D6-ZL
XILINX HW-112 C V3.11 V3.31 V3.31 V5.0.0 V5.0.0 X HW-112-PC20 HW-112-SO8HW-120 V5.00 V5.00 V5.00 V5.00 P 6/95 P 6/95 HW-120-PRM HW-120-PRM HW-120-PRMHW-130 V1.00 V1.00 V1.00 V1.00 V1.00 HW-137-DIP8 S 5/95 S 5/95
C = Currently Supported, P = Planned, S = Scheduled Release Date, X=Package Supported; WHITE = change since last issue
16
C = C
urre
ntly
Supp
orte
d (no
vers
ion nu
mbe
r)P
= Plan
ned R
eleas
eS
= Ship
ping D
ate
WHI
TE=c
hang
e sinc
e las
t issu
e
VEND
ORM
ODEL
7236
7236
A72
7272
72A
PC44
PC68
PC84
PG84
Comm
ents
Adva
ntec
hPC
-UPR
OGV2
.4V2
.4V2
.4V2
.4X
SDP-
7272
-68
SDP-
7272
-84
LabT
ool-4
8V1
.0V1
.0V1
.0V1
.0SD
P-UN
IV-4
4SD
P-72
72-6
8SD
P-72
72-8
4Ad
vin S
yste
ms
Pilo
t-U40
10.7
7E10
.77E
10.7
7E10
.77E
USA-
84US
A-84
USA-
84Pi
lot-U
8410
.77E
10.7
7E10
.77E
10.7
7EUS
A-84
USA-
84US
A-84
AM-X
C84G
B&C
Micr
osys
tem
s, In
c.Pr
oteu
sV3
.6j
V3.6
jV3
.7h
V3.7
hAM
UPLC
84AM
UPLC
84AM
UPLC
84BP
Micr
osys
tem
sBP
-120
0v2
.32
v2.3
2v2
.34
v2.3
4SM
44P
SM68
P or S
M84
UPSM
84P o
r SM
84UP
SM84
UGA
DATA
I/O
UniS
itev4
.3v4
.6*
v4.5
v4.5
**US
BASE
-PLC
CUS
BASE
-PLC
CUS
BASE
-PLC
C*7
236A
=PPI
-0243
2900
V3.4
*V3
.4*
PPI-0
243
PPI-0
246
PPI-0
208
**727
2A=P
PI-02
46 (P
C68)
3900
v2.1
V2.4
*v2
.3v2
.3**
3900
-PLC
C39
00-P
LCC
3900
-PLC
C**7
272A
=PPI-
0247
(PC8
4)Au
toSi
teV2
.4*
V2.4
*v2
.3v2
.3**
PLCC
-44-
1PL
CC-6
8-1
PLCC
-84-
1De
us E
x Mac
hina
XPGM
V1.0
0V1
.00
V1.0
0V1
.00
Adap
ter 1
Adap
ter 2
Adap
ter 3
Elan
Dig
ital S
yste
ms
6000
APS
K2.0
4K2
.04
K2.0
6K2
.06
PDi8
4UPL
CPD
i84U
PLC
PDi8
4UPL
CPD
i84P
Gx
Elec
troni
c Eng
inee
ring
ALLM
AX/A
LLM
AX+
V2.1
V2.1
V2.1
V2.1
Mod
ule
05+P
A44-
84U
PA68
-48A
PA84
-48A
Tools
PROM
AXV2
.34
V2.3
4P
6/95
P 6/
95M
odul
e 19
+ H
44Hi
-Lo S
yste
ms R
esea
rch
All-0
3AV3
.01
V3.0
1V3
.00
V3.0
0AD
P-XC
7236
-PL4
4AD
P-XC
7272
-PL6
8AD
P-XC
7272
QPI-8
4Al
l-07
V3.0
1V3
.01
V3.0
0V3
.00
PAC-
PLCC
44PA
C-PL
CC68
ICE
Tech
nolo
gy Lt
d.M
icrom
aste
r 100
0/E
VX1.
00VX
1.00
VX1.
00VX
1.00
AD-X
C723
6-PLC
C-44
AD-X
C727
2-PLC
C-68
AD-X
C727
2-PLC
C-84
Spee
dmas
ter 1
000/
EVX
1.00
VX1.
00VX
1.00
VX1.
00AD
-XC7
236-P
LCC-
44AD
-XC7
272-P
LCC-
68AD
-XC7
272-P
LCC-
84M
icrom
aste
r LV
VX1.
00VX
1.00
VX1.
00VX
1.00
AD-X
C723
6-PLC
C-44
AD-X
C727
2-PLC
C-68
AD-X
C727
2-PLC
C-84
Spee
dmas
ter L
VVX
1.00
VX1.
00VX
1.00
VX1.
00AD
-XC7
236-P
LCC-
44AD
-XC7
272-P
LCC-
68AD
-XC7
272-P
LCC-
84Lo
gica
l Dev
ices
ALLP
RO-8
82.
2V2
.42.
2V2
.4C
CC
ALLP
RO-8
8XR
1.35
V2.4
1.35
V2.4
CC
CXP
RO-1
1.01
1.01
1.01
1.01
MO
DXP1
-44L
MO
DXP1
-68L
MO
DXP1
-84L
MO
DXP1
-84G
Micr
opro
ssRO
M 9
000
P 3Q
95P
3Q95
P 3Q
95P
3Q95
MQ
P El
ectro
nics
SYST
EM 20
00P
3Q95
P 3Q
95P
3Q95
P 3Q
95M
P1M
P1M
P1PI
NMAS
TER
48P
3Q95
P 3Q
95P
3Q95
P 3Q
95Un
ivers
al P
rogr
amm
erNe
edha
m’s
Elec
troni
csEM
P20
V2.3
7V2
.37
V2.3
7V2
.37
19A+
H44
20A+
U68C
B20
A+U8
4CB
Stag
Eclip
seV5
.7.3
V5.7
.3V5
.7.3
V5.7
.3EP
U84P
+EP
U84P
+EP
U84P
+SM
SEx
pert
A1/9
4A1
/94
A1/9
4A1
/94
TOP1
TOP1
TOP1
Opt
ima
A1/9
4A1
/94
A1/9
4A1
/94
TOP1
TOP1
TOP1
Mul
tisyt
eA1
/94
A1/9
4A1
/94
A1/9
4TO
P1TO
P1TO
P1Su
nrise
Ele
ctro
nics
T-10
UDP
V3.3
1V3
.31
V3.3
1V3
.31
XX
XX
All a
dapte
rs ar
e cus
tomT-
10 U
LCV3
.31
V3.3
1V3
.31
V3.3
1X
XX
XAl
l ada
pters
are c
ustom
Suns
hine
Ele
ctro
nics
POW
ER-1
00V8
.16
V8.1
6CN
V -UNI
VERS
AL-P
LCC4
4EX
PRO-
60/8
0V8
.16
V8.1
6CN
V-UNI
VERS
AL-P
LCC4
4Sy
stem
Gen
eral
TURP
RO-1
v2.1
2v2
.12
v2.1
2v2
.12
P44
P68
P84
TURP
RO-1
F\X
v2.1
2v2
.12
v2.1
2v2
.12
P44
P68
P84
Trib
al M
icros
yste
ms
TUP-
300
v3.0
v3.0
v3.0
v3.0
TUP-
7236
TUP-
7272
TUP-
400
v3.0
v3.0
v3.0
v3.0
TUP-
7236
TUP-
7272
FLEX
-700
v3.0
v3.0
v3.0
v3.0
TUP-
7236
PAC-
PLCC
68PA
C-PL
CC 44
Xelte
kSU
PERP
RO1.
7C2.
22.
12.
1XX
C723
6-44P
L/40D
XXC7
272-6
8PL/6
8DXX
C727
2-84P
L/84D
SUPE
RPRO
II1.
7C2.
22.
12.
1XX
C723
6-44P
L/40D
XXC7
272-6
8PL/6
8DXX
C727
2-84P
L/84D
Xilin
xHW
-120
V3.1
4V3
.14
V3.1
4V3
.14
HW-1
20-P
C44
HW-1
20-P
C68
HW-1
20-P
C84
HW-1
20-P
G84
*HW-
12x E
PLD
adap
ters
HW-1
30V1
.00
V1.0
0S
5/95
S 6/
95HW
-132
-PC4
4*S
5/95
*S
5/95
*ca
n be u
sed o
n HW-
130
PR
OG
RA
MM
ER S
UP
PO
RT F
OR X
ILIN
X X
C72
00 E
PLD
S —
AU
GU
ST 1
995
VEND
ORMO
DEL
7318
7336
7354
7372
7310
873
144
PC44
PC68
PC84
PQ44
PQ10
0PG
144
PQ16
0PG
184
BG22
5
ADVA
NTEC
HPC
-UPR
OGV2
.4V2
.4V2
.4P
3Q95
XSD
P-73
54-6
8La
bToo
l-48
V1.0
V1.0
V1.0
V1.0
4V1
.04
P 3Q
95SD
P-UN
IV-4
4SD
P-73
54-6
8X
ADVI
N SY
STEM
SPI
LOT-
U40
10.7
8N10
.78N
10.7
8N10
.78N
10.7
9P
3Q95
USA-
84US
A-84
USA-
84AM
-XC1
00Q
AM-X
C144
GAM
-XC1
60Q
PILO
T-U8
410
.78B
10.7
8B10
.78B
10.7
8B10
.79
P 3Q
95US
A-84
USA-
84US
A-84
AM-X
C100
QAM
-XC1
44G
AM-X
C160
Q
B&C M
ICRO
SYST
EMS
Prote
us3.
7k3.
7k3.
7kP
3Q95
3.7k
P 3Q
95C
CC
BP M
ICRO
SYST
EMS
BP-1
200
V3.0
1V3
.01
V3.0
1V3
.07
V3.0
6ASM
44P
FHSM
84PX
DATA
I/O
2900
V3.5
V3.5
V3.5
2900
-PLC
C05
2939
00V2
.5V2
.5V2
.5V2
.6V2
.6P
3Q95
3900
-PLC
C39
00-P
LCC
3900
-PLC
C05
2905
5705
58PP
I-110
1Un
iSite
V4.7
V4.7
V4.7
V4.8
V4.8
P 3Q
95US
BASE
-PLC
CUS
BASE
-PLC
CUS
BASE
-PLC
C05
2905
5705
58PP
I-110
1Au
toSi
teV2
.5V2
.5V2
.5V2
.6V2
.6P
3Q95
PLCC
-44-
1PL
CC-6
8-1
PLCC
-84-
105
29PP
I-110
1
DEUS
EX
MAC
HINA
XPGM
V1.0
0V1
.00
V1.0
0V1
.10
V1.1
0P
3Q95
Adap
ter 5
Adap
ter 6
Adap
ter 7
Adap
ter 9
(13
for 7
372)
ELEC
TRON
IC EN
GIN-
ALLM
AX/A
LLM
AX+
V2.1
V2.1
V2.1
V2.1
P 3Q
95Mo
dule
04+P
A44-4
8UPA
68-4
8B (7
354)
PA84
-48B
EERI
NG TO
OLS
PROM
AXV2
.34
V2.3
4V2
.34
V2.5
7P
3Q95
Modu
le #1
9 +
H44
PA68
-48C
(737
2)
ELAN
6000
APS
k2.1
3k2
.13
k2.1
3k2
.13
k2.1
3P
3Q95
PDi84
UPLC
PDi84
UPLC
PDi84
UPLC
PDi04
4QFx
PDi10
0QFx
PDi16
0QFx
PDi22
5BGx
HI-L
O SY
STEM
SAl
l-03A
V3.0
4V3
.04
V3.0
4V3
.05
V3.0
1P
3Q95
ADP-X
C7336
-PL44
ADP-X
C7372
-PL68
ADP-X
C7310
8-PL84
RESE
ARCH
All-0
7V3
.02
V3.0
2V3
.02
V3.0
1V3
.00
P 3Q
95PA
C-PL
CC44
PAC-
PLCC
68
ICE
TECH
NOLO
GY LT
DM
icrom
aste
r 100
0/E
VX1.
00VX
1.00
VX1.
00VX
1.00
VX1.
00P
3Q95
AD-73
XX-P
LCC-
44AD
-7354
-PLC
C-68
AD-73
XX-PL
CC-44
AD-7
372-
PLCC
-68
Spee
dmas
ter 10
00/E
VX1.
00VX
1.00
VX1.
00VX
1.00
VX1.
00P
3Q95
AD-73
XX-P
LCC-
44AD
-7354
-PLC
C-68
AD-73
XX-PL
CC-44
AD-7
372-
PLCC
-68
Micr
omas
ter L
VVX
1.00
VX1.
00VX
1.00
VX1.
00VX
1.00
P 3Q
95AD
-73XX
-PLC
C-44
AD-7
354-
PLCC
-68
AD-73
XX-PL
CC-44
AD-7
372-
PLCC
-68
Spee
dmas
ter LV
VX1.
00VX
1.00
VX1.
00VX
1.00
VX1.
00P
3Q95
AD-73
XX-P
LCC-
44AD
-735
4-PL
CC-6
8AD
-73XX
-PLCC
-44AD
-737
2-PL
CC-6
8
LOGI
CAL D
EVIC
ESAL
LPRO
-88
V2.5
V2.5
V2.5
V2.5
V2.5
P 3Q
95C
CC
ALLP
RO-8
8XR
V2.5
V2.5
V2.5
V2.5
V2.5
P 3Q
95C
CC
XPRO
-11.
011.
011.
011.
011.
01P
3Q95
MOD
XP1-
5444
LM
ODXP
1-54
68L
MOD
XP1-
108L
MODX
P1-16
0QMO
DXP1
-184G
MODX
P1-10
8B
MICR
OPRO
SSRO
M 90
00P
3Q95
P 3Q
95P
3Q95
P 3Q
95P
3Q95
P 3Q
95
MQP E
LECT
RONI
CSSY
STEM
2000
P 3Q
95P
3Q95
P 3Q
95P
3Q95
P 3Q
95P
3Q95
MP1
MP1
MP1
PINM
ASTE
R 48
P 3Q
95P
3Q95
P 3Q
95P
3Q95
P 3Q
95P
3Q95
NEED
HAM'
S ELE
CTRO
NICS
EMP2
0V2
.37
V2.3
7V2
.37
V2.3
7V2
.37
P 3Q
9519
B +
H44
20A
+ U6
8CA
20A
+ U8
4CA
SMS
EXPE
RTC/
94C/
94C/
94P
2Q95
P 2Q
95P
3Q95
TOP1
TOP1
TOP1
OPTI
MA
C/94
C/94
C/94
P 2Q
95P
2Q95
P 3Q
95TO
P1TO
P1TO
P1
STAG
ECLIP
SEV4
.10.
31V4
.10.
31V4
.10.
31V4
.10.
31V4
.10.
31P
3Q95
SUNR
ISET-
10 U
DPV3
.31
V3.3
1V3
.31
V3.3
1V3
.31
P 3Q
95X
XX
T-10
ULC
V3.3
1V3
.31
V3.3
1V3
.31
V3.3
1P
3Q95
XX
X
SUNS
HINE
POW
ER-1
00P
5/95
P 5/
95P
5/95
P 5/
95P
3Q95
CNV-U
NIVER
SAL-P
LCC4
4EX
PRO-
60/80
P 5/
95P
5/95
P 5/
95P
5/95
P 3Q
95CN
V-UNIV
ERSA
L-PLC
C44
SYST
EM G
ENER
ALTU
RPRO
-1V2
.2V2
.2V2
.2V2
.2V2
.2P
3Q95
C
TRIB
AL M
ICRO
SYST
EMS
ALL-
07V3
.02
V3.0
2V3
.02
V3.0
1V3
.00
P 3Q
95PA
C-PL
CC44
PAC-
PLCC
68
XELT
EKSU
PERP
RO2.
12.
2A2.
12.
2BP
3Q95
P 3Q
95XX
C7354
-44PL
/40D
XXC7
354-68
PL/40
DSU
PERP
RO II
2.1
2.2A
2.1
2.2B
P 3Q
95P
3Q95
XXC7
354-44
PL/40
DXX
C7354
-68PL
/40D
XILI
NXHW
-120
V5.0
0V5
.00
V5.0
0V5
.00
V5.0
0P
6/95
HW-1
26-P
C44
HW-1
26-P
C68
HW-12
6-PC8
4HW
-126-P
Q44
HW-12
6-PQ1
00HW
-126-P
G144
HW-12
6-PQ1
60HW
-126-P
G184
HW-12
6-BG2
25HW
-130
V1.0
0V1
.00
V1.0
0S
5/95
S 5/
95S
5/95
HW-1
33-P
C44
C = C
urre
ntly
Supp
orte
d (no
vers
ion nu
mbe
r)P
= Plan
ned R
eleas
eW
HITE
=cha
nge s
ince l
ast is
sue
PR
OG
RA
MM
ER S
UP
PO
RT F
OR X
ILIN
X X
C73
00 E
PLD
S —
AU
GU
ST 1
995
17
18
PRODUCT INFORMATION — COMPONENTS
R
The High-PerformanceXC4000E FamilyNew Family Achieves 50 Percent PerformanceIncrease Over the Popular XC4000 Family
Xilinx has begun shipping the newXC4000E family, the successor to thepopular XC4000 FPGA family. TheXC4000E FPGA family increases perfor-mance over the existing XC4000 family by
up to 50 percent, and is ideal for high-density, high-performance applicationssuch as microprocessor bus interfacing,digital signal processing, image process-ing, and high-speed telecommunications.
This dramatic performance improve-ment results from an improved design, anew 0.5µ triple-layer-metal process tech-nology, and the new Select-RAMTM on-chipmemory feature. The XC4000E familyfeatures eight devices ranging from 3,000to 25,000 gates, including the XC4020Edevice, the first 20,000 gate device offeredby Xilinx. (Higher-density devices will beannounced later this year.) Since the
XC4000E family is based on the XC4000family architecture, XC4000E devices arebackward compatible (i.e., drop-in, withthe same bitstream) with the equivalentXC4000 devices.
Unique capabilities and features of theXC4000E FPGAs include:• Up to 50 percent faster circuit speed
(XC4000E-2 as compared to XC4000-4;see table on page 24)
• 60 percent faster carry chain for arith-metic functions
• Lower component prices than theXC4000 family
• Select-RAM memory reduces chip countand design time while increasing RAMperformance by up to 2X
• Select-RAM memory is mode-selectable- synchronous/asynchronous- single-port/dual-port
• 100 percent PCI compliant and suitable
Architectural Featuresof the XC4000E
The architecture of the XC4000E is asuperset of the XC4000; XC4000E devicesare bitstream and pin-compatible with theequivalent XC4000 family FPGAs. Thus,current designs using XC4000 FPGAs cantake immediate advantage of the XC4000E’sincreased speed by simply inserting newdevices into existing XC4000 sockets.
The XC4000E architecture features anenhanced CLB (configurable logic block)with several new modes for configuringon-chip memory (called Select-RAM). Aswith the XC4000 architecture, the CLB’slook-up tables optionally can be used as
19
on-chip ROM or RAM memory; memoryblocks of any size or width can be con-structed from multiple CLBs and locatedanywhere in the array. The XC4000E ex-tends that flexibility by adding an optionalsynchronous (edge-triggered) mode thatsimplifies the timing of the memory inter-face, and an optional dual-port mode thatsupports simultaneous read and writefunctions. Furthermore, the memory cellscan be programmed during device opera-tion or initialized as part of FPGA configu-ration. The synchronous and dual-portRAM modes ease the implementation ofembedded configuration registers and on-chip data buffering in applications such aslocal area networking (LAN) switches,Peripheral Component Interconnect (PCI)
bus interfaces, and asynchronous transfermode (ATM) controllers.
Additionally, the routing scheme of theXC4000E architecture was redesigned andoptimized to improve CLB access andincrease routing connectivity through theaddition of more routing switches. Newpaths also were added within the CLB; theH function generator has two additionalsources for inputs (see figure). This newarchitecture improves utilization and pro-vides shorter wire lengths, thereby reduc-ing interconnect delay.
Other new features include built-inclock enables for the registers in the I/Oblocks, programmable TTL or CMOS inputvoltage thresholds and output levels, and“Soft Start-Up,” a feature that activates the See XC4000E, page 24
Simplified block diagram of theXC4000E CLB (RAM and Carry Logicfunctions not shown)
20
The XC8100 FPGA Family The new MicroVia antifuse uses amor-
phous silicon as the insulator between twometal layers. When combined with three-layer-metal processes, the MicroViaantifuses can reside between the secondand third metal layers. Thus, both theprogramming elements and the intercon-nect routing can reside above the logiccells, significantly decreasing die size.
In other words, the XC8100 FPGA’srouting resources — both wires andprogrammable interconnections — arestacked above the gates, as in a sea-of-gates gate array. Because the routing nolonger takes up die area, the XC8100achieves the seemingly contradictorycombination of extensive routing on avery small die. Hundreds of test cases andreal-world designs (entered with VHDL orVerilog and usually designed for anotherFPGA or ASIC architecture) have beenretargetted to the XC8100 devices; allhave been implemented successfully.
The XC8100 ArchitectureThe XC8100 FPGA architecture has
three main configurable resources:configurable logic cells (CLCs), input/output blocks, and interconnections.
The CLCs provide the functional ele-ments for constructing the design’s combi-natorial and sequential logic. In keepingwith the sea-of-gates architecture, theCLCs have a fine-grained structure. EachCLC has four inputs and one output, plusa special cascade input and output. TheCLCs are internally programmable to allowa wide range of logic functions to mapefficiently to the architecture; program-mable choices include input inversions,several types of combinatorial functions,synchronous logic internal feedback paths,three-state enables, and cascade enables.Each cell can be used to implement com-binatorial logic (sum-of-products or ANDfunctions), a latch or a three-state buffer.
The new XC8100 family is Xilinx’s firstsingle-chip, one-time-programmable FPGAfamily, based on the MicroViaTM antifuseprocess. There are four initial members inthe family (see table 1), and samples areavailable now for the XC8101-1, XC8103-1and XC8106-1 devices.
MicroViaThe new MicroVia technology combines
a three-layer-metal CMOS process, a metal-to-metal antifuse programming elementand a sea-of-gates architecture. The combi-nation of these three elements allows thedevelopment of FPGAs with extensiverouting resources and high gate utilizationin a very small die size.
Antifuse programming elements arenon-conductive until programmed. Earlier
generations of antifuse-basedFPGAs use a transistor-type,polysilicon antifuse whereinan oxide forms an insula-tor between a polysiliconlayer and the silicon die.A portion of theantifuse is made fromthe same silicon layeras the transistors onthe die. As a result,the FPGA architec-tures must be“channeled” (the
interconnect and itsprogrammable switches run in
channels between the logic cells).
Table 1: XC8100 FPGA family members
XC8101 XC8103 XC8106 XC8109
Capacity (gates) 1200 3300 5600 8700
Cells 384 1024 1728 2688
Flip-flops (max) 182 512 864 1344
I/O 80 128 168 208
21
Enters ProductionTwo adjacent latches are combinedthrough the cascade connection to createa D-flip-flop.
Thus, depending on the input netlist,any CLC can implement a combinatorial,synchronous or three-state buffer function.The XC8100 software has the flexibility tochoose the best cell structure dependingon the function to be implemented. Theobjective is to allow the user to designentirely at a high level, without regard tothe resources available on the device, andstill achieve near-100-percent gate utiliza-tion. Designs can be entered in HDLs withlittle concern for the FPGA architecture.Thanks to the programmable CLC and anabundance of routing resources, XC8100devices often will replace competitiveFPGAs claimed to be 30-50 percent larger.Other features of the architecture include:• Low power CMOS technology• Pin-compatible with the XC4000 and
XC5200 FPGA families• 24 mA drive per pin with capacitive
or resistive load drivers• Built-in JTAG boundary scan logic• Flexible clocks/buffers (e.g., the
XC8106 can have up to 72 clocks.)• Extensive test circuitry for 100 percent
testability
Design SecurityThe XC8100 offers a high level of
security for designs that might be subjectto reverse-engineering attempts. First, theXC8100 software automatically storesdesign information in a compressed andencrypted format. Second, the MicroViatechnology is practically impossible toreverse-engineer. The antifuses are pro-grammed between the second and thirdmetal layers and, therefore, are covered bya layer of metal and a protective passiva-tion layer. The programmed state of theantifuse cannot be detected by inspection;removal of the protective layers would
inevitably damage the underlyingantifuses. Furthermore, antifuses arevirtually indistinguishable from regular,permanent “vias” between the metal lay-ers. (The XC8106 has more than 750,000antifuses, about two percent of which areprogrammed in a typical application.)
XACT step Series 8000 SoftwareBecause the XC8100 architecture is
gate-array-like, the design flow is ASIC-like. Like all new Xilinx architectures, theXC8100 uses the standard Xilinx libraryconventions. However, the very differentXC8100 architecture required a newplacer, router and other developmentsoftware. Thus, the initial software forthe XC8100 is different from that of theSRAM-based products and will be offeredseparately.
The first CAE interfaces focus onsynthesis, both workstation and PC-based.This includes support for Synopsys,Mentor Graphics Autologic, Viewlogic
See XC8100 PRO-DUCTION, page 24
Each CLC can be configured foreither combinatorial, sequentialor three-state buffer functions.
22
Introducing the XC6200 FPGA Architecture:Reconfigurable processing refers to
the use of in-system-programmable FPGAsas processing elements, combining theversatility of a programmable solutionwith the performance of dedicated hard-ware. (See XCELL #16.) Most FPGA-basedprocessors are implemented as coproces-sors dedicated to offloading computa-tionally-intensive tasks from a host proces-sor; in other words, the main program isexecuted by a traditional processor, andcertain tasks are assigned to the FPGA-based coprocessor to accelerate theirexecution.
This approach exploits the fact thatmost of the processing time for compute-intensive tasks is spent in relatively smallportions of the code, and hardware accel-eration can significantly improve overallperformance. Tasks can be swapped in
and out of thecoprocessor asneeded throughreconfiguration ofthe FPGAs.
Today’s FPGAarchitectures arebeing used to con-struct reconfigurablecoprocessors. (TheXC4000 FPGA fam-ily, with it’s on-chipmemory capability,has been particu-larly popular forreconfigurable com-puting applications.)
However, these general-purpose architec-tures have some limitations.
The interface to the main processor’sbus must be implemented using program-mable logic resources in the FPGA, whichmay consume a significant portion of theFPGA resources. The internal FPGA archi-
tectures are not always optimal for thedata-path algorithms typical of coproces-sing applications. Providing bus access tolarge numbers of internal registers requirescareful design. On-chip memory capacitiesare too small for some algorithms. Recon-figuration times are relatively long (severalmilliseconds) for computing operations,and partial reconfiguration (reconfiguringjust a portion of the FPGA) is difficult.
These limitations have been addressedin the new XC6200 FPGA architecture —an SRAM-based FPGA architecture specifi-cally designed for implementingreconfigurable coprocessors in embeddedsystem applications. The XC6200 architec-ture features a built-in processor interface,a fine-grained cell structure, abundantrouting, and support for fast partial or fullreconfiguration. The register-rich XC6200 isideally suited for computationally-intensivedatapath applications.
XC6200 FPGA Architectural Features
• FastMAPTM interface. Besides the usualprogammable I/O, the XC6200 architec-ture includes a dedicated interface,called the FastMAP interface, designedto connect directly to a host processorbus. The interface can be configured fora 32-bit, 16-bit or 8-bit interface. Thisbuilt-in, memory-like interface simplifiessystem design and directly interfaces tomost embedded processors withoutconsuming any FPGA resources. TheFastMAP interface provides high-speedaccess to all internal registers in thelogic cells. Any register can be mappedinto the memory address space of thehost processor, allowing for simplehardware and fast data transfers.
• Ultra fast configuration andreconfiguration. The FastMAP inter-face also provides ultra-fast configura-
23
The First FPGA Architecture Optimized forCoprocessing in Embedded System Applications
tion capability — up to 1,000 timesfaster than traditional FPGAs. Systemperformance is further improved by thedynamic partial configuration capability,allowing the modification of parts ofthe FPGA while the other algorithms inthe FPGA continue uninterrupted. Aserial configuration mode is available.
• Flexible, fine-grained logic cell. Theprogrammable logic of an XC6200FPGA is composed of a large array ofsimple, reconfigurable logic cells. Eachcell contains both programmable logicand routing resources. The cells aresimpler than previous FPGA genera-tions, since coprocessing applicationstend to be more regular and register-intensive than random logic. Each cellcontains a flip-flop and combinatoriallogic capable of implementing any two-input function or any type of 2-to-1multiplexer. Cells are arranged in 4-by-4 blocks and 16-by-16 tiles.
• High capacity distributed memory.The very nature of coprocessing de-mands varying amounts of memorydepending on the algorithm beingexecuted at a given time. The XC6200addresses this by offering high-capacitydistributed memory that the user cantailor to suit the application. Each cellcan be used for either logic or memoryfunctions. In the memory mode, eachcell can be configured to provide twobytes of ROM or RAM. This memorycan be accessed via the FastMap inter-face, by logic implemented in theFPGA, or both.
• Abundant routing resources. Sixdifferent types of hierarchical routingresources are offered in the XC6200
architecture yielding fast predictablerouting delays. In most other architec-tures these routing delays grow geo-metrically with distance, whereas in theXC6200 they grow logarithmically.
• Symmetric architecture for positionindependent design mapping. TheXC6200 architecture is very symmetricin cell structure and routing resources,making it possible to implement de-signs that are position-independent.This ability to relocate designs withinthe FPGA can greatly increase utiliza-tion and provides greater latitude inswapping algorithms in and out of anXC6200 family FPGA.
The XC6200 Product FamilyThe initial product roadmap consists of
devices with gate counts as high as 100Kgates or memories as large as 256K bits.Products will become available over thenext four quarters.
New XACTstep Series 6000Development System
The advanced XC6200 architecture hasan equally advanced development system.The system fully exploits the architecturewith the push of a button or give thedesigner complete hands-on control. Atabout 100 gates/second of place and routetime, it’s every bit as fast as the XC6200architecture.
Product Function Cells Usable Gates 1 Max. Memory Availability
XC6209 2304 9K ~ 14K 36K bytes 1H96
XC6216 4096 16K ~ 25K 64K bytes 4Q95
XC6236 9216 36K ~ 56K 144K bytes 1H96
XC6264 16348 64K ~ 100K 256K bytes 2H961based upon 4~6 gates/function cell.
24
devices, you can begin exploiting thespeed of the XC4000E-3 today using theexisting XC4000 support software! Simplydownload the -3 speed files from theXilinx bulletin board (in the Software Helparea) and begin designing. You’ll be ableto program your XC4000E-3 the day itarrives. (Of course, this approach does notprovide access to the new features of theXC4000E architecture.)
A new module for the new XACTstepsystem that allows users to take advantageof the enhanced features of the XC4000Efamily will be available in early 4Q95 atno charge to users with an active mainte-nance contract.
Table 2 lists the initial members of theXC4000E family and their projected avail-ability.
Favorable reports have come in fromearly users of the XC4000E family. JimSimkins, senior engineering specialist atE-Systems, a manufacturer of military andgovernment systems, reports that “Thereare dramatic speed increases using theXC4025E device — in fact, up to two tothree times in several cases. Currently,E-Systems is using an XC4025E device toimplement a DSP function that processes11.5 bops (billion arithmetic and storageoperations per second), with anequivalent capacity of 170,000 LSILogic gates.”
XC4000EContinued from page 19
output buffers with a slow slew rate at theend of the configuration process to avoidsystem noise. Once the I/O blocks areactivated, slew rates are set to their pro-grammed values.
Begin Designing TODAY!Because the XC4000E FPGAs are drop-
in compatible with the equivalent XC4000
TABLE 1: Example benchmarks XC40XXE-2 XC40XXE-4
Data Path 156 MHz 109 MHz
State Machine 69 MHz 55 MHz
16 Bit pre-scaled counter 115 MHz 64 MHz
Address map decoder 71 MHz 50 MHz
TABLE 2:DENSITY RANGE DENSITY RANGEWITHOUT RAM WITH RAM* AVAILABILITY
DEVICE (in usable gates) Sampling ProductionXC4003E 2,500 - 3,000 4,000 - 6,000 4Q95 Q196XC4005E 4,000 - 5,000 7,000 - 11,000 Now 4Q95XC4006E 5,000 - 6,000 8,500 - 15,000 Now 4Q95XC4008E 6,500 - 8,000 11,000 - 18,000 Now 4Q95XC4010E 8,000 - 10,000 14,000 - 22,000 Now 4Q95XC4013E 10,000 - 13,000 19,000 - 31,000 Now 4Q95XC4020E 18,000 - 20,000 28,000 - 44,000 4Q95 4Q95XC4025E 22,500 - 25,000 36,000 - 57,000 Now 4Q95
*10% - 30% RAM usage
XC8100Production
Continued from page 19
ProSynthesis, Exemplar, and Motive, aswell as VHDL and Verilog models. (Con-tact your local Xilinx representative formore details or information about otherinterfaces.)
There are several significant new fea-tures in the Series 8000 software. First, alllogic and nets, including hierarchy, aremaintained by the back-end XC8100 tools,so this information is consistent for simu-lation and debugging; this feature is calledTrueMapTM logic mapping. Second, a newrouter, called PowerMazeTM, routes thou-sands of gates per second. Third, thanksto a new algorithm, Series 8000 software
can do incremental design within thesynthesis environment. Fourth, patentedcircuitry and software allows every deviceto be 100 percent testable, including anautomatic post-programming verificationwithout test vectors.
For more informationA data sheet and a product overview
are available from your local Xilinx repre-sentative and on the Xilinx World WideWeb site. License-free demonstrationsoftware also is available. Contact yourlocal Xilinx sales office or representativefor the latest availability and pricinginformation.
R
PRODUCT INFORMATION — DEVELOPMENT SYSTEMS
25
Improved Synthesis Support for EPLDsSynthesis users have plenty of reasons
to try the new and improved XACTstepversion 6. This latest version of the Xilinxcore software has been optimized forsynthesis, providing significant improve-ments in speed and density among severalnew features that make EPLD designseasier to develop. Improvements include:
• Logic Optimization - XACTstep EPLDimplementation tools automaticallyproduce shorter cycle times, shortersetup times, and reduced pin-to-pindelays. The EPLD fitter now uses re-fined algorithms for flattening gatelevel logic produced from synthesis,resulting in better overall speed anddensity. Table 1 details performanceimprovements seen in actual customerdesigns.
• Timing Driven Optimization - XACT-PerformanceTM optimizes designs basedon user-specified timing requirements.The software now supports path-timingconstraints for EPLDs in the same man-ner as for any other ASIC technology;for HDL-based designs, these timingspecifications are expressed directlythrough the synthesis tool interface.Timing specifications are automaticallytransmitted to the XEPLD fitter usingthe same TIMESPEC attributes currentlyused for Xilinx FPGAs. The task ofproducing high-performance designs isnow a lot easier.
• Full Timing Analyzer - XACTstepversion 6 includes a new timing ana-lyzer that can create a variety of reportsto meet specific needs. These reportscan provide summaries of the fullsystem or just specific paths and pathtypes. This new EPLD timing analyzeris now compatible with the XilinxFPGA timing analyzer. Timing reports
are easier to readwith more detailedinformation.
Xilinx is committedto providing the bestsynthesis support in theprogrammable logicindustry with on-goingsupport and develop-ment for many third-party synthesis tools,including:• Synopsys - FPGA Compiler, Design
Compiler logic synthesis; VSS full-timing simulation.
• Exemplar - Galileo version 3 logicsynthesis (new from Exemplar).
• ViewLogic - ViewSynthesis logic syn-thesis
• Cadence - Synergy logic synthesis;Verilog timing simulation.
• Mentor Graphics - AutoLogic logicsynthesis.
• Data I/O - Synario and ABEL HDLlogic synthesis.
Xilinx is committed to
providing the best synthesis
support in the programmable
logic industry with on-going
support and development for
many third party synthesis tools.
Continued on the next page
Table 1: Cycle Time and Density Improvements in XEPLD 6.0
XEPLD 5.1 Macro- XEPLD 6.0 Macro-Device cells tCYCLE Device cells tCYCLE
1 7336-5PC44 32 28.0ns 7336-5PC44 16 10.4ns2 73108-7PC84 76 31.0ns 7354-7PC44 25 10.5ns3 73108-10PQ160 82 31.0ns 73108-10PQ160 75 16.0ns4 73144-10PQ160 95 49.0ns 73108-10PC84 95 31.0ns5 None (No Fit) (142) - 73144-10PQ160 105 38.5ns
This table is based on customer designs that were expressed in generic VHDL with noinstantiations. The designs were processed by the Synopsys FPGA compiler, targetingthe Xilinx XC7000 library, to produce XNF netlists. The netlists were processed with theindicated version of the XACT fitter, using default options and no timespecs.
For most designs there is a significant improvement in cycle time, and density is oftenimproved enough to allow use of a smaller device. So, higher performance designs areproduced at a lower cost.
26
Tools for both VHDL and Verilog HDLdesign entry are available. VITAL-compli-ant simulation models are available for avariety of third-party simulation toolsincluding Cadence Verilog and ModelTechnologies. In addition, the EPLD physi-cal device models are available from LogicModeling, a division of Synopsys.
So, no matter what tools are used,Xilinx provides everything needed toproduce high-performance EPLD designswith minimal effort.
For product availability or otherinformation, please contact your localXilinx representative.
SynthesisSupport
Continued fromthe previous page
NewAdvanced Design System
The XACTstep Advanced package isavailable now. Easy upgrade paths forexisting XACT and NeoCAD FPGAFoundry users also are available. Contactyour local Xilinx sales representativefor ordering information.
As reported in XCELL #17, Xilinx hasmerged with NeoCAD, Inc. of Boulder,Colorado, a leading supplier of FPGAdesign software. As a result of the merger,Xilinx recently brought to market a newFPGA design system called the XACTstepTM
Advanced package — the first new prod-uct offering that leverages the NeoCADsoftware technology.
The Advanced package featuresXACTstep Foundry, NeoCAD’s core designsystem for FPGA implementation (formerlycalled NeoCAD FPGA Foundry), bundledwith the XACTstep system from Xilinx(formerly called XACT).
XACTstep Foundry, featuring advancedtiming driven placement and routing
technology, has a proven trackrecord for helping users achievemaximum utilization and perfor-
mance for Xilinx FPGA designs.XACTstep Foundry is netlist and li-
brary compatible with XACTstep, andsupports the Xilinx XC4000, XC3100/A,
and XC3000/A FPGA families. It addsparticularly significant value to theimplementation of high-density de-signs, and includes support for theXC4025. XACTstep Foundry in-cludes optional high-level synthesis
integration, multi-device partitioningand distributive processing capabilities. It
executes on PCs and workstations, includ-ing Sun Solaris.
Update NewsThe latest revision of XACTstep Foundry(version 7) was shipped this summer toNeoCAD FPGA Foundry owners with aXilinx configuration and active mainte-nance contract.
XACTstep version 6 updates are sched-uled for first customer ship in October.Most users will receive their updates inthe fourth quarter. XACTstep version 6supports the XC2000, XC3000, XC3100,XC4000, XC5000, and XC7000 compo-nent families.
Xilinx is hard at work finalizing a newsoftware technology strategy and re-lease plan leveraging the best softwaretechnologies of both Xilinx and NeoCAD.New products integrating the best ofXACTstep and XACTstep Foundry, sched-uled for introduction in 1996, will resultin unparalleled power, functionality andease-of-use for FPGA designers. Detailson these products will become availablein the coming months.
27
DESIGN HINTS AND ISSUES
R
HDL Synthesis Design Guide for FPGAsconcepts also apply to other synthesistools and other Xilinx FPGAs. Synopsysand non-Synopsys users alike will findthis document extremely useful. All designexamples are available in Verilog andVHDL. Xilinx endorses both (thoughsome find VHDL more difficult to learnthan Verilog).
To get the most from this guide, Xilinxrecommends that you be conversant withVHDL (or Verilog), the synthesis tool andthe Xilinx Development tools.
Table of Contents
This guide covers the following topics.
• Chapter 1, “Getting Started,” provides ageneral overview of designing FieldProgrammable Gate Arrays (FPGAs)with HDLs. It includes installationrequirements and instructions.
• Chapter 2, “HDL Coding Hints,” dis-cusses design hints and examples tohelp you develop anefficient coding style.
• Chapter 3, “HDLCoding for FPGAs,”provides designexamples to help youincorporate FPGAsystem features intoyour HDL designs.
• Chapter 4,“Floorplanning YourDesign,” describes basic operations ofthe XACT-FloorplannerTM and providesHDL design examples that illustratewhich HDL constructs benefit fromfloorplanning.
• Chapter 5, “Building Design Hierar-chy,” describes how to partition yourdesigns to improve synthesis resultsand reduce routing congestion.
To help designers who are new toHDL-based design with Xilinx FPGAs,Xilinx has created the HDL Synthesis De-sign Guide for FPGAs. This 250-page guideprovides general design methodologies fortargeting FPGAs from synthesis.
Hardware Description Languages(HDLs) are used to describe the behaviorand structure of system and circuit designs.The HDL source code is then synthesizedto the target device (e.g., an FPGA). Ingeneral, synthesis can produce results thatare equal to or exceed those of a well-designed schematic. However, synthesisresults depend on the quality of the syn-thesis tool and the style in which the HDLcode is written. Often, it is not sufficientthat the HDL code is just “functionallycorrect”; the code must be written in amanner that directs the synthesis tool togenerate an efficient hardware implemen-tation and that matches the idiosyncrasiesof the particular synthesis tool being used.
For designs that push the limits ofFPGA speed and density, synthesis alone isnot good enough—designer intervention isnecessary. Synthesis tools are not a substi-tute for good digital design techniques andknowledge of an FPGA’s architecture.
Most documentation available todaydescribes how to use synthesis tools effec-tively to target ASICs. However, not all ofthe methods used for ASICs apply to pro-grammable logic design. ASICs have moregates and routing resources than FPGAs.Poorly written code or the use of a synthe-sis tool not designed for FPGAs can resultin an inefficient design. The Xilinx HDLSynthesis Design Guide for FPGAs ad-dresses the use of HDLs and synthesistools for FPGA design.
Although the guide uses the SynopsysFPGA Compiler and the XC4000 device toillustrate the design methodologies, the
For designs that
push the limits of FPGA
speed and density, synthesis
alone is not good enough.
Continued on the next page
28
• Chapter 6, “Understanding High-Den-sity Design Flow,” discusses the designflow for high-density HDL designs.
• Appendix A, “Accelerate FPGA Macroswith One-Hot Approaches,” reprints anarticle describing one-hot encoding indetail.
• Appendix B, “Top Design Scripts,”includes the three script files used tocompile the Top design described inthe “Building Design Hierarchy” chap-ter of the manual.
• Appendix C, “Tactical Software andDesign Examples,” lists the tacticalsoftware and design examples that aredescribed in this manual.
How Do I Get a Copy?The manual and the design examples
are available at the Xilinx Internet FTP site(ftp.xilinx.com), the World Wide Web site(http://www.xilinx.com), and the XilinxTechnical Bulletin Board (XTBB); theyalso will be included on the XACTstep
version 6 CD-ROM when it is released.To read the online version, you will
need a copy of the Adobe AcrobatTM
reader. You can obtain instructions and afree copy of the software from the XilinxWEB site, XTBB, the Xilinx ProgrammableLogic Breaklthrough ’95 CD-ROM, or theappLINX July ’95 CD-ROM.
The design guide refers to three utilityprograms, 27 VHDL design examples and25 Verilog design examples. Two utilities,AddTNM and MakeTNM were createdusing Perl. To run these utilities, you willneed Perl 4.0 or 5.0 (see right).
The instructions on how to retrieve themanual and the design examples from theXilinx FTP site, World Wide Web site andXilinx Bulletin Board are described below.A description of the design examples’ filesand instructions on how to extract the filesare in the “Extracting the Files” section of“Getting Started” in the design guide.
Xilinx Internet FTPThe manual and design examples are available on the Xilinx FTP site.
Descriptions and sizes of the files are shown in the following table.
Compressed File/Direct-Files Description File ory Sizehdl_dg.pdf HDL Synthesis Design Guide for —— 1.9 MB
FPGAs in Adobe Acrobat formatXSI_files • Tactical code 83 K 344 K
• XNF files for RPMs• Default Synopsys setup file
XSI_vhdl VHDL Examples with SIM, SYN andMRA files in Work directory 5.1 MB 13 MB
XSI_vhdl_no_work VHDL Examples without SIM, SYNand MRA files in Work directory. 3.3 MB 10.2 MB
XSI_verilog Verilog Examples 3 MB 9.2 MB
Procedures to retrieve the manual from the Xilinx FTP site:1. Go to the directory on your local machine where you want to down-
load the files:cd directory
2. Invoke the FTP utility — Unix users, type: ftpPC users: contact your system administrator for assistance.
3. Connect to the Xilinx Internet FTP machine, ftp.xilinx.com:ftp> open ftp.xilinx.com
4. Log onto the guest account. It givesyou download privileges.Name (machine:user-name): ftp
Password: your_email_address
5. Go to the pub/XSI_HDL directory.ftp> cd pub/XSI_HDL
6. Retrieve the manual hdl_dg.pdf andthe appropriate design files as fol-lows. Both VHDL and Verilog usersshould retrieve XSI_files.tar.Z. VHDLusers can retrieve the smaller designfile XSI_vhdl_no_work.tar.Z or thefile with the WORK directory,XSI_vhdl.tar.Z. Verilog users shouldretrieve the file XSI_verilog.ftp> get hdl_dg.pdf
ftp> get XSI_file.tar.Z
ftp> get design_files . tar.Z
7. Extract the example files as describedin the “Extracting the Files” section ofthis article.
CONTINUED
HDL SynthesisDesign Guide
Continued from previous page
29
World Wide WebA copy of the manual and design
examples can be obtained from the XilinxWorld Wide Web site. Access the Xilinxhome page under “Product Information ->Application Notes -> HDL Design Guide.”
Xilinx Technical Bulletin BoardThe manual and design examples are available on the Xilinx
Bulletin Board (XTBB). XTBB is a 24-hour electronic bulletinboard available to all registered XACTstep customers. Refer tothe 1994 version of The Programmable Logic Data book for acomplete description of XTBB, including how to locate anddownload files.
A description and size of the files are shown in the tablefollowing. Note: The manual hdl_dg.zip is very large and maytake a long time to download.
Compressed DirectoryFiles Description File Sizehdl_dg.zip HDL Synthesis Design Guide for 1.6 MB
FPGAs in Adobe Acrobat formatZipped (using PKZIP)
tactical.uu • Tactical code 115 K 344 K• XNF file for RPMs• Default Synopsys setup file
vhdl_ex.uu Source files and major files for 2.6 MB 5.1 MBVHDL Examples
ver_ex.uu Source files and major files for 2.5 MB 4.7 MBVerilog Examples
To retrieve the files from the XTBB:
1. Go to the directory on your local machinewhere you want to download the files:cd directory
2. Access the XTBB as described in of TheProgrammable Logic Data book (Chapter 6).
3. Locate the files in the application area of theXTBB. The directory names are listed in thetable above.
4. Retrieve the zip and encoded design files.
5. Unzip the file hdl_dg.zip file:unzip hdl_dg.zip
6. Follow the instructions below to undecodeand uncompress the files.
Extracting the Compressed and Encoded filesAfter you have retrieved the manual and design examples, perform the follow-
ing to extract the compressed and encoded files:1. If the file is uu encoded (i.e. has an .uu extention) undecode the file as follows:
uudecode file .uu
2. Uncompress the files:uncompress file .tar.Z
3. Extract the files:tar xvf file .tar
How to Get PerlGet information about Perl (Perl FAQ) from the Unix FTP site:• North America:
ftp://fpt.cis.ufl.edu/pub/perl/doc/FAQftp://fwp.khoros.unm.edu/pub/perl/faq.gz
• Europe:ftp://ftp.cs.ruu.nl/upb.NEWS.ANSWERS/perl-faq/ftp://ftp.funet.fi/pub/languages/perl/doc/faq
• Access Perl All-Sorts information on the World Wide Web:http://www.khoros.unm.edu/staff/neilb/perl/http://www.metronet.com/1h/perlinfohttp://ww.cis.ufl.edu/perl
Software RequirementsTo synthesize, floorplan and implement the de-
sign examples, you need the following versions ofsoftware installed on your system. (Either XACTstepor XACTstep Foundry is required, but not both.)
SOFTWARE VERSION
Xilinx Synopsys Interface (XSI) 3.2.0 or later
XACTstep 5.1.0 or later
XACTstep Foundry* 7.0 or later
Synopsys FPGA Compiler 3.2 or later
Xilinx Floorplanner Contact Xilinx sales rep.
XC4025 die files Contact Xilinx sales rep.
* XACTstep Foundry v7 does not support the Xilinx Floorplanner.
You can download the Adobe Acrobatreader for Windows, Mac and SPARC froma link to Adobe’s home page in the Appli-cation Notes section. The design examplesare also available on the Web.
30
Overshoot and UndershootThe “Absolute Maximum Ratings” table in the Xilinx Data Book restricts the signal-
pin voltage to a maximum 500 mV excursion above VCC
and below ground. The purposeof this tight specification is to prevent uncontrolled current in the input-clamping ESD-protection diodes. Such specifications are common in the industry; some manufacturerslimit the excursion to 300 mV.
This specification seems to be clean and simple, but it is violated in almost everypractical design. When modern CMOS devices on PC boards are interconnected withunterminated traces, reflections (commonly called “ringing”) cause overshoots and under-shoots of substantial amplitude (2 V and more). The recent migration to smaller devicegeometries has made the IC outputs even faster and increased the slew-rate, causingmore reflections, even on short PC-board traces.
Fortunately, this problem has an easy solution:The input voltage is not the important consideration. The real concern is the current
through the input protection diode and other input structures. Excessive current cancause latch-up if it exceeds hundreds of milliamps and if it lasts for microseconds(shorter duration current spikes do not activate the SCR-like latch-up mechanism).
PC-board reflections, on the other hand, usually have a short duration (just a fewnanoseconds), and have an impedance of 40 to 100 Ω, which makes them incapable ofcausing latch-up. They don’t drive enough current and they don’t last long enough tocause any harm.
Here is the new Xilinx specification:“Maximum DC overshoot or undershoot above V
CC or below GND must be limited to
either 0.5 V or 10 mA, whichever is easier to achieve. During transitions, the device pinsmay undershoot to -2.0 V or overshoot to V
CC + 2.0 V, provided this overshoot or under-
shoot lasts less than 20 ns”.
Low-Pass Filtering of Noisy Inputssuccessive samples have been identical. In other words, alldisturbances shorter than two clock periods are guaranteedto be suppressed. (For a slow clock source, see the RC oscil-lator on page 9-22 of the Xilinx Data Book.)
In the rare case of severe noise on a digital input, alow-pass filter, as illustrated, can clean up the signal, at theexpense of additional throughput delay. This circuit usestwo CLBs and recognizes an input change only after three
31
XC4000E Conceptual ModelFigure 1 shows a conceptual model of
the XC4000E RAM, configured as a 16x1dual-port, edge-triggered RAM.. This dia-gram will be used to describe the variousedge-triggered and dual-port capabilitiesavailable within each XC4000E logicblock. (The diagram is not intended toconvey the actual circuit implementation,but rather to describe the functionality.)
A single Configurable Logic Block(CLB) contains two function generators,which can be configured as one 16x1dual-port RAM, as shown in Figure 1, oras a 32x1 single-port RAM. Alternatively,
Although it provides increased perfor-mance and several new features, eachmember of the new XC4000E FPGA familyis pin- and bitstream-compatible with itscorresponding XC4000 cousin.
While maintaining all of the XC4000’scapabilities, the XC4000E adds theseprominent new features:
• Distributed on-chip RAM
• Synchronous or edge-triggered RAMwriting that simplifies timing and im-proves performance. Careful timingrelationships between address, data,and write enable are no longer re-quired.
• Dual-port RAM mode that providessimultaneous read/write capability. Thismode is especially useful for buildingFIFOs and buffer memories. Dual-portRAM is always edge triggered.
• The ability to pre-initialize the contentsof RAM on power-up. This featuresimplifies an overall design in that RAMvalues are automatically defined. Noadditional logic is required to performthe initialization.
Table 1 describes the relative capabili-ties of the XC4000 and XC4000E families.
Using the new capabilities, memory-based designs operate at much higherspeeds. For example, a First-In, First-OutMemory (FIFO) can double in speed whenimplemented with edge-triggered RAMcompared to level-sensitive RAM. Designscan take advantage of the edge-triggeredfunctionality to eliminate input data regis-ters, significantly reducing the size of thecircuit.
Dual-port mode allows simultaneousreading and writing, effectively quadru-pling the speed of a FIFO over level-sensi-tive implementations (a first doubling as aresult of edge-triggered write, and a sec-ond doubling due to the dual-port mode).
Continued onthe next page
Examining XC4000E RAM CapabilitiesTable 1. RAM Capabilities of XC4000 and XC4000E
Feature XC4000 XC4000E
On-chip RAM
Level-sensitive RAM write
Single-port capability
Dual-port capability
Edge-triggered RAM write
Initialized RAM data at power-up
Figure 1: Conceptual model of dual-port memoryimplemented in an XC4000E CLB.
32
the two function generators can be indi-vidually configured as any combination of16x1 single-port RAM and 4-input combina-torial logic functions. The RAM outputs, aswith any other function generator outputs,can optionally be registered within the samelogic block.
Edge-Triggered WriteThe XC4000E provides the choice of
level-sensitive or edge-triggered writecapabilities. Both options are available forsingle-port mode, while dual-port mode isalways edge-triggered. Most designers arefamiliar with level-sensitive RAM. This typeof RAM is similar to most SRAM devicesavailable on the market.
One disadvantage of level-sensitive RAMis that it requires a precise timing relation-ship between the Address, Data and WriteEnable signals. Maintaining such relation-ships inside an array-based device can be
difficult because thedesigner does nothave direct controlover the routing delayswithin the device.
A better approachfor system design is touse clocked or edge-triggered RAM, be-cause edge-triggeredwriting simplifies theRAM timing. With the
introduction of the XC4000E, this option isnow available to FPGA designers. Insteadof a complex relationship between varioustiming parameters, the XC4000E RAM tim-ing operates like writing to a data register.Data and address are presented. The regis-ter is enabled, after which a clock edgeloads the data into the register as shown inFigure 2.
The signals used during a write opera-tion are described in Table 2. These signalsare derived from Figure 1.
During a write operation, data is pre-sented on the D input. The write location ispresented on the address inputs, A[3:0]. TheRAM block is enabled for writing by a logichigh on the write enable input, WE.
The write clock input, WCLK, can beconfigured as active on either the risingedge (default) or the falling edge. Therising edge will be used throughout theseexamples. On the rising edge of WCLK, theD, A[3:0], and WE inputs are captured asshown in Figure 2, thereby synchronizingthem to the clock.
A short, built-in delay on the WCLKsignal allows the signals to propagatethrough the decoder logic that enables theappropriate memory cell — the one corre-sponding to the correct address location inthe RAM. The data is clocked into the en-abled cell by the delayed clock edge. Thenew RAM data is available at the RAMoutputs a short time later. The timing dia-gram in Figure 2 shows the case where theA[3:0] address does not change, and SPOreflects the data just written.
The WCLK input to the logic block isthe same input used to clock the CLB flip-flops, but it can be separately inverted.Consequently, RAM output data can becaptured in the flip-flops, if desired, oneither the inactive edge or the next activeedge of WCLK.
Dual-Port ModeMost RAMs have a single address port
and a single output port. These are calledsingle-port RAMs. However, some applica-tions require more than one port. FIFOs are
ExaminingXC4000E RAM
CapabilitiesContinued from previous page
Table 2. Edge-triggered RAM Description
Signal I /O Description
A[3:0] I Address input for writing both ports of the RAM, and reading thesingle port.
DPRA[3:0] I Address input for reading the dual port.
D I RAM Data input.
WE I Write enable input. When high, the RAM may be written with thedata presented on the D input.
WCLK I Write clock input. Clocks the data into the RAM when WE is high.Also captures and synchronizes the A[3:0], D, and WE inputs.
SPO O Single-port RAM output. RAM location is controlled by A[3:0]inputs. SPO is not controlled by the WCLK input.
DPO O Dual-port RAM output. RAM location is controlled by DPRA[3:0]inputs. DPO is not controlled by the WCLK input.
Figure 2. Edge-Triggered RAM Write Cycle
33
one example of an application that ben-efits from additional output and addressports.
In a FIFO, there are separate read andwrite addresses for the memory. A FIFOcan be implemented using a single-portmemory by multiplexing both the read andwrite addresses onto a single address port.This approach, however, prevents a simul-taneous read and write operation. Either aread or a write operation can access theRAM at different times, but not both at thesame time. The extra multiplexers andtheir associated control logic add to thecomplexity of a RAM-based FIFO design. Adual-port RAM—one with two addressinputs and two data outputs—would sim-plify a FIFO design.
Again, Figure 1 provides an example.The logic in the figure is configured as a16x1 edge-triggered dual-port RAM. Datacan be read and written using the A[3:0]address port and the RAM data appears onthe SPO output, just as it would for asingle-port RAM.
Simultaneously, data can be read—butnot written—using the DPRA[3:0] addressport. The RAM data appears on the DPOoutput. Operations with the DPRA[3:0]address port are independent of the A[3:0]address port. Consequently, a RAM loca-tion can be accessed simultaneouslythrough two different ports using the twosets of address and data ports as describedin Table 3.
If both addresses point to the samelocation, and a write is performed usingthe A[3:0] inputs, data appears first on SPOand then on DPO a short time later.
Selecting an Appropriate RAM ModeTable 4 shows the recommended
usage for each RAM mode in the XC4000Earchitecture.
Frankly, there is little reason to uselevel-sensitive mode in new designs nowthat edge-triggered RAM is available. Incases where CLB usage must be mini-mized, single-port edge-triggered mode isrecommended. This mode offers the best
density, although a lower system through-put than dual-port mode for some applica-tions. If simultaneous read and write capa-bility is an asset and silicon efficiency isnot a priority, consider using dual-port,edge-triggered mode for maximum systemthroughput.
Schematic SymbolsUsing the XC4000E edge-triggered and
dual-port RAM capabilities requires specialschematic symbols available within theXC4000E library. All edge-triggered RAMshave symbols that begin with “RAM” andend with S (in the case of single-port,edge-triggered RAMs) or D (in the case ofdual-port RAMs). If no letter is appended,the level-sensitive RAM is referenced.
Initializing RAMsThe XC4000E can initialize RAM to a
known value during FPGA configuration.All types of XC4000E RAM can be initial-ized, including the original level-sensitivemode. The INIT attribute or property isused to initialize RAM to a known value. Ifomitted, the initial value defaults to allzeros. RAM contents are not affected by aglobal reset.
Software SupportThe edge-triggered and dual-port capa-
bilities are supported in XACTstepTM ver-sion 5.2, or later. An XC4000E update maybe required. Edge-triggered, single-portand dual-port RAM are supported in X-BLOXTM with the SYNC_RAM and DP_RAMmodules.
Table 3. Address Port Functionality
Address Port Operation Output Data
A[3:0] Read and Write SPO
DPRA[3:0] Read only DPO
Table 4. RAM Mode Selection
Dual-PortLevel-Sensitive Edge-Triggered Edge-Triggered
Use for New Designs? No Yes Yes
Density (Registered 16x1) 1/2 CLB 1/2 CLB 1 CLB
Simultaneous Read/Write? No No Yes
Relative Performance X 2X 4X (Effective)
34
Building FIFO Memories in the XC4000E
Figure 1: Traditional FIFO with level-sensitive RAM
First-in-first-out memories (FIFOs)receive three significant benefits from thenew edge-triggered RAM option of theXC4000E architecture:• Greatly simplified logic design due to
the elimination of timing from the ex-ternal write enable pulse.
• Fewer data and control logic registersand logic blocks required becausesynchronization is performed by theWCLK pulse within the RAM.
• An approximate doubling of the overallspeed compared with conventionaldesigns.
The remarkable speed improvementresults from the elimination of the externalwrite enable signal as the active control.In a traditional FIFO design using level-sensitive RAM, two methods are availableto generate the write enable. An external2x clock can be used to generate a pulsein the third quarter of the FIFO clockperiod, or the falling edge of the FIFOclock can be used to trigger a glitch onwrite enable. (The latter method is
discouraged because of the risks inherentin internal race conditions.)
A block diagram of a FIFO using anexternal 2x clock and level-sensitive RAMis shown in Figure 1. Whichever methodis used, only half of a FIFO clock period isavailable for data and address lines to
settle prior to initialization of the WriteEnable pulse.
By redesigning the same FIFO to useedge-triggered RAM, an entire clock pulseis available for data and address lines tosettle. For FIFOs of any size, loading onthe address lines usually determines thespeed of operation for the FIFO. Therefore,the modified FIFO operates at about twicethe speed of the level-sensitive version.
Figure 2 shows a block diagram of theedge-triggered FIFO. The divide-by-twoon the clock has been removed, along withthe logic generating the RAM write enablepulse. The registers on data and controlinputs are also no longer necessary.
A FIFO in a PCI (Peripheral ComponentInterconnect) bus interface must operate at33 MHz, and is typically 8 or 16 wordsdeep by 32 bits wide. A 16x32 PCI writeFIFO was implemented using a portion ofa PCI-compliant Xilinx XC4005E-3. Usingthe level-sensitive RAM mode, PCI perfor-mance was met, but not exceeded.Switching to edge-triggered mode, a FIFOwas produced that reliably runs at 60-65MHz, without any manual editing required.
Dual-Port FIFOTo implement a FIFO that can read and
write at the same time, use only the DPOoutput. A[3:0] is the write address, andDPRA[3:0] is the read address. The multi-plexer on the address lines can be re-moved. The arbitration logic in the Con-trol block, which normally selects betweena Read and a Write operation when bothcommands are received simultaneously,can also be removed.
The block diagram for a dual-port edge-triggered FIFO is shown in Figure 3. Theoriginal nine logic blocks in Figure 1 arereduced to five.
When the PCI FIFO referenced abovewas modified to use dual-port RAM, theoperating frequency was about the same— the advantage of removing the address
CONTINUED
35
multiplexers was offset by the routingrequirements of the increased number ofaddress lines. Although the clock fre-quency is approximately 60 MHz, the
same as the single-port implementation,simultaneous read and write allows a datatransfer rate equivalent to 120 MHz in asingle-port FIFO.
Figure 2: FIFO with edge-triggered RAM Figure 3: Dual-port FIFO with edge-triggered RAM
Mixing 3.3 Volt and 5 Volt DevicesIn the past, almost all digital logic devices operated
on a 5 volt standard. To reduce chip size and meet thedemand for higher integration and reduced power con-sumption, the semiconductor industry has started thetransition to 3.3 V logic. In the future, 3.3 volts is likelyto become the dominant supply voltage. For the timebeing, designers must accommodate both types of ICsin the same design. What are the potential problems?
3.3 V Devices Driving Inputs on 5 V DevicesThe lowest output High voltage (V
OH) must be high
enough to exceed the VIH
requirements of the 5 Vdevice. This is not a problem if the 5 V device uses TTL-compatible input thresholds, available on all Xilinxdevices. If the 5 V device has CMOS input thresholds, apull-up resistor to 5 V on each such input will assure asufficiently High input voltage. The resistor should besomewhere between 10 kΩ and 1 kΩ in value. Theupper limit causes the rising input transition to be slow;the lower limit is set by the output current sinking capa-bility of the 3.3 V device output. In the High state, thevoltage will be clamped by the protection diode of the
3.3 V device. With only 1 V across the resistor, thiscurrent will be fairly small, but care should be taken thatthe sum of these pull-up currents does not exceed the3.3 V supply current, thereby reverse-biasing and raisingthe 3.3 V supply voltage.
5 V Devices Driving Inputs on 3.3 V DevicesThe highest output voltage may not force excessive
current into the input of the 3.3 V device. If the 5 Vdevice has a truly complementary CMOS output (likeall Xilinx FPGAs and CPLDS except the XC4000 familydevices), then the input current must be limited by aseries resistor of no less than 100 Ω. This guarantees aninput current below 10 mA, flowing through the inputprotection diode backwards into the 3.3 V supply. Caremust be taken to avoid raising the nominally 3.3 Vsupply voltage above its 3.6 V maximum when a largenumber of active High inputs drive the 3.3 V device.
If the 5 V device has “totem-pole” n-channel onlyoutputs, V
OH is reduced by one threshold and the series
resistor can be reduced or even eliminated, provided thenominally 5 V supply never exceeds 5.25 V.
36
“Hold” is a Four-Letter WordBeware of hold-time problems, because
they can lead to unreliable, temperature-sensitive designs that can fail even at lowclock rates.
“Set-up time” and “hold time” describe thetiming requirements on the data input of aflip-flop or register with respect to the clock
input. The set-up and hold times describe awindow of time during which data must bestable in order to guarantee predictable per-formance over the full range of operatingconditions and manufacturing tolerances.
A positive set-up time describes the lengthof time that the data must be available andstable before the active clock edge. A positivehold time, on the other hand, describes thelength of time that the data to be clocked intothe flip-flop must remain available and stableafter the active clock edge. A positive set-uptime limits the maximum clock rate of asystem, but a positive hold time can causemalfunction at any clock rate. Thus, chipdesigners and system designers strive toeliminate hold-time requirements.
The IC design usually guarantees that anyindividual flip-flop does not require a positivehold time with respect to the clock signal atthis flip-flop.
Hold-time requirements between flip-flopsor registers on the same chip can be avoidedby careful design of the on-chip clock distri-bution network. If the worst-case clock-skewvalue is shorter than the sum of minimumclock-to-Q plus minimum interconnect delays,there is never any on-chip hold-time problem.
It is, however, far more difficult to avoid ahold time problem in the device input flip-
flops, with respect to the device clock input pin.When specifying the data pin-to-clock pin set-up and hold times, the chip-internal clock distri-bution delay must be taken into consideration.It effectively moves the timing window to theright (see figure), thus subtracting from thespecified internal set-up time (which is good),but adding to the hold time (which is very bad).If the clock distribution delay is any longer thanthe data input delay — and it easily might be —the device data input has a hold-time require-ment with respect to the clock input.
This means that the data source, usuallyanother IC driven by the same clock, mustguarantee to maintain data beyond the clockedge. In other words, the data source is notallowed to be very fast. If it is, the receivermight erroneously input the new data insteadof the data created by the previous clock, as itshould. This is called a race condition, and canbe a fatal system failure.
If the receiving device has a hold time re-quirement, the source of data must guaranteean equivalent minimum value for its clock-to-output delay. Almost no IC manufacturer iswilling to do this, and in the few cases where itis done, the minimum value is usually a token1 ns. Any input hold time requirement is, there-fore, an invitation to system failure. Any clockdistribution skew on the PC-board can com-pound this issue and wipe out even the speci-fied short minimum delay.
Xilinx has addressed this problem by addinga deliberate delay to every FPGA data input. InXC3000, and XC3100 FPGAs, this delay is fixedand always present; in XC4000 and XC5200FPGAs, the delay is optional; its value is tailoredto the clock distribution delay (i.e. it is larger forbigger devices). As a result we can claim that noXilinx FPGA Data input has a hold-time problem(i.e., none has a positive hold time with respectto the externally applied clock), when the de-sign uses the internal global clock distributionnetwork (and, in XC4000 and XC5200, uses thedelayed input option). Most competitive devicesdo not offer this feature.
37
Acquiring Application Notesand Design Files
Xilinx constantly strives to provide application notes on topics important for pro-grammable logic users. Table 1 lists some of the newer application notes, including thetargeted device family and available design files:
Table 1. Recently Published Xilinx Application Notes.DESIGN XDOCS
TITLE FAMILY FILES XFACTS WEB
XC4000 Edge-Triggered and Dual-Port RAM Capability XC4000E 80004 YesImplementing FIFOs in XC4000E RAM XC4000E VIEWdraw 80003 Yes16-Tap, 8-Bit FIR Filter Applications Guide XC4000/XC4000E VIEWdraw 80000 YesPlug and Play ISA in an XC4000 XC4000/XC5200 VIEWdraw + ABEL 80007 Yes
2910-Compatible Microprogram Sequencer in an XC4000 FPGA XC4000 VIEWdraw YesDynamic Microcontroller in an XC4000 FPGA XC4000 VIEWdraw 80005 YesDesigning Flexible PCI Interfaces With Xilinx EPLDs XC7300 ABEL, VHDL YesEPLD-Based Segmented Elastic Frame Store for ATM XC7300 80010 YesFully Compliant PCI Interface in an XC3164A-2 FPGA XC3100A Verilog, VIEWdraw 80006 YesConfiguring FPGAs Over a Processor Bus All SRAM FPGAs VIEWdraw 80011 Yes
Pulse-Width Modulation in Xilinx Programmable Logic All VIEWdraw 80009 YesVoltage Monitoring for XC2000 Devices XC2000 80008 Yes
Family — The family for which the appli-cation note was written.
Design Files — If indicated, this columnshows which design files and formatsare available.
XDOCS/XFACTS — If indicated, use thisnumber to retrieve the document fromthe XDOCS E-mail server or from theXFACTS fax server.
• For XDOCS, send an E-mail message to‘[email protected]’ with ‘ send<number>’ in the subject header. Theserver will automatically send auuencoded and compressed PostScriptfile that you can send to anyPostScript-compatible printer. (Youcan also send an E-mail to XDOCS with‘help’ in the subject header to retrievefull instructions on using XDOCS.)
• For XFACTS, just dial 1-408-879-4400and specify the document numberalong with your return fax number.
WebIf “yes,” the document is available on the
World Wide Web. The Xilinx home page,called webLINX, can be found at ‘http://www.xilinx.com/’. The document can befound under Application Notes, which isunder Product Information. The documentsare in Adobe AcrobatTM format. If you do notalready have the Acrobat reader installed onyour machine, then you can jump to theAdobe home page to download it.
IMPO
RTAN
T: Updated Package Pinout InformationIf you are designing with the following devices and pack-
ages, please be aware that pinout information in the 1994 Xil-inx Programmable Logic Data Book, third edition, is incorrectfor XC4010BG225, XC4013BG225 and XC4025.
Updated pinout information is available on the XilinxWebLINX under Part Information, on the Xilinx Bulletin Board(filename “newpins.zip”) and via XFACT/XDOCS (request docu-ment #80012).
38
TECHNICAL QUESTIONS AND ANSWERS
GeneralQ. What are the FXC Libraries included
with XACT 5.1.1?A. In addition to the XC2000, XC3000, XC4000,
and XC7000 libraries, the 5.1.1 release alsoincludes libraries called FXC2000, FXC3000,FXC4000, and FXC7000 that can be used inplace of the Unified libraries to reducesimulation runtime. Simulation of designswith the 5.0.0 Unified libraries sufferedsignificant increases in simulation runtimedue to the addition of more comprehensiveviolation checking. The FXC simulationlibraries do not contain the additional viola-tion checks but are identical in every otherway. NOTE: The XC libraries should be
used to perform a final timing simulation sothat the new violation checking will beperformed.
Q. How do I turn off the internaloscillator in an XC5200 family FPGA?
A. Set the Makebits tag for the oscillator clockto the user clock setting (“OscClk:UserClk”).This means that the internal oscillator clockis replaced by the user clock. The default is“OscClk:Cclk”. Doing this may produce aDRC error since XACT expects a net to beconnected to the osc.CK pin in the top rightcorner of the XACT Design Editor. You mayeither ignore the DRC error, or, to eliminatethe DRC error, connect a grounded net tothe osc.CK pin.
ViewlogicQ. I just installed XACT 5.1.1, and
ProSeries reports: SYSCMD.PIF or SYSBLOCK.PIF
Cannot find file.
Check to insure the path and
filename are correct.
How is this corrected?A. The system window opened by a sys com-
mand or a print command requires the filessyscmd.pif and sysblock.pif. These two filesare missing from the DS-VLS-STD-PC1 pack-age. You can retrieve these two files eitherby installing “PROSYN” from the DS-VLS-EXT-PC1 package, by unzipping theprosyn1.zip file from thewn1\prosyn\group2 directory, or by down-loading 511FIX.ZIP from the BBS. Makesure these two .pif files are in either thePROSER\ or Windows\ directory.
Q. Why do I get the message “TypeMismatch” from ProSeries?
A. PROvhdl, PROgen, PROlib, PROsynth, andPROgen return this error message when noproject has been defined. Defining a projectvia PROjman or PROcapture will cause themessage to go away.
Q. I can run all of the ProSeries softwareexcept ProSim. What could be wrong?
A. PROsim is the only program in the PROSeries 6.0 release that uses the WIN32S 32-bitextender. If all the other PROseries softwareworks, the problem may be that WIN32S isnot installed or the version installed is notcompatible. Try installing WIN32S from the5.1.1 CD. The WIN32S setup.exe program islocated in the WIN32S directory.
Q. Why do I get the error message,“The 386 chip is currently executingin virtual mode under the control ofanother program” from PROseriestools?
A. The versions prior to XACT 5.1.1 containedexecutables that could not be run in Win-dows. Attempting to run these executables inan MS-DOS box would result in this errormessage. Typically, this occurs when anolder, non-Windows compatible executableappears in the path before the new PROSERdirectory. Remove all references toWORKVIEW in the following system vari-ables: PATH, WDIR, and SYSPLT, and themessage should go away.
39
A. If you have an existing setup of Synopsysand XSI, and you upgrade your version ofSynopsys as above, then you must reanalyzeyour designware and simulation libraries.Please see the release notes section entitled‘Analyzing the Designware and SimulationLibraries.’
Q. Can Synopsys 3.2a work with XSI 3.3?A. No. XSI is only compatible with versions of
Synopsys equal to or greater than the XSIversion. In other words:XSI 3.2 can work with Synopsys
3.2a and greater.
XSI 3.3 can work with Synopsys
3.3a and greater.
Synopsys 3.2a will not work
with XSI 3.3.
Q. What are some of the new features inXSI 3.3?
A. Among the major improvements: XSI 3.3supports XC5200 family designs, and XBLOXoptimization has been improved.
SynopsysQ. How can I tell what version of
XSI I have?A. At your command prompt, type
syn2xnf <CR>. A help screen will comeup with a version number of syn2xnf:syn2xnf v3.5.0=XSI 3.2
syn2xnf v3.6.0=XSI 3.3
Q. I was using Synopsys 3.2a andXSI 3.2. Now, I’ve upgradedSynopsys to v3.3a. When I try tocompile my design, I get an errormessage from the SynopsysCompiler:Error: The entity add_sub_ub’
depends on the package
‘std_logic_arith’ which has
been analyzed more
recently.
Please re-analyze the source
file for ‘add_sub_ub’ and try
again.
Information: Compileterminated abnormally.
OVERVIEW OF TECHNICAL SUPPORT FACILITIES
Automated Support SystemsAn incorrect number for the telephone hotline service
in Germany was published on page 29 of XCELL #17.Our apologies for any inconvenience that may havecaused. The correct number is given below.
Xilinx home page - available at http://www.xilinx.com.XDOCS E-mail document server - send an E-mail to [email protected]
with ‘help’ as the only item in the subject header. You willautomatically receive full instructions via E-mail.
XFACTS fax document server - available by calling 1-408-879-4400.
In order to provide timely support for new, high-growth markets, Xilinx Applications has established aseries of E-mail addresses to direct technical inquiries.These addresses may be used to request informationpackets or to ask in-depth technical questions:
Digital Signal Processing applications ...................... [email protected] applications .................................................. [email protected] and Play ISA applications ................................ [email protected] Transfer Mode applications ............... [email protected] logic/computing applications ... [email protected]
Hotline Support, North AmericaCustomer Support Hotline: ........................................ 800-255-7778
Hrs: 8:00 a.m. - 5:00 p.m. Pacific timeCustomer Support Fax Number: ................................ 408-879-4442
Avail: 24 hrs/day-7 days/weekElectronic Technical Bulletin Board: ......................... 408-559-9327
Avail: 24 hrs/day-7 days/weekCustomer Service: ............ 408-559-7778, ask for customer serviceFor software updates, authorization codes, documentation updates, etc.
Hotline Support, EuropeUK , LONDON OFFICE
telephone: (44) 1932 349402fax: (44) 1932 333530Bulletin Board Service: (44) 1932 333540e-mail: [email protected]
FRANCE, PARIS OFFICEtelephone: (33) 1 3463 0100fax: (33) 1 3463 0109e-mail: [email protected]
GERMANY, MUNICH OFFICEtelephone: (49) 89 99 15 49 30fax: (49) 89 904 4748e-mail: [email protected]
40
FAX in Your Comments and SuggestionsTo: Brad Fawcett, XCELL Editor Xilinx Inc. FAX : 408-879-4676
From: ________________________________________ Date: ____________
Please add my name to the XCELL mailing list.
NAME
COMPANY
ADDRESS
CITY/STATE/ZIP
PHONE
I’m interested in having my company’s design featured in a future edition ofXCELL as a Customer Feature.
Comments and Suggestions:____________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________
Please use this form to FAX in your comments and suggestions, or to request an addition to theXCELL mailing list. Please feel free to make copies of this form for your colleagues.
U.S. PostagePAID
First ClassPermit No. 2196
San Jose, CA2100 Logic DriveSan Jose, CA 95124-3450
FAX RESPONSE FORM — XCELL 18 3Q95
CorporateHeadquartersXilinx, Inc.2100 Logic DriveSan Jose, CA 95124Tel: 408-559-7778Fax: 408-559-7114
EuropeXilinx, Ltd.Suite 1B, Cobb HouseOyster LaneByfleetSurrey KT147DUUnited KingdomTel: 44-1-932-349401Fax: 44-1-932-349499
JapanXilinx, KKDaini-Nagaoka Bldg. 2F2-8-5, Hatchobori,Chuo-ku, Tokyo 104JapanTel: 81-3-3297-9191Fax: 81-3-3297-9189
Asia PacificXilinx Asia PacificUnit 2308-2319 Tower 1MetroplazaHing Fong RoadKwai Fong, N.T.Hong KongTel: 852-2410-2739Fax: 852-2494-7159
R