xilinx programs

8/13/2019 Xilinx programs

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TRUTH TA9LE:

A 9 SUM ARR;

0 0 0 0

0 1 1 0

1 0 1 0

1 1 1 1

OUTPUT:



PROGRAM FOR FULL ADDER USING VHDL:

+"-a "/,! ".!%d+o#"11.a++/

,! ".!%d+o#"a"%&.a++/,! ".!%d+o#",$!"#$d.a++/$%"% *,++add "!

'o%(a4-4:"$ !%d+o#"/ !4o,%:o,% !%d+o#")/

$d *,++add/a&"%%, -&a5"oa+ o* *,++add "!

-#"$! 6 a 8o - 8o /o,% 6 (a a$d -) o ((a 8o -) a$d )/

$d -&a5"oa+/

FULL ADDER:



TRUTH TA9LE:

A 9 SUM ARR;

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

OUTPUT:

RESULT:

T&,! %& 'o#a *o &a+*add < F,++ add =a! !",+a%d -

,!"$# VHDL a$d 5"*"d !,!!*,++.

EXPT NO:1(-) DESIGN OF HALF ADDER AND FULL ADDER USING VERILOG



DATE:30.07.2011

AIM:

To d!"#$ %& 'o#a *o &a+* add a$d *,++ add ,!"$# 5"+o#

PROGRAM FOR HALF ADDER USING VERILOG:

od,+ &a+*add(a4 -4 !,4 a)/"$',% a/"$',% -/o,%',% !,/

o,%',% a/8o #1(!,4a4-)/a$d #2(a4a4-)/

$dod,+

HALF ADDER:

TRUTH TA9LE:



A 9 SUM ARR;

0 0 0 0

0 1 1 0

1 0 1 0

1 1 1 1

OUTPUT:

PROGRAM FOR FULL ADDER USING VERILOG:



od,+ *,++add(a4 -4"$4 !,4 a)/"$',% a/"$',% -/"$',% "$/

o,%',% !,/o,%',% a/=" 4*4#/8o #1(4a4-)/8o #2(!,44"$)/a$d #3(*4a4-)/a$d #(#44"$)/o #>(a4*4#)/$dod,+

FULL ADDER :

TRUTH TA9LE:



A 9 SUM ARR;

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

OUTPUT:

RESULT:

T&,! %& 'o#a *o &a+*add < F,++ add =a! !",+a%d -

,!"$# VERILOG a$d 5"*"d !,!!*,++.

EXPT NO:2(a) DESIGN OF HALF SU9TRATOR AND FULL SU9TRATOR USING



DATE:13.0?.2011 VHDL

AIM:

To d!"#$ %& 'o#a *o &a+* !,-%a%o a$d *,++ !,-%a%o ,!"$# VHDL

PROGRAM FOR HALF SU9TRATOR USING VHDL:

+"-a "/,! ".!%d+o#"11.a++/,! ".!%d+o#"a"%&.a++/,! ".!%d+o#",$!"#$d.a++/

$%"% &a!,- "! 'o%(a4-:"$ !%d+o#"/

d4 -o,%:o,% !%d+o#")/$d &a!,-/a&"%%, -&a5"oa+ o* &a!,- "!

-#"$d 6 a 8o -/

-o,% 6 ($o% a) a$d -/$d -&a5"oa+/

HALF SU9TRATOR:

TRUTH TA9LE:



A 9 DIFFERENE 9ORRO@

0 0 0 0

0 1 1 1

1 0 1 0

1 1 0 0

OUTPUT:

PROGRAM FOR FULL SU9TRATOR USING VHDL:



+"-a "/,! ".!%d+o#"11.a++/,! ".!%d+o#"a"%&.a++/,! ".!%d+o#",$!"#$d.a++/

$%"% *,+!,-1 "! 'o%(a4-4:"$ !%d+o#"/d4 -o,%:o,% !%d+o#")/$d *,+!,-1/a&"%%, -&a5"oa+ o* *,+!,-1 "!

-#"$d 6 a 8o - 8o /

-o,% 6 (($o% a) a$d -) o (($o% (a 8o -)) a$d ) /$d -&a5"oa+/

FULL SU9TRATOR:

TRUTH TA9LE:




0 0 0 0 0

0 0 1 1 1

0 1 0 1 1

0 1 1 0 1

1 0 0 1 0

1 0 1 0 0

1 1 0 0 0

1 1 1 1 1

OUTPUT:

RESULT:

T&,! %& 'o#a *o &a+*!,-%a%o< F,++!,-%a%o=a! !",+a%d

- ,!"$# VHDL a$d 5"*"d !,!!*,++.

EXPT NO:2(-)DESIGN OF HALF SU9TRATOR AND FULL SU9TRATOR USING



DATE:13.0?.2011 VERILOG

AIM:

To d!"#$ %& 'o#a *o &a+* !,-%a%o a$d *,++ !,-%a%o ,!"$# 5"+o#

PROGRAM FOR HALF SU9TRATOR USING VERILOG:

od,+ &a+*!,-(a4-4d"**4-o,%)/"$',% a4-/

o,%',% d"**4-o,%/=" /8o #1(d"**4a4-)/$o% #2(4a)/a$d #3(-o,% 4-)/$dod,+

HALF SU9TRATOR



TRUTH TA9LE:


0 0 0 0

0 1 1 1

1 0 1 0

1 1 0 0

OUTPUT:



TRUTH TA9LE:


0 0 0 0 0

0 0 1 1 1

0 1 0 1 1

0 1 1 0 1

1 0 0 1 0

1 0 1 0 0

1 1 0 0 01 1 1 1 1

OUTPUT:

RESULT:

T&,! %& 'o#a *o &a+*!,-%a%o< F,++!,-%a%o=a! !",+a%d

- ,!"$# VERILOG a$d 5"*"d !,!!*,++.

EXPT NO:3(a)DESIGN OF MULTIPLEXER AND DEMULTIPLEXER USING VHDL



DATE:20.0?.2011

AIM:

To d!"#$ %& 'o#a *o ,+%"'+8 a$d d,+%"'+8 ,!"$# VHDL

PROGRAM FOR MULTIPLEXER USING VHDL:

+"-a "/,! ".!%d+o#"11.a++/,! ".!%d+o#"a"%&.a++/,! ".!%d+o#",$!"#$d.a++/$%"% ,+%"' "!

'o% (a4-44d4!14!0:"$ !%d+o#"/ :o,% !%d+o#")/

$d ,+%"'/a&"%%, -&a5"oa+ o* ,+%"' "!!"#$a+ 4*4#4&4"4 : !%d+o#"/

-#"$ 6 # o & o " o / 6 $o% !1/

* 6 $o% !0/# 6 a a$d a$d */& 6 - a$d a$d !0/" 6 a$d !1 a$d */

6 d a$d !1 a$d !0/$d -&a5"oa+/

MULTIPLEXER



TRUTH TA9LE:



S1 S0 OUTPUT

0 0 D0

0 1 D1

1 0 D2

1 1 D3

OUTPUT:

PROGRAM FOR DEMULTIPLEXER USING VHDL:



+"-a "/,! ".!%d+o#"11.a++/,! ".!%d+o#"a"%&.a++/,! ".!%d+o#",$!"#$d.a++/

$%"% d,+%" "! 'o% (84!14!0:"$ !%d+o#"/a4-44d :o,% !%d+o#")/

$d d,+%"/a&"%%, -&a5"oa+ o* d,+%" "!!"#$a+ 4* : !%d+o#"/

-#"$ 6 $o% !1/* 6 $o% !0/

a 6 8 a$d a$d */ - 6 8 a$d a$d !0/ 6 8 a$d !1 a$d */d 6 8 a$d !1 a$d !0/$d -&a5"oa+/

DEMULTIPLEXER



TRUTH TA9LE:

S1 S0 IBP D0 D1 D2 D3

0 0 0 0 0 0 0

0 0 1 1 0 0 0

0 1 0 0 0 0 0

0 1 1 0 1 0 0

1 0 0 0 0 0 0

1 0 1 0 0 1 0

1 1 0 0 0 0 0

1 1 1 0 0 0 1



OUTPUT:

RESULT:

T&,! %& 'o#a *o M,+%"'+8< D,+%"'+8=a! !",+a%d

- ,!"$# VHDL a$d 5"*"d !,!!*,++.



EXPT NO:3(-) DESIGN OF MULTIPLEXER AND DEMULTIPLEXER USING VERILOG

DATE:20.0?.11

AIM:

To d!"#$ %& 'o#a *o ,+%"'+8 a$d d,+%"'+8 ,!"$# 5"+o#

PROGRAM FOR MULTIPLEXER USING VERILOG:

od,+ ,8(!4d4)/"$',% C1:0!/

"$',% C3:0d/o,%',% /=" a4-444*4#/$o% #1(a4!C1)/$o% #2(-4!C0)/a$d #3(4a4-4dC0)/a$d #(4a4!C04dC1)/a$d #>(*4!C14-4dC2)/a$d #(#4!C14!C04dC3)/o #7(444*4#)/

$dod,+



MULTIPLEXER



TRUTH TA9LE:

S1 S0 OUTPUT

0 0 D0

0 1 D1

1 0 D2

1 1 D3

OUTPUT:



PROGRAM FOR DEMULTIPLEXER USING VERILOG:

od,+ d,8(!4d4)/"$',% C1:0!/

"$',% d/o,%',% C3:0/=" a4-/$o% #1(a4!C1)/$o% #2(-4!C0)/a$d #3(C04a4-4d)/a$d #(C14a4!C04d)/

a$d #>(C24!C14-4d)/a$d #(C34!C14!C04d)/$dod,+

DEMULTIPLEXER:



TRUTH TA9LE:

S1 S0 IBP D0 D1 D2 D3

0 0 0 0 0 0 0

0 0 1 1 0 0 0

0 1 0 0 0 0 0

0 1 1 0 1 0 0

1 0 0 0 0 0 0

1 0 1 0 0 1 0

1 1 0 0 0 0 01 1 1 0 0 0 1



OUTPUT:

RESULT:

T&,! %& 'o#a *o M,+%"'+8< D,+%"'+8=a! !",+a%d - ,!"$# V"+o# a$d 5"*"d !,!!*,++.



ENODER :

TRUTH TA9LE:

INPUTS OUTPUTS

;0 ;1 ;2 ;3 ; ;> ; ;7 A 9

1 0 0 0 0 0 0 0 0 0 0

0 1 0 0 0 0 0 0 0 0 1

0 0 1 0 0 0 0 0 0 1 0

0 0 0 1 0 0 0 0 0 1 1

0 0 0 0 1 0 0 0 1 0 0

0 0 0 0 0 1 0 0 1 0 1

0 0 0 0 0 0 1 0 1 1 0

0 0 0 0 0 0 0 1 1 1 1



OUTPUT:



PROGRAM FOR DEODER USING VHDL:

+"-a "/,! ".!%d+o#"11.a++/

,! ".!%d+o#"a"%&.a++/,! ".!%d+o#",$!"#$d.a++/ $%"% dod "!

'o% (a4-4:"$ !%d+o#"/804814824834848>48487 :o,% !%d+o#")/$d dod/a&"%%, -&a5"oa+ o* dod "!!"#$a+ 4*4#: !%d+o#"/

-#"$ 6 $o% a/

* 6 $o% -/# 6 $o% /80 6 a$d * a$d #/81 6 a$d * a$d /82 6 a$d - a$d #/83 6 a$d - a$d /8 6 a a$d * a$d #/8> 6 a a$d * a$d /8 6 a a$d - a$d #/

87 6 a a$d - a$d /$d -&a5"oa+/



DEODER:

TRUTH TA9LE:

E A 9 D0 D1 D2 D3

0 0 0 0 0 0 0

1 0 0 1 0 0 0

1 0 1 0 1 0 0

1 1 0 0 0 1 0

1 1 1 0 0 0 1

OUTPUT:



RESULT:

T&,! %& 'o#a *o $od< dod=a! !",+a%d - ,!"$#

VHDL a$d 5"*"d !,!!*,++.

EXPT NO:(-)DESIGN OF ENODER AND DEODER USING VERILOG



DATE:27.0?.2011

AIM:

To d!"#$ %& 'o#a *o $od a$d dod ,!"$# 5"+o#PROGRAM FOR ENODER USING VERILOG:

od,+ $od?(84)/"$',% C7:08/

o,%',% C2:0/o #1(C048C148C348C>48C7)/o #2(C148C248C348C48C7)/o #3(C248C48C>48C48C7)/

$dod,+

ENODER:

TRUTH TA9LE:

INPUTS OUTPUTS



;0 ;1 ;2 ;3 ; ;> ; ;7 A 9

1 0 0 0 0 0 0 0 0 0 0

0 1 0 0 0 0 0 0 0 0 1

0 0 1 0 0 0 0 0 0 1 0

0 0 0 1 0 0 0 0 0 1 1

0 0 0 0 1 0 0 0 1 0 0

0 0 0 0 0 1 0 0 1 0 1

0 0 0 0 0 0 1 0 1 1 0

0 0 0 0 0 0 0 1 1 1 1

OUTPUT:

PROGRAM FOR DEODER USING VERILOG:

od,+ dod(a4-4$4)/"$',% a4-/



"$',% $/o,%',% C3:0/=" 4d/$o% #1(4a)/

$o% #2(d4-)/a$d #3(C044d4$)/a$d #(C144-4$)/a$d #>(C24a4d4$)/a$d #(C34a4-4$)/

$dod,+

DEODER:

TRUTH TA9LE:



E A 9 D0 D1 D2 D3

0 0 0 0 0 0 0

1 0 0 1 0 0 0

1 0 1 0 1 0 0

1 1 0 0 0 1 0

1 1 1 0 0 0 1

OUTPUT:

RESULT:

T&,! %& 'o#a *o $od< dod=a! !",+a%d - ,!"$#5"+o# a$d 5"*"d !,!!*,++.EXPT NO:>(a)DESIGN OF D FLIP FLOP4 T FLIP FLOP4 FLIP FLOP AND SR

DATE:10.0.2011 FLIPFLOP USING VHDL



TRUTH TA9LE:

D Q Qn

0 X 01 X 1

OUTPUT:

PROGRAM FOR T FLIP FLOP USING VHDL:



+"-a "/,! ".!%d+o#"11.a++/,! ".!%d+o#"a"%&.a++/,! ".!%d+o#",$!"#$d.a++/

$%"% %** "! 'o%( %:"$ !%d+o#"/+4!%:"$ !%d+o#"/

J4J-a: "$o,% !%d+o#")/$d %**/a&"%%, -&a5"oa+ o* %** "!

-#"$ 'o!!(+) -#"$

"* !% K1K %&$J 6 K0K/J-a 6 K1K/+! "* +K5$% a$d + K1K %&$"* % K0K %&$J 6J/J-a 6 J-a/+!J 6 J-a/J-a 6 J/

$d "*/$d "* $d "*/$d 'o!!/$d -&a5"oa+/

TFLIP FLOP:

TRUTH TA9LE:



T Q Qnext Commen

t

0 0 0 Hold

state

0 1 1 Holdstate

1 0 1 Toggle

1 1 0 Toggle

OUTPUT:



PROGRAM FOR FLIP FLOP USING VHDL:

+"-a "/,! ".!%d+o#"11.a++/

,! ".!%d+o#"a"%&.a++/,! ".!%d+o#",$!"#$d.a++/$%"% ** "!

'o% ( + : "$ !%d+o#"/ : "$ !%d+o#"5%o(1 do=$%o 0)/

J4 J- : o,% !%d+o#")/$d **/

a&"%%, 9&a5"oa+ o* ** "! -#"$ 'o!!(+)

5a"a-+ %'14 %'2 : !%d+o#"/ -#"$"* "!"$#d#(+) %&$a! "!=&$ 01 %'1 :K0K/=&$ 10 %'1 :K1K/=&$ 00 %'1 : %'1/=&$ 11%'1 : $o% %'1/=&$ o%&! $,++/

$d a!/J6 %'1/%'2 : $o% %'1/J- 6 %'2/$d "*/$d 'o!! /$d 9&a5"oa+



FLIPFLOP:

TRUTH TA9LE:

J K Q Qn Comment

0 0 0 0 No Change

0 0 1 1 No Change

0 1 0 0 Reset

0 1 1 0 Reset

1 0 0 1 Set

1 0 1 1 Set

1 1 0 1 Toggle

1 1 1 0 Toggle

OUTPUT:

PROGRAM FOR SR FLIP FLOP USING VHDL:



+"-a "/,! ".!%d+o#"11.a++/,! ".!%d+o#"a"%&.a++/,! ".!%d+o#",$!"#$d.a++/

$%"% SR** "! 'o% ( +4 !4 : "$ !%d+o#"/

J : -,** !%d+o#")/$d SR**/

a&"%%, 9&a5"oa+ o* SR** "! -#"$ 'o!!( +) -#"$"* (+K5$% a$d + K1K) %&$

"* (!K0K a$d K0K)%&$ J6 J/+!"* (!K0K a$d K1K)%&$ J6 K0K/+!"* (!K1K a$d K0K)%&$ J6 K1K/+!"* (!K1K a$d K1K)%&$ J6 KK/$d "* /$d "*/$d 'o!! /$d 9&a5"oa+/

SR FLIPFLOP:



TRUTH TA9LE:

S R Q Qn Comment

0 0 0 0 No Change

0 0 1 1 No Change0 1 0 0 Reset

0 1 1 0 Reset

1 0 0 1 Set

1 0 1 1 Set

1 1 0 Z Indetermin

e

1 1 1 Z Indetermiin

e

OUTPUT:

RESULT:

T&,! %& 'o#a *o D*+"'*+o'4T*+"'*+o'4*+"'*+o'4SR*+"'*+o'

=a! !",+a%d - ,!"$# VHDL a$d 5"*"d !,!!*,++.



EXPT NO:>(-)DESIGN OF D FLIP FLOP4T FLIP FLOP4 FLIP FLOPAND

DATE:10.0.2011 SRFLIPFLOP USING VERILOG

AIM:

To d!"#$ %& 'o#a *o D F+"' F+o'4 T F+"' F+o'4 F+"' F+o' a$d SR

F+"' F+o' ,!"$# 5"+o#

PROGRAM FOR D FLIP FLOP USING VERILOG:

od,+ d** (J4d4+4+) /o,%',% J /"$',% d4+4+ /# J /a+=a! ('o!d# +)"* (+) J 0 /+! J d /$dod,+

DFLIPFLOP:



TRUTH TA9LE:

D Q Qn

0 X 0

1 X 1

OUTPUT:



PROGRAM FOR T FLIP FLOP USING VERILOG:

od,+ %** (J4%4+4+4!%) /o,%',% J /

"$',% %4+4+4!% /# J /a+=a! ('o!d# + o $#d# !%)"* (+) J 0 /+!a!!"#$ J %QJ /$dod,+.

T FLIPFLOP:

TRUTH TA9LE:

T Q Qnext Commen

t

0 0 0 Hold

state

0 1 1 Hold

state

1 0 1 Toggle

1 1 0 Toggle

OUTPUT:



PROGRAM FOR FLIP FLOP USING VERILOG:

od,+ **(4 +4 J4 J-)/"$',% C1:0/"$',% +/o,%',% J4 J-/# J4 J-/

a+=a!('o!d# +) -#"$

a! ()2Kd1:JJ/2Kd1:J0/2Kd2:J1/2Kd3:JJ/$da!J-J/

$d$dod,+

FLIPFLOP:



TRUTH TA9LE:

J K Q Qn Comment

0 0 0 0 No Change

0 0 1 1 No Change

0 1 0 0 Reset

0 1 1 0 Reset1 0 0 1 Set

1 0 1 1 Set

1 1 0 1 Toggle

1 1 1 0 Toggle

OUTPUT:



PROGRAM FOR SR FLIP FLOP USING VERILOG:

od,+ !**(!4 +4 J4 J-)/"$',% C1:0 !/"$',% +/

o,%',% J4 J-/# J4J-/

a+=a!('o!d# +) -#"$a! (!4)2Kd0 : J J/2Kd1 : J0/2Kd2 : J1/2Kd3 : JJ/$da!

J-J/$d$dod,+.

SR FLIPFLOP:

TRUTH TA9LE:

S R Q Qn Comment

0 0 0 0 No Change

0 0 1 1 No Change

0 1 0 0 Reset

0 1 1 0 Reset

1 0 0 1 Set

1 0 1 1 Set

1 1 0 Z Indetermin

e

1 1 1 Z Indetermiin

e



OUTPUT:

RESULT:

T&,! %& 'o#a *o D*+"'*+o'4T*+"'*+o'4*+"'*+o'4SR*+"'*+o'

=a! !",+a%d - ,!"$# VHDL a$d 5"*"d !,!!*,++.

EXPT NO:(a)DESIGN OF UPBDO@N S;NHRONOUS OUNTERUSING VHDL

DATE:2.0.2011



AIM:

To d!"#$ %& 'o#a *o UPBDO@N !$&o$o,! o,$% ,!"$# VHDL

PROGRAM FOR S;NHRONOUS UP OUNTER USING VHDL:

+"-a "/,! ".!%d+o#"11.a++/,! ".!%d+o#"a"%&.a++/,! ".!%d+o#",$!"#$d.a++/$%"% o,$% "!

'o%(+4 +: "$ !%d+o#"/J: o,% !%d+o#"5%o(3 do=$%o 0))/

$d o,$%/a&"%%, a&" o* o,$% "!!"#$a+ %': !%d+o#"5%o(3 do=$%o 0)/

-#"$ 'o!!(+4+) -#"$"*(+ K1K) %&$%' 6 0000/+! "* +K5$% a$d +K1K %&$%' 6 %'1/

$d "*/$d "*/$d 'o!!/J 6 %'/$d a&"/

S;NHRONOUS UP OUNTER:



TRUTH TA9LE:

L D 9 A

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

0 1 0 0

> 0 1 0 1

0 1 1 0

7 0 1 1 1? 1 0 0 0

1 0 0 1

10 1 0 1 0

11 1 0 1 1

12 1 1 0 0

13 1 1 0 1

1 1 1 1 0

1> 1 1 1 1

OUTPUT:

PROGRAM FOR S;NHRONOUS DO@N OUNTER USING VHDL:



+"-a "/,! ".!%d+o#"11.a++/,! ".!%d+o#"a"%&.a++/,! ".!%d+o#",$!"#$d.a++/$%"% o,$% "!

'o%(+4 +: "$ !%d+o#"/J: o,% !%d+o#"5%o(3 do=$%o 0))/

$d o,$%/a&"%%, a&" o* o,$% "!!"#$a+ %': !%d+o#"5%o(3 do=$%o 0)/

-#"$ 'o!!(+4+)

-#"$"*(+ K1K) %&$%' 6 1111/+! "* +K5$% a$d +K1K %&$%' 6 %'1/$d "*/$d "*/$d 'o!!/J 6 %'/$d a&"/

S;NHRONOUS DO@N OUNTER:

TRUTH TA9LE:



L D 9 A

0 1 1 1 1

1 1 1 1 0

2 1 1 0 1

3 1 1 0 0

1 0 1 1

> 1 0 1 0

1 0 0 1

7 1 0 0 0

? 0 1 1 1

0 1 1 0

10 0 1 0 1

11 0 1 0 0

12 0 0 1 1

13 0 0 1 0

1 0 0 0 11> 0 0 0 0

OUTPUT:

RESULT:T&,! %& 'o#a *o !$&o$o,! UPBDO@N o,$% !",+a%d

- ,!"$# VHDL od,+ a$d 5"*"d !,!!*,++.

EXPT NO: (-)DESIGN OF UPBDO@N S;NHRONOUS OUNTERUSING VERILOG



L D 9 A

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

0 1 0 0

> 0 1 0 1

0 1 1 0

7 0 1 1 1

? 1 0 0 0

1 0 0 1

10 1 0 1 0

11 1 0 1 1

12 1 1 0 0

13 1 1 0 11 1 1 1 0

1> 1 1 1 1

OUTPUT:

PROGRAM FOR S;NHRONOUS DO@N OUNTER USING VERILOG:



od,+ do=$o,$%(J4+4+)/o,%',% C3:0 J/"$',% +4 +/# C3:0 J/a+=a! ('o!d# +)

"* (+) -#"$J 6 K-1111 /$d+!

-#"$J 6 J 1/$d$dod,+

S;NHRONOUS DO@N OUNTER:

TRUTH TA9LE:



L D 9 A

0 1 1 1 1

1 1 1 1 0

2 1 1 0 1

3 1 1 0 0

1 0 1 1

> 1 0 1 0

1 0 0 1

7 1 0 0 0

? 0 1 1 1

0 1 1 0

10 0 1 0 1

11 0 1 0 0

12 0 0 1 1

13 0 0 1 0

1 0 0 0 1

1> 0 0 0 0

OUTPUT:

RESULT:T&,! %& 'o#a *o !$&o$o,! UPBDO@N o,$% !",+a%d

- ,!"$# 5"+o# od,+ a$d 5"*"d !,!!*,++.

EXPT NO:7(a)DESIGN OF 9IT RIPPLE OUNTERUSING VHDL



DATE:0?.10.2011

AIM:

To d!"#$ %& 'o#a *o -"% R"''+ o,$% ,!"$# VHDL

PROGRAM FOR 9IT RIPPLE OUNTER USING VHDL:

+"-a IEEE/

,! IEEE.STDLOGI11.ALL/

,! IEEE.STDLOGIARITH.ALL/

,! IEEE.STDLOGIUNSIGNED.ALL/$%"% o,$% "!

'o%(+4 + : "$ !%d+o#"/

J : o,% !%d+o#"5%o(3 do=$%o 0))/

$d o,$%/

a&"%%, a&" o* o,$% "!

!"#$a+ %': !%d+o#"5%o(3 do=$%o 0)/

-#"$

'o!! (+4 +)

-#"$"* (+K1K) %&$

%' 6 0000/

+!"* (+K5$% a$d +K1K) %&$

%' 6 %' 1/

$d "*/

$d 'o!!/

J 6 %'/

$d a&"/



9IT RIPPLE OUNTER:

TRUTH TA9LE:

L D 9 A

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

0 1 0 0

> 0 1 0 1

0 1 1 0

7 0 1 1 1? 1 0 0 0

1 0 0 1

10 1 0 1 0

11 1 0 1 1

12 1 1 0 0

13 1 1 0 1

1 1 1 1 0

1> 1 1 1 1



OUTPUT:

RESULT:T&,! %& 'o#a *o -"% "''+ o,$% =a! !",+a%d - ,!"$#

VHDL od,+ a$d 5"*"d !,!!*,++.

EXPT NO:7(-) DESIGN OF 9IT RIPPLE OUNTER USING VERILOG



DATE:0?.10.2011

AIM:

To d!"#$ %& 'o#a *o -"% "''+ o,$% ,!"$# 5"+o#

PROGRAM FOR 9IT RIPPLE OUNTER USING VERILOG:

od,+ o(J4+4+)/

"$',% +4+/

o,%',%C3:0J/

#C3:0J/

a+=a!('o!d# + o $#d# +)

-#"$"*(+)

J6K-0000/

+!

J6J1/

$d

$dod,+.

9IT RIPPLE OUNTER:

TRUTH TA9LE:



L D 9 A

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

0 1 0 0

> 0 1 0 1

0 1 1 0

7 0 1 1 1

? 1 0 0 0

1 0 0 1

10 1 0 1 0

11 1 0 1 1

12 1 1 0 0

13 1 1 0 11 1 1 1 0

1> 1 1 1 1

OUTPUT:

RESULT:T&,! %& 'o#a *o -"% "''+ o,$% =a! !",+a%d - ,!"$#

V"+o# od,+ a$d 5"*"d !,!!*,++.

EXPT NO:?(a) DESIGN OF RING OUNTER AND 9D OUNTER USING VHDL

DATE:1>.10.2011



AIM:

To d!"#$ %& 'o#a *o "$# o,$% a$d 9D o,$% ,!"$# VHDL

PROGRAM FOR RING OUNTER USING VHDL:

+"-a IEEE/



,! IEEE.STDLOGIUNSIGNED.ALL/

$%"% "$# "!

Po% ( +4!% : "$ STDLOGI/

J : o,% STDLOGIVETOR (3 do=$%o 0))/

$d "$#/

a&"%%, 9&a5"oa+ o* "$# "!

!"#$a+ #: !%d+o#"5%o(3 do=$%o 0)/

!"#$a+ $8%: !%d+o#"5%o(3 do=$%o 0)/

-#"$

'o!!(+4!%)

-#"$

"*(!%K1K) %&$

#6 (0 K1K4 o%&! K0K)/+!"*(+K5$% a$d +K1K) %&$

#6 $8%/

$d "*/

$d 'o!!/

$8%6 #(0) < #(3 do=$%o 1)/

J6 #/

$d 9&a5"oa+/

RING OUNTER :



TRUTH TA9LE:

L D 9 A

0 0 0 0 0

1 1 0 0 0

2 0 1 0 0

3 0 0 1 0

0 0 0 1

> 0 0 1 0

0 1 0 0

7 1 0 0 0

OUTPUT:

PROGRAM FOR 9D OUNTER USING VHDL:



+"-a IEEE/,! IEEE.STDLOGI11.ALL/,! IEEE.STDLOGIARITH.ALL/,! IEEE.STDLOGIUNSIGNED.ALL/ $%"% o,$%2VHDL "! 'o%( +o$a-+: "$ !%d+o#"/ +o: "$ !%d+o#"/ R!%: "$ !%d+o#"/ O,%',%: o,% !%d+o#"5%o(0 %o 3))/$d o,$%2VHDL/ a&"%%, 9&a5"oa+ o* o,$%2VHDL "! !"#$a+ %': !%d+o#"5%o(0 %o 3)/

-#"$ 'o!!(+o4R!%) -#"$ "* R!%K1K %&$ %' 6 0000/ +!"*(+oK5$% a$d +oK1K) %&$ "* +o$a-+K0K %&$ "* %'1001 %&$ %'60000/ +! %' 6 %' 1/ $d "*/ +!

%' 6 %'/ $d "*/ $d "*/ $d 'o!!/ O,%',% 6 %'/$d 9&a5"oa+/

9D OUNTER:



TRUTH TA9LE:L D 9 A

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

0 1 0 0

> 0 1 0 1

0 1 1 0

7 0 1 1 1

? 1 0 0 0 1 0 0 1

10 0 0 0 0

OUTPUT:

RESULT:

T&,! %& 'o#a *o "$# o,$% a$d 9D o,$% =a! !",+a%d

- ,!"$# VHDL a$d 5"*"d !,!!*,++.

EXPT NO:?(-)DESIGN OF RING OUNTER AND 9D OUNTER USING VERILOG



DATE:1>.10.2011

AIM:

To d!"#$ %& 'o#a *o "$# o,$% a$d 9D o,$% ,!"$# VHDL

PROGRAM FOR RING OUNTER USING VERILOG:

od,+ "$#(o,$%4+oad4"4+4+4a40)/

"$',% o,$%4+oad/

"$',% +4+/

"$',% C3:0"/

o,%',%C3:0a/o,%',% 0/

#C3:0a/

a!!"#$ 0o,$%<+oad<(aK-1111)/

a+=a!('o!d# + o $#d# +)

"*(+)

aK-0000/

+! "*(+oad)

a"/

+! "*(o,$%)

aa1K-1/

+!

aa/

$dod,+

RING OUNTER:

TRUTH TA9LE:



L D 9 A

0 0 0 0 0

1 1 0 0 02 0 1 0 0

3 0 0 1 0

0 0 0 1

> 0 0 1 0

0 1 0 0

7 1 0 0 0

OUTPUT:

PROGRAM FOR 9D OUNTER USING VERILOG:



od,+ -do,$%(+4+44-d14-d0)/

"$',% +4+4/

o,%',%C3:0-d14-d0/

#C3:0-d14-d0/

a+=a!('o!d# +) -#"$

"*(+)

-#"$

-d160/

-d060/

$d

+! "*()

"*(-d0K-1001)

-#"$

-d060/

"*(-d1K-1001)

-d160/

+!

-d16-d11/

$d

+!

-d06-d01/$d

$dod,+

9D OUNTER:



DATE:22.10.2011

AIM:

To d!"#$ %& 'o#a *o o&$!o$ o,$% ,!"$# VHDL

PROGRAM FOR OHNSON OUNTER USING VHDL:

+"-a IEEE/


,! IEEE.NUMERISTD.ALL/

$%"% o&$!o$o,$% "!

'o% (J : o,% ,$!"#$d(3 do=$%o 0)/ +4+ : "$ !%d+o#"/ )/

$d o&$!o$o,$%/

a&"%%, 9&a5"oa+ o* o&$!o$o,$% "!

!"#$a+ %' : ,$!"#$d(3 do=$%o 0):(o%&! K0K)/

-#"$

J 6 %'/

'o!!(+)

-#"$

"*( "!"$#d#(+) ) %&$

"* (+ K1K) %&$

%' 6 (o%&! K0K)/

+!

%'(1) 6 %'(0)/

%'(2) 6 %'(1)/

%'(3) 6 %'(2)/

%'(0) 6 $o% %'(3)/

$d "*/ $d "*/

$d 'o!!/

$d 9&a5"oa+/

OHNSON OUNTER:



TRUTH TA9LE:

L D 9 A

0 0 0 0 0

1 1 0 0 0

2 1 1 0 0

3 1 1 1 0

1 1 1 1

> 0 1 1 1

0 0 1 1

7 0 0 0 1

? 0 0 0 0

OUTPUT:

RESULT:

T&,! %& 'o#a *o o&$!o$ o,$% =a! !",+a%d - ,!"$#

VHDL od,+ a$d 5"*"d !,!!*,++.

EXPT NO:(-)DESIGN OF OHNSON OUNTER USING VERILOG



DATE:22.10.2011

AIM:

To d!"#$ %& 'o#a *o o&$!o$ o,$% ,!"$# 5"+o#

PROGRAM FOR OHNSON OUNTER USING VERILOG:

od,+ o&$!o$(o,$%4%o,$%4+4!%$)/

'aa% ="d%&0/

o,%',%C="d%&3:0o,$%/

o,%',% %o,$%/

"$',% +4 !%$/#C="d%&3:0o,$%/

# %o,$%/

a+=a!('o!d# + o $#d# !%$)

-#"$

"*(!%$)

-#"$

o,$%60/

%o,$%60/

$d +!

-#"$

o,$%6o,$%C="d%&:04o,$%C="d%&3/

%o,$%6(o,$%C="d%&31<o,$%C="d%&0)/

$d

$d

$dod,+

OHNSON OUNTER:



TRUTH TA9LE:

L D 9 A

0 0 0 0 0

1 1 0 0 0

2 1 1 0 0

3 1 1 1 0

1 1 1 1

> 0 1 1 1

0 0 1 1

7 0 0 0 1

? 0 0 0 0

OUTPUT:

RESULT:

T&,! %& 'o#a *o o&$!o$ o,$% =a! !",+a%d - ,!"$#

V"+o# od,+ a$d 5"*"d !,!!*,++.

EXPT NO:10(a)DESIGN OF 9IT SHIFT REGISTERUSING VHDL

DATE:0>.11.2011



AIM:

To d!"#$ %& 'o#a *o -"% !&"*% #"!% ,!"$# VHDL

PROGRAM FOR 9IT SHIFT REGISTER USING VHDL:

+"-a IEEE/



,! IEEE.STDLOGIUNSIGNED.ALL/

$%"% S&"*%#"!%VHDL "!

'o%( +o4 L4=: "$ !%d+o#"/

O,%',%: o,% !%d+o#"5%o(3 do=$%o 0)/

I$',%: "$ !%d+o#"5%o( 3 do=$%o 0))/

$d S&"*%#"!%VHDL/

a&"%%, 9&a5"oa+ o* S&"*%#"!%VHDL "!

!"#$a+ %': !%d+o#"5%o(3 do=$%o 0)/

-#"$

'o!!

-#"$

=a"% ,$%"+ +oK5$% a$d +oK1K/ "* LK1K %&$

%' 6 I$',%/

+!

*o " "$ 0 %o 2 +oo'

%'(") 6 %'("1)/

$d +oo'/ %'(3) 6 =/

$d "*/ $d 'o!!/

O,%',% 6 %'/

$d 9&a5"oa+/

9IT SHIFT REGISTER:



TRUTH TA9LE:

L INPUTS OUTPUTS

DA D9 D DD A 9 D

1 1 0 0 1 1 0 0 1

2 0 1 1 1 0 1 1 1

3 1 0 1 0 1 0 1 0

OUTPUT:

RESULT:

T&,! %& 'o#a *o -"% !&"*% #"!% =a! !",+a%d - ,!"$# VHDL

od,+ a$d 5"*"d !,!!*,++.

EXPT NO: 10(-)DESIGN OF 9IT SHIFT REGISTER USING VERILOG

DATE:0>.11.2011



AIM:

To d!"#$ %& 'o#a *o -"% !&"*% #"!% ,!"$# 5"+o#

PROGRAM FOR 9IT SHIFT REGISTER USING VERILOG:

od,+ !&"*%(4+4=4+4J)/

"$',%C3:0/

"$',% +4=4+/

o,%',% C3:0J/

# C3:0J/

a+=a!('o!d# +)

"*(+)

J6/

+!

-#"$

JC06JC1/

JC16JC2/

JC26JC3/

JC36=/

$d$dod,+

9IT SHIFT REGISTER:

TRUTH TA9LE:



L INPUTS OUTPUTS

DA D9 D DD A 9 D

1 1 0 0 1 1 0 0 1

2 0 1 1 1 0 1 1 1

3 1 0 1 0 1 0 1 0

OUTPUT:

RESULT:

T&,! %& 'o#a *o -"% !&"*% #"!% =a! !",+a%d - ,!"$# V"+o#

od,+ a$d 5"*"d !,!!*,++.

EXPT NO: 11DESIGN OF MULTIPLEXER USING TEST 9ENH USING VHDL

DATE:12.11.2011



AIM:

To d!"#$ %& 'o#a *o ,+%"'+8 ,!"$# %!% -$& ,!"$# VHDL

PROGRAM FOR MULTIPLEXER USING TEST 9ENH USING VHDL:

od,+ ,81(o,%4"04"14"24"34!14!0)/

o,%',% o,%/

"$',% "04"14"24"3/

"$',% !14!0/

=" !1$4!0$/

=" 0414243/

$o% (!1$4!1)/ $o% (!0$4!0)/

a$d (04"04!1$4!0$)/ a$d (14"14!1$4!0)/

a$d (24"24!14!0$)/

a$d (34"34!14!0)/

o (o,%40414243)/

$dod,+

od,+ !%",+,!/

# "$04"$14"$24"$3/ # !14!0/

=" o,%',%1/ ,81(o,%',%14"$04"$14"$24"$34!14!0)/"$"%"a+

-#"$

"$01/"$10/"$21/"$30/

W100d"!'+a

("$0Y-4"$1Y-4"$2Y-4"$3Y-B$4"$04"$14"$24"$3)/

!10/!00/

W100d"!'+a

(!1Y-4!0Y-4o,%',%1Y-B$4 !14!04o,%',%1)/

!10/!01/

W100d"!'+a

(!1Y-4!0Y-4o,%',%1Y-B$4 !14!04o,%',%1)/

!11/!00/

W100d"!'+a

(!1Y-4!0Y-4o,%',%1Y-B$4 !14!04o,%',%1)/

!11/!01/

W100d"!'+a

(!1Y-4!0Y-4o,%',%1Y-B$4 !14!04o,%',%1)/

$d



$dod,+

OUTPUT:

RESULT:

T&,! %& 'o#a *o ,+%"'+8 ,!"$# %!%-$& =a! !",+a%d -

,!"$# VHDL a$d 5"*"d !,!!*,++.

EXPT NO:12(a)DESIGN OF ALU USING VHDL

DATE:1.11.2011



AIM:

To d!"#$ %& 'o#a *o ALU ,!"$# VHDL

PROGRAM FOR ALU USING VHDL:

+"-a "/

,! ".!%d+o#"11.a++/

,! ".!%d+o#"a"%&.a++/

,! ".!%d+o#",$!"#$d.a++/

$%"% a+,1 "!

'o%(od:"$ !%d+o#"5%o(2 do=$%o 0)/

a:"$ !%d+o#"5%o(3 do=$%o 0)/

-:"$ !%d+o#"5%o(3 do=$%o 0)/

:o,% !%d+o#"5%o(3 do=$%o 0))/

$d a+,1/

a&"%%, -&a5"oa+ o* a+,1 "!

-#"$

'o!!(od4a4-)

-#"$

a! od "!=&$ 000

6 0000/

=&$ 001

6 a-/

=&$ 010

6 a-/

=&$ 011

6 a a$d -/

=&$ 101

6 $o% a/

=&$ 110

6 a $a$d -/

=&$ 111

6 a o -/

=&$ o%&!

6 1111/

$d a!/

$d 'o!!/



$d -&a5"oa+/

OUTPUT:

RESULT:

T&,! %& 'o#a *o ALU =a! !",+a%d - ,!"$# VHDL a$d 5"*"d

!,!!*,++.

EXPT NO:11(-) DESIGN OF ALU USING VERILOG

DATE:1.11.2011

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