xilinx spartan development kit user guide...2010/12/14 · jtag port miscellaneous /io sd card...

Xilinx

® Spartan

®-6 LX150T

Development Kit User Guide

Copyright © 2010 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. All other brands are property of their respective owners. Avnet Electronics Marketing 2 of 46 Rev D 1.2 12/14/2010

Table of Contents

1.0 Introduction ............................................................................................................................................................................... 5

1.1 Description ............................................................................................................................................................................ 5 1.2 Board Features ..................................................................................................................................................................... 5 1.3 Test Files .............................................................................................................................................................................. 5 1.4 Reference Designs ............................................................................................................................................................... 6 1.5 Ordering Information ............................................................................................................................................................. 6

2.0 Functional Description .............................................................................................................................................................. 7 2.1 Xilinx Spartan-6 LX150T FPGA ............................................................................................................................................ 8 2.2 GTP Interface ....................................................................................................................................................................... 8

2.2.1 GTP Reference Clock Inputs ............................................................................................................................................ 9 2.2.2 PCI Express x4 Add-in Card .......................................................................................................................................... 10 2.2.2.1 PCIe Configuration Timing ................................................................................................................................. 13 2.2.3 SFP Connector ............................................................................................................................................................... 13 2.2.4 GTP on FMC Expansion Connectors JX1 AND JX2 ...................................................................................................... 15 2.2.5 SATA Connector ............................................................................................................................................................ 16

2.3 Memory............................................................................................................................................................................... 16 2.3.1 DDR3 SDRAM Interface................................................................................................................................................. 16 2.3.2 Spansion Flash Interface................................................................................................................................................ 19 2.3.4 Platform Flash Interface ................................................................................................................................................. 20 2.3.5 SD Card Interface .......................................................................................................................................................... 20

2.4 Clock Sources .................................................................................................................................................................... 21 2.4.1 CDCM61002 Programmable LVDS Clock Synthesizer .................................................................................................. 23 2.4.1.1 CDCM61002 Clock Generation ................................................................................................................................. 24 2.4.1.2 CDCM61002 Programming Mode .............................................................................................................................. 24

2.5 Communication ................................................................................................................................................................... 24 2.5.1 10/100/1000 Ethernet PHY ............................................................................................................................................ 24 2.5.2 USB 2.0 ULPI PHY ........................................................................................................................................................ 27 2.5.3 RS232 ............................................................................................................................................................................ 28 2.5.4 USB-RS232 .................................................................................................................................................................... 29

2.6 User Switches ..................................................................................................................................................................... 29 2.7 User LEDs .......................................................................................................................................................................... 29 2.8 Configuration ...................................................................................................................................................................... 30

2.8.1 Configuration Modes ...................................................................................................................................................... 30 2.8.2 JTAG Chain .................................................................................................................................................................... 30

2.9 I2C Buses, Devices, and Interfaces .................................................................................................................................... 31 2.9.1 Real Time Clock ............................................................................................................................................................. 31 2.9.2 Temperature Sensor ...................................................................................................................................................... 32 2.9.3 ALI Interface (Avnet LCD Interface) ............................................................................................................................... 32 2.9.4 FPGA Mezzanine Card (FMC) Low Pin Count (LPC) Interface ...................................................................................... 32

2.10 Power ................................................................................................................................................................................. 33 2.10.1 FPGA I/O Voltage (VCCO) ........................................................................................................................................ 34 2.10.2 FPGA Reference Voltage (Vref) ................................................................................................................................ 35 2.10.3 GTP Voltage Regulators (AVCC, AVCCPLL, VTTRX, VTTTX, AVTTRCAL) ............................................................. 35

2.11 Thermal Management ........................................................................................................................................................ 35 2.12 Expansion Connectors ....................................................................................................................................................... 35

2.12.1 FMC Low Pin Count (LPC) Interface.......................................................................................................................... 35 3.0 Test Designs ........................................................................................................................................................................... 43

3.1 Factory Test ........................................................................................................................................................................ 43 3.2 Ethernet Test ...................................................................................................................................................................... 43

4.0 Revisions ................................................................................................................................................................................ 44 Appendix A ........................................................................................................................................................................................... 45


Figures

Figure 1 - Spartan-6 LX150T Development Board Picture ......................................................................................................................... 6 Figure 2 - Spartan-6 LX150T development board Block Diagram .............................................................................................................. 7 Figure 3 - GTP Ports on the Spartan-6 LX150T Development Board ......................................................................................................... 9 Figure 4 - GTP Clock Sources on the Spartan-6 LX150T development board ......................................................................................... 10 Figure 5 - PCI Express Reference Clock Conversion ............................................................................................................................... 11 Figure 6 - PCI Express x4 Interface ......................................................................................................................................................... 12 Figure 7 - SFP Module Interfaces ............................................................................................................................................................. 14 Figure 8 - Host Board Connector AMP 1367073-1 (photo taken from AMP Web Page) .......................................................................... 14 Figure 9 - DDR3 SDRAM Interface .......................................................................................................................................................... 16 Figure 10 - Flash Interface ....................................................................................................................................................................... 19 Figure 11 - S6LX150T Development Board Platform Flash Interface ....................................................................................................... 20 Figure 12 - Clock Nets Connected to Global Clock Inputs........................................................................................................................ 21 Figure 13 - CDCM61002 Clock Synthesizer ............................................................................................................................................. 23 Figure 14 - 10/100/1000 Mb/s Ethernet Interface ..................................................................................................................................... 25 Figure 15 - USB 2.0 ULPI PHY Interface.................................................................................................................................................. 27 Figure 16 - RS232 Interface ..................................................................................................................................................................... 28 Figure 17 - JTAG Chain on the Spartan-6 PCI Express Board ................................................................................................................. 30 Figure 18 - I2C Buses .............................................................................................................................................................................. 31 Figure 19 - ALI Interface ........................................................................................................................................................................... 32 Figure 20 - Board Power Supply .............................................................................................................................................................. 34 Figure 21 - FMC LPC Connector Pinout ................................................................................................................................................... 36 Figure 22 - FMC LPC Connector JX1 Block Diagram .............................................................................................................................. 37 Figure 23 - FMC LPC Connector JX2 Block Diagram .............................................................................................................................. 40 Figure 24 - Board Jumpers, Headers, Connectors ................................................................................................................................... 45 Figure 25 - FMC1_VIO ―JP8".................................................................................................................................................................... 45


Tables Table 1 - Ordering Information ................................................................................................................................................................... 6 Table 2 – XC6SLX150T FPGA Features .................................................................................................................................................... 8 Table 3 - Communications Standards Supported by the Spartan-6 GTP ................................................................................................... 8 Table 4 - GTP Placement Names ............................................................................................................................................................... 8 Table 5 – ICS874003-05 F_SEL Switch Settings ..................................................................................................................................... 11 Table 6 - GTP Pin Locations for PCI Express .......................................................................................................................................... 13 Table 7 - GTP Pin Locations for the SFP Interface .................................................................................................................................. 14 Table 8 - SFP Host Connector Pin Description ........................................................................................................................................ 15 Table 9 - FPGA Pin Locations for the SFP Interface ................................................................................................................................ 15 Table 10 - GTP Pin Assignments for FMC Connectors ............................................................................................................................ 15 Table 11 - GTP Pin Assignments for 10Gbps Media Connector .............................................................................................................. 16 Table 12 - FPGA Pin Locations for DDR3 SDRAM .................................................................................................................................. 18 Table 13 - Flash Interface Pin Locations .................................................................................................................................................. 19 Table 14 - SD Card Pin Locations ............................................................................................................................................................ 20 Table 15 - On-Board Clock Sources ......................................................................................................................................................... 22 Table 16 - Clock Socket "U25" Pin-out ..................................................................................................................................................... 22 Table 17 - User Clock Input Pin Locations ............................................................................................................................................... 22 Table 18 - CDCM61002 Clock Synthesizer Pin Description ..................................................................................................................... 23 Table 19 - CDCM61002 Common Application Settings ............................................................................................................................ 24 Table 20 - Ethernet PHY Hardware Strapping Options ............................................................................................................................ 26 Table 21 - Faceplate Ethernet PHY ―U4‖ Pin Locations ........................................................................................................................... 27 Table 22 - USB Interface Pin Locations.................................................................................................................................................... 28 Table 23 - RS232 Pin Locations ............................................................................................................................................................... 29 Table 24 – USB-to-RS232 Pin Locations ................................................................................................................................................. 29 Table 25 - Push Button Pin Locations ...................................................................................................................................................... 29 Table 26 - DIP Switch Pin Locations ........................................................................................................................................................ 29 Table 27 - LED Pin Locations ................................................................................................................................................................... 30 Table 28 - Setting the Configuration Mode ―JP2‖ ..................................................................................................................................... 30 Table 29 - Flying Lead JTAG Header ....................................................................................................................................................... 31 Table 30 - Real Time Clock Pin Locations................................................................................................................................................ 31 Table 31 - Temperature Sensor Pin Locations ......................................................................................................................................... 32 Table 32 - I/O Bank Voltages .................................................................................................................................................................. 34 Table 33 - Typical Current Measurements per MGT Tile.......................................................................................................................... 35 Table 34 - FMC LPC Connector Signals .................................................................................................................................................. 36 Table 35 - FMC LPC Connector JX1 Pin Locations ................................................................................................................................. 40 Table 36 - FMC LPC Connector JX2 Pin Locations ................................................................................................................................. 43


1.0 Introduction The purpose of this manual is to describe the functionality and contents of the Spartan-6 LX150T PCI Express Development Kit from Avnet Electronics Marketing. This document includes instructions for operating the board, descriptions of the hardware features and explanations of the test code programmed in the on-board PROM. For reference design documentation, see the PDF file included with the project files of the design.

1.1 Description

The Spartan-6 LX150T PCI Express Development Kit provides a complete hardware environment for designers to accelerate their time to market. The kit delivers a stable platform to develop and test designs targeted to the advanced Xilinx FPGA family. The installed Spartan-6 LX150T device offers a prototyping environment to effectively demonstrate the enhanced benefits of leading edge Xilinx FPGA solutions. Reference designs are included with the kit to exercise standard peripherals on the evaluation board for a quick start to device familiarization.

1.2 Board Features

FPGA

— Xilinx Spartan-6 XC6SLX150T-3FGG676C FPGA

I/O Connectors

— Two FMC LPC general-purpose I/O expansion connectors — One SD card connector — Avnet LCD Interface (ALI) connector

RocketIO™ GTP Transceiver Connectors

— One Small-Form Pluggable (SFP) cage — Two transceivers supplied on an FMC connectors for use by an expansion module — One PCI Express add-in card interface (4 lanes @ 2.5 Gbps) — One SATA host connector

Memory

— 128 MB DDR3 SDRAM components — 32 MB FLASH

Communication

— RS-232 serial port — USB 2.0 — USB-RS232 Port — 10/100/1000 Ethernet port

Power

— Regulated 5.0, 3.3, 2.5, 1.8, 1.5 and 1.2 V supply voltages derived from the PCI Express slot or an external 12 V supply

— SSTL2 Termination Regulators — Point of Load Regulators for MGT supply rails

Configuration

— XCF32 and XCF08 Platform Flash Configuration Flash — Xilinx Parallel Cable IV or Platform USB Cable support for JTAG Programming/Configuration

1.3 Test Files

The configuration PROM on the Spartan-6 LX150T development board comes programmed with a factory test example design. Additional test files that can be used to verify the functionality of the peripherals on the board can be found on the Avnet Electronics Marketing Design Resource Center (DRC) web site: www.em.avnet.com/drc. The test designs listed below are discussed in Section 3.0.

— Factory Test — Ethernet Test

http://www.em.avnet.com/drc


1.4 Reference Designs

Reference designs that demonstrate some of the potential applications of the Spartan-6 LX150T PCI Express Development Board can be downloaded from the Avnet Design Resource Center (www.em.avnet.com/drc). The reference designs include all of the source code and project files necessary to implement the designs. See the PDF document included with each reference design for a complete description of the design and detailed instructions for running a demonstration on the development board. Check the DRC periodically for updates and new designs.

Figure 1 - Spartan-6 LX150T Development Board Picture

1.5 Ordering Information

The following table lists the evaluation kit part numbers and available software options. Internet link at http://www.em.avnet.com/drc

Part Number Hardware

AES-S6DEV-LX150T-G Xilinx Spartan-6 LX150T Development Kit populated with an

XC6SLX150T FGG676C -3 speed grade device

Table 1 - Ordering Information




2.0 Functional Description A high-level block diagram of the Spartan-6 LX150T development board is shown below followed by a brief description of each sub-section.

Spartan-6

LX150T

FG676

FMC LPC Slot

( 76 I/O , 1 GTP)

Co

nn

ecto

r

RS 232 Port

( 2 I/O)

DIP Switches

( 8 I/O)

User LEDs

( 8 I/O)

10/100/ 1000 PHY

( 30 I/O)

USB-RS 232 Bridge

( 2 I/O)

Communication Ports

Push Switches

( 4 I/O)

JTAG Port

Miscellaneous I/O

SD Card Connector

( 6 I/O)

Memory Interfaces

128 MB DDR3 SDRAM

(x16)

GTP Interfaces

SFP Connector

( 1 GTP, 7 I/O)

PCI - Express x4

( 1 I/O , 4 GTPs)

FMC LPC Slot

( 73 I/O , 1 GTP )

Co

nn

ecto

r

USB 2. 0 PHY

( 13 I/O)

SATA Connector

( 1 GTP )

ALI Serial Connector

( Display, 20 I/O)

32 MB Flash

(x16, 47 I/O)

Temp Sensor

Real-Time Clock

( 3 I/O)

Voltage Regulators

3.3 V and 5.0 V

Regulators

2.5 V and 1.5 V

Regulators

1.2V

Regulator

0.75V

Regulator

12.0 V

Regulator

Clock Sources

Programmable

LVDS Clock Source

LVDS Clock Input

(SMA Connectors)

LVTTL OSC

@ 100 MHz

LVTTL OSC Socket

XCF32 P and

XCF08P

Figure 2 - Spartan-6 LX150T development board Block Diagram


2.1 Xilinx Spartan-6 LX150T FPGA

The Spartan-6 LX150T FPGA devices available in the FG676 package have four embedded memory controller blocks, one embedded PCI Express Endpoint Block and six Clock Management Tiles (each tile contains two DCMs and one PLL).

Device Number of

Slices BlockRAM

(Kb) DSP48A1

Slices GTP

Transceivers I/O Pins

XC6SLX150T 23,038 4,824 180 8 540

Table 2 – XC6SLX150T FPGA Features

The Spartan-6 LX150T PCI Express Development Board uses production silicon devices. The pin-out used for the PCI Express interface supports the Xilinx recommended pin-out for production silicon.

2.2 GTP Interface

The RocketIO™ GTP Transceiver is a full-duplex serial transceiver for point-to-point transmission applications. Up to 8 transceivers are available on a single Spartan-6 LX150T FPGA. The transceiver block is designed to operate at any serial bit rate in the range of 614 Mb/s to 3.125 Gb/s per channel , including the specific bit rates used by the communications standards listed in the following table. Only the -3 speed grade part is capable of 3.125 Gb/s. The -2 speed grade part is capable of 2.7 Gb/s. Multiple channels can be bonded together for increased data throughput. The data width of the FPGA fabric interface is programmable (one or two bytes) allowing the parallel data frequency to be tailored to the user application. The table below lists a sub-set of protocols supported by the Spartan-6 GTP.

Standards Channels (# of transceivers)

I/O Bit Rate (Gb/s)

PCI Express 1, 2, 4 2.5

SFI-5 1 2.488 – 3.125

OC-12 1 0.622

OC-48 1 2.488

Fibre Channel 1 1.06

2.12

Gigabit Ethernet 1 1.25

10-Gbit Fibre Channel 4 3.1875

Infiniband 1, 4 2.5

HD-SDI 1 1.485

1.4835

Serial ATA 1 1.5

3.0

Serial Rapid I/O 1, 4

1.25

2.5

3.125

Aurora (Xilinx protocol) 1, 2, 3, 4, … 0.100 – 3.75

Table 3 - Communications Standards Supported by the Spartan-6 GTP

The Spartan-6 LXT transceivers are grouped into tiles with two transceivers per tile. The two transceivers in each tile share a single PLL and other resources involving the reset and power control. A trailing number ‗0‘ or ‗1‘ is used to distinguish between the two transceivers in the tile. These transceiver tiles are physically located into a single column on the die. Each tile has a placement name associated to its X-Y coordinate on the die. For example, GTP_Dual_X0Y0 is the first tile in the column. The GTP_Dual placement name is used in the User Constraint File (UCF) to map specific tiles on the device to those instantiated in a HDL design.

GTP Interface

Lanes Number

S6LX150T

SATA 0 GTP_Dual_X0Y0

MGT245_1

SFP 0 GTP_Dual_X0Y0 MGT245_0

FMC1 - GTP_Dual_X1Y0 MGT267_0

FMC2 - GTP_Dual_X1Y0 MGT267_1

PCI Express 0,1 GTP_Dual_X0Y1 MGT101

2,3 GTP_Dual_X1Y1 MGT123

Table 4 - GTP Placement Names


The following figure shows the 8 RocketIO transceiver ports used on the Spartan-6 LX150T development board. The GTP tiles are depicted in their actual locations.

SPARTAN 6

LX150T

FPGA

GT

P1

23

TXPTXN

RXP

RXN

GT

P1

01

TXPTXN

RXP

RXN

TXPTXN

RXP

RXN

GT

P2

45

Ch

an

ne

l 0

TXPTXN

RXP

RXN

GT

P2

67

TXPTXN

RXP

RXN

PCIe

x4

SATA

SFP0

FMC1

and

FMC2

GT

P2

45

Ch

an

ne

l 1

Figure 3 - GTP Ports on the Spartan-6 LX150T Development Board

2.2.1 GTP Reference Clock Inputs

Each GTP_Dual tile has a reference clock input that can also be used by any adjacent dual tile. Several of these reference clock inputs are supplied by on-board clock sources while others are supplied externally. A single programmable LVDS synthesizer is used to provide variable clock sources to the dedicated GTP clock inputs. This synthesizer provides reference clock frequencies that support the full range of line rates. A dedicated pair of differential SMA connectors is connected to one of the GTP clock inputs. The SMA connector inputs are for user clocks generated by external test equipment or by the Spartan-6 itself on one of the SMA output connectors (requires SMA cables to make the connection). PCI Express applications use the 100 MHz reference clock provided over the card edge. The following figure shows the clock sources provided to the dedicated GTP clock inputs.


SPARTAN 6

GTPREFCLKP_101

GTPREFCLKN_101

GTPREFCLKP_123

GTPREFCLKN_123

GTPREFCLKP_245

GTPREFCLKN_245

GTPREFCLKP_245

GTPREFCLKN_245

ICS

87

40

03

-05

Jitte

r A

tte

nu

ato

r

PCIe_REFCLK_P

PCIe_REFCLK_N

REFCLK0_P

REFCLK0_N

REFCLK2_P

REFCLK2_N

SMA_REFCLK_P

SMA_REFCLK_N

CLKSYN0_REFCLK_P

CLKSYN0_REFCLK_N

Figure 4 - GTP Clock Sources on the Spartan-6 LX150T development board

2.2.2 PCI Express x4 Add-in Card

Four of the GTP transceivers are connected to the PCI Express card edge interface. PCI Express is an enhancement to the PCI architecture where the parallel bus has been replaced with a scalable, fully serial interface. The differences in the electrical interface are transparent to the software so existing PCI software implementations are compatible. Use of the Spartan-6 LX150T development board in a PCI Express application requires the implementation of the PCI Express protocol in the FPGA. The PCI Express Endpoint Block embedded in the Spartan-6 FPGA implements the PCI Express protocol and the physical layer interface to the GTP ports. This block must be instantiated in the user design. For more information, see the ―Spartan-6 FPGA Integrated Endpoint Block for PCI Express User Guide‖ on the Xilinx web site.

http://www.xilinx.com/support/documentation/ip_documentation/s6_pcie_ug654.pdf

The PCI Express electrical interface on the Spartan-6 LX150T development board consists of 4 lanes, each lane having a unidirectional transmit and receive differential pair. Each lane supports both first generation data rate of 2.5 Gbps. In addition to the 4 serial lanes there is a 100MHz reference clock that is provided from the system slot. In order to work in open systems, add-in cards must use the reference clock provided over the PCI Express card edge to be frequency locked with the host system.

To add clocking flexibility in the end user design Spartan-6 LX150T development board utilizes the on board ICS874003-05 jitter attenuator. This device provides a stable, low jitter reference clock that is programmable. See the figure below for an illustration of how the PCI Express reference clock is connected to the Spartan-6 LX150T FPGA.

http://www.xilinx.com/support/documentation/ip_documentation/s6_pcie_ug654.pdf


PCI Express Connector

PC

Ie L

ink

PC

Ie L

ink

+ -

ICS874003-05

Spartan-6 LXT

PCI Express

Endpoint

Device

PC

Ie L

ink

PC

Ie L

ink

+ -MGTs

+

-

100 MHz with SSC

PCI Express Clock

Programmable Reference Clock

PCI Express Add-In Card

Figure 5 - PCI Express Reference Clock Conversion

The ICS874003-05 device will provide a 100 MHz, 125 MHz, or 250 MHz reference clock to the PCI Express dedicated GTP_DUAL tiles with the proper F_SEL switch configuration. The F-SEL switch is SW8. Refer to the table below for the

proper switch configuration. This table assumes the QA0 and/or QA1 outputs are used for forwarding the reference clock to the Spartan-6 FPGA. See the IDT data sheet for switch settings regarding the QB outputs

SW8.1 SW8.2 SW8.3 PCI Express Mode of Operation ( QA0/QA1 Fout)

ON OFF ON PCI Express Reference Clock = 100MHz

OFF ON OFF PCI Express Reference Clock = 125MHz

OFF OFF OFF PCI Express Reference Clock = 250MHz

Table 5 – ICS874003-05 F_SEL Switch Settings

There is also a side band signal from the PCI Express card edge that connects to a regular I/O pin on the Spartan-6 FPGA. The ―PERST#‖ signal is an active low reset signal provided by the host PCI Express slot. The following figure shows the PCI Express interface to the Spartan-6 FPGA.


Spartan-6

LX150T

FPGA

MGT_DUAL

X0Y1

MGT101

PCI EXPRESS

x4 EDGE

CONNECTOR

PETp0PETn0

PERp0PERn0

PETp1PETn1

PERp1

PERn1

PETp03PETn3

PERp3PERn3

PETp2PETn2

PERp2PERn2

FPGA I/0

CREFCLKpCREFCLKn

CPERST#

MGT_DUAL

X1Y1

MGT123

1

x1 x4

JP1

PRSNT#

SELECT

2

Figure 6 - PCI Express x4 Interface

The lane width of the PCI Express interface is determined by the PRSNT1# and PRSNT2# connections. There are separate PRSNT2# pins for each of the lane options: one lane (x1) and four lanes (x4). These pins are pulled-up on the host motherboard. There is a single PRSNT1# pin that is pulled-low or tied to GND on the host motherboard. The add-in card connects the PRSNT1# pin to the PRSNT2# pin for the widest lane option in most applications, which effectively pulls the corresponding PRSNT2# pin low. This indicates to the host controller the lane width supported by the add-in card. The Spartan-6 LX150T development board provides the ability for the user to select the lane width by connecting the desired PRSNT2# pin with a jumper on JP1. See Appendix A for more information about the JP1 jumper settings.


The PCI Express transmit lanes are AC coupled (DC blocking capacitors are included in the signal path) on the development board as required by the PCI Express specification. The Spartan-6 LX150T development board takes advantage of the polarity inversion feature of the GTP transceivers. The ―P‖ and ―N‖ of the Lane 3 RX path are swapped on the board to improve the PCB routing. Each GTP has attributes that are used to enable polarity inversion on either the transmit or receive pairs, or both. The polarity inversion attributes are ―TXPOLARITY‖ for the transmit pairs and ―RXPOLARITY‖ for the receive pairs. Setting these attributes to a logic 1 enables the inversion.

GTP Instance Net Name Connector.pin# Spartan-6

pin# P/N Swapped?

GTP_Dual_X0Y1

PCIe_RX0P P4.B14 D7 No

PCIe_RX0N P4.B15 C7

PCIe_TX0P P4.A16 B6 No

PCIe_TX0N P4.A17 A6


PCIe_RX1N P4.B20 C9


PCIe_TX1N P4.A22 A8

GTP_Dual_X1Y1


PCIe_RX2N P4.B24 C17


PCIe_TX2N P4.A26 A18

PCIe_RX3P P4.B27 C19 Yes (RX)

PCIe_RX3N P4.B28 D19


PCIe_TX3N P4.A30 A20

Table 6 - GTP Pin Locations for PCI Express

2.2.2.1 PCIe Configuration Timing

The Spartan-6 LX150T PCI Express Development Board meets the 200 ms configuration time requirement for ATX based PC systems when configuring from the on boards PROMs. It should be noted that to meet this requirement the FPGA‘s USRCLK input must be used instead of the default FPGA_CCLK. The Spartan-6 USRCLK input is sourced by the 25 MHz clock oscillator U18 and is pin AC14 on the FPGA. Using this clock input for configuration renders approximately 166 ms for the FPGA to configure and be detected and enumerated on the system PCIe bus. A Bitgen option must be set for this input to be used. Use the following Bitgen switch to enable this USRCLK input to be the configuration clock:

- g ExtMasterCclk_en:yes 2.2.3 SFP Connector

One GTP transceiver is connected to a Small Form-factor Pluggable (SFP) interface which provides the ability to support optical links with the addition of optical transceiver modules (not included in the kit). The following figure shows a high-level block diagram of the SFP interface on the development board. This interface utilizes one channel of a GTP_Dual tile and a set of low-speed control signals to interface to the SFP module. One of the programmable LVDS synthesizers on the board is used to provide the reference clock. Alternately, a pair of differential SMA connectors can be used to provide the reference clock for the SFP interface The SFP interface on the Spartan-6 LX150T development board have been designed to support transceivers with transmission rates up to 3.75 Gbps operating over multimode or single mode fiber.


GbE

Sy

ste

m In

terf

ac

e

SFP Module Connector

P2

TD+

TD-

RD+

RD-

MOD-DEF(2)

MOD-DEF(1)

MOD-DEF(0)

Tx Disable

Rate Select

Tx Fault

LOS

SFP_TD1_P

SFP_TD1_N

SFP_RD1_P

SFP_RD1_N

SFP_TR1_LOS

SFP_TR1_ MODDEF0

SFP_TR1_ MODDEF1

SFP_TR1_ MODDEF2

SFP_TR1_ RATESELECT

SFP_TR1_ TXDISABLE

SFP_TR1_ TXFAULTF

PG

A I/

O

MGTRXP0

MGTRXN0

MGTTXP0

MGTTXN0

1/2

GT

X_

Du

al_

X0

Y0

J2

P2 EnableSpartan-6

LX150T

FG676

Figure 7 - SFP Module Interfaces

The SFP connector includes a Host Board Connector, and top and bottom EMI cage. The Host Connector is directly connected or DC coupled to the GTP port. SFP compliant modules include AC coupling capacitors in the modules for both transmit and receive signal paths so the AC coupling internal to the Spartan-6 LXT GTP receiver may be bypassed (RXDCCOUPLE = TRUE). MGT245 transceiver 0 is connected to the SFP host connector labeled ―P2‖ as indicated in the previous figure.


pin# P/N Swapped?

GTP_Dual_X0Y0

SFP0_RXN P3.12 AD8 No

SFP0_RXP P3.13 AC8

SFP0_TXP P3.18 AE7 No

SFP0_TXN P3.19 AF7

Table 7 - GTP Pin Locations for the SFP Interface

SFP modules connect to the board via the Host Board Connector defined in the SFP Multi-Source Agreement (MSA). This 20-pin connector provides connections for power, ground, high-speed serial data, and the low-speed control signals for controlling the operation of the SFP module. The following figure shows the host connector used on the Spartan-6 LX150T development board.

Figure 8 - Host Board Connector AMP 1367073-1 (photo taken from AMP Web Page)


The following table lists the Host Board Connector pin assignments and provides a brief description of each signal.

Pin Number Name Function

1 VEET Transmitter Ground

2 Tx Fault Transmitter Fault Indication

3 Tx Disable Transmitter Disable

4 MOD-DEF(2) Module Definition 2 (Serial Interface Data Line)

5 MOD-DEF(1) Module Definition 1 (Serial Interface Clock Line)

6 MOD-DEF(0) Module Definition 0 (Module Present Signals, active low)

7 Rate Select Not Connected

8 LOS Loss of Signal

9 VEER Receiver Ground



12 RD- Inverse Received Data Out

13 RD+ Received Data Out


15 VCCR Receiver Power

16 VCCT Transmitter Power


18 TD+ Transmitter Data In

19 TD- Inverse Transmitter Data In


Table 8 - SFP Host Connector Pin Description

The following table lists the FPGA I/O assignments for the SFP interface.

Net Name Spartan-6 Pin#

SFP #0

SFP0_LOS C24

SFP0_MOD0 D23

SFP0_MOD1 K19

SFP0_MOD2 K18

SFP0_RSEL J23

SFP0_TX_DISABLE A25

SFP0_TX_FAULT B24

Table 9 - FPGA Pin Locations for the SFP Interface

2.2.4 GTP on FMC Expansion Connectors JX1 AND JX2

Two GTP transceivers are brought out to the board-to-board connectors labeled ―JX1‖ and ―JX2‖ on the board for use by FMC daughter cards. The MGT267 transceiver is directly connected to JX1 and JX2 pins C6 and C7 (RX+ and RX-) and pins C2 and C3 (TX+ and TX-). The user must evaluate whether AC coupling is required on the daughter card to safely interface with the Spartan-6 GTP transceiver. The MGT267 tile is GTP_Dual ―X1Y0‖ in the LX150T device.


pin# P/N Swapped?

GTP_Dual_X1Y0

FMC1_C_DP0_C2M_p JX1.C2 AE19 No

FMC1_C_DP0_C2M_n JX1.C3 AF19

FMC1_C_DP0_M2C_p JX1.C6 AC18 No

FMC1_C_DP0_M2C_n JX1.C7 AD18

FMC2_C_DP0_C2M_p JX2.C2 AE21 No

FMC2_C_DP0_C2M_n JX2.C3 AF21

FMC_C_DP0_M2C_p JX2.C6 AC20 No

FMC2_C_DP0_M2C_n JX2.C7 AD20

Table 10 - GTP Pin Assignments for FMC Connectors


2.2.5 SATA Connector

One GTP transceiver is connected to a Serial ATA host connector that can be used to connect an I/O device such as a hard drive to the board. Only the signal connector is present on the Spartan-6 LX150T development board. Power for the Serial ATA peripheral must be supplied externally. MGT245 transceiver #1 is connected to the vertical cable-to-board connector labeled J3. The connector is keyed to ensure the correct polarity. The MGT245 tile is GTP_Dual ―X0Y0‖ in the LX150T

device.


pin# P/N Swapped?

LX50T/SX50T: GTP_Dual_X0Y5 LX110T/SX95T: GTP_Dual_X0Y6

SATA_TXP J3.2 AE9 No

SATA_TXN J3.3 AF9

SATA_RXN J3.5 AD10 No

SATA_RXP J3.6 AC10

Table 11 - GTP Pin Assignments for 10Gbps Media Connector

2.3 Memory

The Spartan-6 LX150T development board is populated with both high-speed RAM and non-volatile ROM to support various types of applications. Each development board has three memory interfaces: 1) 128 MB DDR3 SDRAM, 2) 32 MB non-volatile flash, and 3) 32 Mb + 8 Mb (daisy chained) Xilinx Platform XCF configuration flash.

2.3.1 DDR3 SDRAM Interface

A single Micron DDR3 SDRAM device, part number MT41J64M16LA-187E:B, make up the 16-bit data bus. The device provides 128 MB of memory on a single IC and is organized as 8 Megabits x 16 x 8 banks (1Gb). The Spartan-6 LX150T development board can support larger devices with addressing support for up to 128MB (two 512-Megabit devices). The device has an operating voltage of 1.5 V and the interface is JEDEC Standard SSTL_15 (Class I for unidirectional signals, Class II for bidirectional signals). The -187E speed grade supports 1.87 ns cycle times with a 7 clock read latency (DDR3-1066). The following figure shows a high-level block diagram of the DDR3 SDRAM interface on the development board.

Spartan-6

LX150T

Bank 4

Memory

Controller

64M x 16

DDR3

Data[15:0]

BA[1:0]

Addr[12:0]

UDQM

LDQM

UDQS

UDQS_n

LDQS

LDQS_n

CS_n

RAS_n

CAS_n

WE_n

CLKE

CLK

CLK_n

ODT

RESET_n

Figure 9 - DDR3 SDRAM Interface


The DDR3 signals are connected to I/O Bank 4 of the Spartan-6 LXT FPGA. The supply pins (VCCO) for the DDR3 bank (Bank 4) is connected to 1.5 Volts. This supply rail can be measured at the test point labeled 1.5 V. The reference voltage pins (VREF) for the DDR3 bank is connected to the reference output of the National Semiconductor LP2998 1.5 amp LDO. This device provides the supply voltage and reference voltage necessary for the SSTL_15 I/O standard. The termination voltage is 0.75 Volts and can be measured at the test point labeled DDR_TERM_0.75V. The LP2998 also supplies the DDR3 termination voltage of 0.75 V and can be measured at the test point labeled DDR_TERM_0.75V.

The following guidelines were used in the design of the DDR3 interface to the Spartan-6 LXT FPGA. These guidelines are based on Micron recommendations and board level simulation.

50 ohm* controlled trace impedance

Dedicated data bus with matched trace lengths (+/- 50 mils)

Memory clocks and data strobes routed differentially

Parallel termination following the memory device connection on shared signals (control, address)

50 ohm* pull-up resistor to the termination supply (0.75V) on clock signals

Termination supply that can both source and sink current

* Ideal impedance values. Actual may vary.

All DDR3 signals are compliant to the Xilinx recommended and MIG generated pin out.


The following table contains the FPGA pin numbers for the DDR3 SDRAM interface.

NET NAME SPARTAN-6 PIN

NET NAME SPARTAN-6 PIN

DDR3_A0 L7 DDR3_D0 H3

DDR3_A1 L6 DDR3_D1 H1

DDR3_A2 K10 DDR3_D2 G2

DDR3_A3 M8 DDR3_D3 G1

DDR3_A4 J7 DDR3_D4 D3

DDR3_A5 L4 DDR3_D5 D1

DDR3_A6 L3 DDR3_D6 E2

DDR3_A7 L10 DDR3_D7 E1

DDR3_A8 C2 DDR3_D8 J2

DDR3_A9 C1 DDR3_D9 J1

DDR3_A10 J9 DDR3_D10 K3

DDR3_A11 E3 DDR3_D11 K1

DDR3_A12 K8 DDR3_D12 M3

DDR3_D13 M1

DDR3_BA0 B2 DDR3_D14 N2

DDR3_BA1 B1 DDR3_D15 N1

DDR3_BA2 G3

DDR3_UDM0 J4

DDR3_CS# DDR3_LDM0 J3

DDR3_ODT M6

DDR3_RST# E4

DDR3_WE# G4

DDR3_RAS# L9 DDR3_UDQS0 L2

DDR3_CAS# L8 DDR3_UDQS0# L1

DDR3_CLKE K9 DDR3_LDQS0 F3

DDR3_CLK0 K5 DDR3_LDQS0# F1

DDR3_CLK0# J5

Table 12 - FPGA Pin Locations for DDR3 SDRAM


2.3.2 Spansion Flash Interface

The Flash memory consists of a single 32 MB Spansion S29GL-P device in a 64 ball BGA package, part number S29GL256P11FFIV10. The S29GL-P device is an asynchronous memory that also supports a synchronous-burst read mode

for high-performance applications. The S29GL-P device has a 110 nanosecond access time. The S29GL-P flash connects to pins in Banks 1 and 2 of the Spartan-6 FPGA. The Flash I/O voltage (VIO) is set to 2.5 V to match the VCCO voltage of Banks 1 and 2. The following figure shows a high-level block diagram of the S29GL-P flash interface on the development board.

Flash

Addr [24:0]

Data [15:0]

RST#BYTE#

CE#

OE#WE#

WP#

GND

JP3

1

VCC

3 3V

A[22:0]

D[15:0]

Spartan-6

2.5V

VIO

2.5V

Figure 10 - Flash Interface

The following table contains the FPGA pin numbers for the Flash interface.

Net Name Spartan-6 pin# Net Name Spartan-6 pin#

FLASH_A0 N17 FLASH_D0 AD23

FLASH_A1 V26 FLASH_D1 V18

FLASH_A2 V24 FLASH_D2 W19

FLASH_A3 T26 FLASH_D3 AD6

FLASH_A4 T24 FLASH_D4 AF6

FLASH_A5 R24 FLASH_D5 W8

FLASH_A6 R23 FLASH_D6 W7

FLASH_A7 P26 FLASH_D7 AA10

FLASH_A8 P24 FLASH_D8 AF3

FLASH_A9 R21 FLASH_D9 AA11

FLASH_A10 R20 FLASH_D10 N18

FLASH_A11 P22 FLASH_D11 AD5

FLASH_A12 P21 FLASH_D12 Y20

FLASH_A13 R19 FLASH_D13 AF22

FLASH_A14 R18 FLASH_D14

FLASH_A15 N24 FLASH_D15

FLASH_A16 N23

FLASH_A17 P19 FLASH_CE# AB9

FLASH_A18 P17 FLASH_WE# AA25

FLASH_A19 N22 FLASH_OE# W26

FLASH_A20 N21 FLASH_RST# AA9

FLASH_A21 N20 FLASH_BYTE# AA26

FLASH_A22 N19

FLASH_A23 L24

FLASH_A24 L23

FLASH_A25 NC

Table 13 - Flash Interface Pin Locations


2.3.4 Platform Flash Interface

The Spartan-6 LX150T development board utilizes on-board Xilinx Platform Flash XCF devices to configure the FPGA quickly using Select Map modes. When configuring the FPGA, the flash clock is sourced by the FPGA CCLK pin. To speed up configuration times for PCI Express applications a 25MHz User Clock is connected to the USERCCLK input in Bank 2. If the USERCCLK is not used to configure the Spartan-6 FPGA for PCI Express applications the board will not be recognized on the bus at the time the host PC powers up and enumerates the PCI Express bus.

Note: The Bitgen option “-g ExtMasterCclk_en:yes” must be set in order for the FPGA to use the USERCCLK

input as the configuration clock. Note: The S6LX150T development board’s reconfiguration circuit is not functional on Revision C hardware. Pressing the PROG button (SW1) will NOT reconfigure the FPGA. The PROG_B signal that is supposed to be connected to the XCF32P device as shown in the figure below was not implemented properly on revision C hardware. The diagram below is correct and can be used as reference to show how the devices should be connected. Hardware revisions after revision C have this error corrected.

D[0:7]

Spartan-6

FPGA

DONE

CLK

CEn

CCLK

D[0:7]

INIT_B OE/RESETn

PROG_B CFn

BUSYBUSY

RDWR_B

CSI_B

XCF32P

D[0:7]

CLK

CEn

OE/RESETn

CFn

BUSY

XCF08P

CEOn

CCLK

D[0:7]

INIT_B

PROG_B

BUSY

M1

M0Ju

mp

ers

Figure 11 - S6LX150T Development Board Platform Flash Interface

2.3.5 SD Card Interface

The Spartan-6 LX150T development board has an on-board SD Card connector. The part number for the connector used is a Hirose PN: 609_0003_5. Below is a table that shows how the SD Card connector interfaces to the FPGA.

Signal Name Spartan-6 FPGA pin #

SD1_CLK V5

SD1_CMD T6

SD1_D0 W5

SD1_D1 U9

SD1_D2 U8

SD1_D3 U7

Table 14 - SD Card Pin Locations


2.4 Clock Sources

The Spartan-6 LX150T development board includes all of the necessary clocks on the board to implement high-speed logic and RocketIO transceiver designs as well as providing the flexibility for the user to supply their own application specific clocks. The clock sources described in this section are used to derive the required clocks for the memory and communications devices, and the general system clocks for the logic design. This section also provides information on how to supply external user clocks to the FPGA via the on-board connectors and oscillator socket. For a description of the GTP reference clock sources, see Section 2.2.1.

The following figure shows the clock nets connected to the I/O banks containing the global clock input pins on the Spartan-6 LX150T FPGA. Fifteen out of the sixteen global clock inputs of the Spartan-6 FPGA are utilized on the board. However the majority of these inputs are for expansion clocks and user inputs. It should be noted that single-ended clock inputs must be connected to the P-side of the pin pair because a direct connection to the global clock tree only exists on this pin. The I/O voltages (VCCO) for the one of the FPGA banks containing the global clock input pins (Banks 0) is jumper selectable to either 2.5 V or 3.3 V. In order to use the differential clock inputs as LVDS inputs, the VCCO voltage for Bank 0 must be set for 2.5 V since the Spartan-6 FPGA does not support 3.3 V differential signaling. Single-ended clock inputs do not have this restriction and may be either 2.5 V or 3.3 V. Setting the voltage selection jumper to 2.5 V (default condition) enables the board to support both single-ended and differential clock inputs.

Spartan-6™ FG676

Bank 0

LVTTL OSC

@100 MHz

GMII ClocksExpansion Clocks

FM

C1-

CL

K0-

M2C

_P

FM

C1-

CL

K0-

M2C

_N

Expansion Clocks

GM

II_F

P_T

X_C

LK

GB

E_F

P_M

CL

K

FMC1_VIO

2.5V

3.3V

JP8

GM

II_F

P_R

X_C

LK

FP

GA

-US

ER

CC

LK

US

B IF

CL

K

Bank 1

Bank 2 Bank 3

FM

C1-

CL

K1-

M2C

_P

FM

C1-

CL

K1-

M2C

_N

FM

C1-

LA

17-C

C_P

FM

C1-

LA

17-C

C_N

FM

C1-

LA

00-C

C_P

FM

C1-

LA

00-C

C_N LVTTL OSC

Socket

FM

C1-

LA

18-C

C_P

FM

C1-

LA

18-C

C_N

FM

C1-

LA

25_P

FM

C1-

LA

25_N

FM

C2-

CL

K0-

M2C

_P

FM

C2-

CL

K0-

M2C

_N

FM

C2-

LA

00-C

C_P

FM

C2-

LA

00-C

C_N

FM

C2-

CL

K1-

M2C

_P

FM

C2-

CL

K1-

M2C

_N

Figure 12 - Clock Nets Connected to Global Clock Inputs


The on-board 100MHz oscillator provides the system clock input to the global clock tree. This single-ended, 100 MHz clock can be used in conjunction with the Spartan-6 Clock Management Tiles (CMTs) to generate the various logic clocks and the clocks forwarded to the DDR3 SDRAM devices. The interface clocks supplied by the communications devices are derived from dedicated crystal oscillators.

Additionally, there is an on-board TI CDCM61002 LVDS clock synthesizer that is connected to GTP_Dual tile X0Y0 to give the user the ability to source that and adjacent tiles with a wide range of frequencies. SMA connectors are also attached to one of the two outputs of these devices so that the user can utilize the clock source off-board if needed. The CDCM61002 clock synthesizer is explained in detail in Section 2.4.1.

Reference# Frequency Derived Interface Clock Derived

Frequency Spartan-6pin#

U23 100 MHz CLK_100MHZ 100 MHz U23

U25 User Defined CLK_SOCKET User Defined R25

Y1 19.2 MHz USB_CLKOUT 30, 48 MHz R2

U18 25 MHz

CLK_SYN0_P

21.25 – 1360 MHz

AE11 (GTP X0Y0)

CLK_SYN0_N AF11 (GTP X0Y0)

CLKSYN_SMA_P (J14) --

CLKSYN_SMA_N (J15) --

U6 25 MHz

GMII_FP_RX_CLK 2.5, 25, 125 MHz V4

GMII_FP_TX_CLK 125 MHz R7

GBE_FP_MCLK 125 MHz T3

Table 15 - On-Board Clock Sources

In addition to the 100 MHz oscillator, an 8-pin DIP clock socket is provided on the board so the user can supply their own oscillator of choice. The socket is a single-ended, LVTTL or LVCMOS compatible clock input to the FPGA that can be used as an alternate source for the system clock.

Signal Name Socket pin#

Enable 1

GND 4

Output 5

VDD 8

Table 16 - Clock Socket "U25" Pin-out

There is one pair of SMA connectors for user supplied differential clocks. The SMA pair is routed differentially and connected to dedicated GTP clock input pins to provide a reference clock to the transceivers as shown in Figure 4 in Section 2.2.1. The reference designators for these connectors are ―J12‖ and ―J13‖. The silk screen labels indicate the polarity of the inputs with a trailing minus sign for the N pin and a positive sign for the P pin. These differential clock inputs are AC coupled to the Spartan-6 MGTREFCLK_245 pins.

Net Name Input Type Connector.pin# Spartan-6

pin#

MGT_REFCLK_P GTP Clock

J12.1 AC12

MGT_REFCLK_N J13.1 AD12

Table 17 - User Clock Input Pin Locations


2.4.1 CDCM61002 Programmable LVDS Clock Synthesizer

The Spartan-6 LX150T PCI Express Development Board design uses the TI CDCM61002 LVDS frequency synthesizer for generating various clock frequencies. A list of features included in the CDCM61002 device is shown below.

Output frequency range: 43.75 MHz to 683.264 MHz

RMS period jitter: 0.509 ps @ 625 MHz

Output rise and fall time: 255 ps (maximum)

Output duty cycle: varies dependant on output frequency

The following figure shows a high-level block diagram of the CDCM61002 programmable clock synthesizer. Inputs OS0 and OS1 are hard wired to use the LVDS mode of the CDCM61002 device.

Design Note: The CDCM61002 is sourced by a 25 MHz clock oscillator U18. This clock output is also connected to the Spartan-6 LX150T USERCCLK input to decrease configuration times.

CDCM61002

U19

PR[1:0]

OD[2:0]

PR

OD

OS0

OS1

3.3V

OUT0_P

OUT0_N

OUT1_P

OUT1_N

SMA

Connectors

CLK_SYN0_P

CLK_SYN0_N

SW9

SW10

CE

RST_N

U18

XIN

25MHzUSERCCLK

GTP_245

Figure 13 - CDCM61002 Clock Synthesizer

Signal Name Direction Pull up/Pull down Description

PR[1:0] Input Pull up Prescaler and Feedback divider control pins.

OD[2:0] Input Pull up Output divider control pins.

OS[1:0] Input Pull up Output type select control pins.

CE Input Pull up Chip enable.

RST_N Input Pull up Device reset (active low).

XIN Input Pull up Parallel resonant crystal/LVCMOS input.

OUT0 P/N Input Differential output pair.

OUT1 P/N Input Differential output pair.

Table 18 - CDCM61002 Clock Synthesizer Pin Description


2.4.1.1 CDCM61002 Clock Generation

The CDCM610024 output clocks are generated based on the following formula (assuming the crystal clock input is 25 MHz):

FOUT = (FIN) (FD) / OD

Equation Variables:

FOUT = Output Frequency

FIN = Clock Input Frequency

FD = Feedback Divider Value

OD = Output Divider Value

Please refer to the CDCM61002 datasheet for detailed tables regarding the Feedback Divider and Output Divider values. The CDCM61002 FD and OD values are programmed via dipswitches SW9 and SW10. These dipswitches should be configured prior to powering up the board.

The following table shows how to set the dipswitches for a common application. All the values are based on a 25 MHz crystal clock input to the CDCM61002 device.

Interconnect Technology

OUT0 and

OUT1 (MHz)

PR1 PR0 OD2 OD1 OD0

SATA 150 0 0 0 1 1

GigE 125 1 1 0 1 1

10 GigE 156.25 1 0 0 1 1

12 GigE 187.5 0 1 0 0 1

Table 19 - CDCM61002 Common Application Settings

2.4.1.2 CDCM61002 Programming Mode

The Spartan-6 LX150T PCI Express Development Board allows programming of the PR and OD values in parallel mode. This is the only mode allowed by the device. In parallel mode, PR and OD values are programmed into the device upon the release of the master reset signal (rising edge of the MR_N signal). The switches should be set into the correct position prior to turning on power to the board. Should the switch settings change after power up the board will have to be power cycled to reset the device.

2.5 Communication

The Spartan-6 LXT FPGA has access to Ethernet, USB and RS232 physical layer transceivers for communication purposes. Network access is provided by a single 10/100/1000 Mb/s Ethernet PHY device, which is connected to the Spartan-6 via a standard GMII interface. The PHY device connects to the outside world with a standard RJ45 connector. The connector is located on the PCI faceplate. General purpose I/O transfers are supported by way of the USB 2.0 port. The USB Type Mini-B peripheral connector on the faceplate facilitates communication with the board while enclosed in a PC case. Serial port communication to the embedded PowerPC processor or FPGA fabric is provided through a dual-channel RS232 transceiver. An alternate Cypress CP2102 USB-RS232 transceiver is also implemented on the Spartan-6 LX150T PCI Express Development Board. 2.5.1 10/100/1000 Ethernet PHY

The PHY device is a National DP83865DVH Gig PHYTER® V. The DP83865 is a low power version of National‘s Gig PHYTER V with a 1.8 V core voltage and a selectable I/O voltage (2.5 V or 3.3 V). The PHY is connected to a Tyco RJ-45 jack with integrated magnetics (part number: 1-6605833-1). The jack also integrates two LEDs and their corresponding resistors as well as several other passive components. External logic is used to logically OR the three link indicators for 10, 100 and 1000 Mb/s to drive a Link LED on the RJ-45 jack. The external logic is for the default strap options and may not work if the strap options are changed. Four more LEDs are provided on the board for status indication. These LEDs indicate Link at 10 Mb/s, Link at 100 Mb/s, link at 1000 Mb/s and Full Duplex operation. The PHY clock is generated from a 25 MHz clock oscillator. The following figure shows a high-level block diagram of the interface to the DP83865 Tri-mode Ethernet PHY.


data_tx[7:0]

clk_tx

control_tx

data_rx[7:0]

clk_rx

control_rx

25MHz

OSC

National DP83865

10/100/ 1000 PHYSpartan- 6 FPGA

phy_ reset

Tra

ns

mit

Rec

eiv

e

10/1

00/1

000

Mag

neti

cs

RJ

45

Co

nn

ecto

r

MDIA_P

MDIA_N

LEDs

MDIB_P

MDIB_N

MDIC_P

MDIC_N

MDID_P

MDID_N

gtxclk

Figure 14 - 10/100/1000 Mb/s Ethernet Interface

The PHY device has the address 0b00001 by default. PHY address 0b00000 is reserved for a test mode and should not be used. Three-pad resistor jumpers are used to set the strapping options. These jumper pads provide the user with the ability to change the settings by moving the resistors. The strapping options used for the PHY device are shown in the following table. The dual-function pins that are used for both a strapping option and to drive an LED, have a set of two jumpers per pin. The dual-function pins are indicated by an asterisk in the table.


Function

Jumper Installation

Resistor Mode Enabled

Faceplate (U4)

Auto-Negotiation*

JT9: pins 1-2 JT10: pins 1-2

0 ohm 0 ohm

Auto-negotiation enabled (default)


0 ohm 0 ohm

Auto-negotiation disabled

Full/Half Duplex*


0 ohm 0 ohm

Full Duplex (default)


0 ohm 0 ohm

Half Duplex

Speed 1*


(Speed1 – 0)

0 ohm 0 ohm

Speed Selection: (Auto-Neg enabled) Speed1 Speed0 Speed Advertised 1 1 1000BASE-T, 10BASE-T 1 0 1000BASE-T 0 1 1000BASE-T, 100BASE-TX 0 0 1000BASE-T, 100BASE-TX, 10BASE-T Default: 1000BASE-T, 100BASE-TX, 10BASE-T

Speed 0*


(Speed0 – 0)

0 ohm 0 ohm

PHY address 0*


0 ohm 0 ohm

PHY Address 0b00001 (default)


0 ohm 0 ohm

PHY Address 0b00000

Non-IEEE Compliant Mode JT14: pins 1-2 1 K

1 K

Compliant and Non-comp. Operation (default)

JT14: pins 2-3 Inhibits Non-compliant operation

Manual MDIX Setting JT13: pins 1-2 1 K

1 K

Straight Mode (default)

JT13 pins 2-3 Cross-over Mode

Auto MDIX Enable

JT12: pins 1-2 1 K 1 K

Automatic Pair Swap – MDIX (default)

JT12: pins 2-3 Set to manual preset – Manual MDIX Setting

(JT12)

Multiple Node Enable JT11: pins 1-2 1 K

1 K

Single node – NIC (default)

JT11: pins 2-3 Multiple node priority – switch/hub

Clock to MAC Enable JT15: pins 1-2 1 K

1 K

CLK_TO_MAC output enabled (default)

JT15: pins 2-3 CLK_TO_MAC output disabled

Table 20 - Ethernet PHY Hardware Strapping Options

The default options as indicated in Table 20 are Auto-Negotiation enabled, Full Duplex mode, Speed advertised as 10/100/1000 Mb/s, PHY address 0b00001, IEEE Compliant and Non-compliant support, straight cable in non-MDIX mode, auto-MDIX mode enabled, Single node (NIC) and CLK_TO_MAC enabled. The pin-out for a jumper pad is shown below.

The auto-MDIX mode provides automatic swapping of the differential pairs. This allows the PHY to work with either a straight-through cable or crossover cable. Use a CAT-5e or CAT-6 Ethernet cable when operating at 1000 Mb/s (Gigabit Ethernet). The boundary-scan Test Access Port (TAP) controller of the DP83865 must be in reset for normal operation. This active low reset pin of the TAP (TRST) is pulled low through a 1K resistor on the board.

1 2 3

JT#


The following tables provide the Spartan-6pin assignments for the Ethernet PHY interfaces.

Net Name Spartan-6 pin # Net Name Spartan-6 pin #

GBE_FP_MDC N5 GBE_ FP_INT# P10

GBE_ FP_MDIO N4 GBE_ FP_RST# P8

GBE_ FP_MCLK T3 GMII_ FP_CRS R3

GMII_ FP_GTC_CLK U5 GMII_ FP_COL R9

GMII_ FP_TXD0 T4 GMII_ FP_RXD0 T9

GMII_ FP_TXD1 R10 GMII_ FP_RXD1 P3

GMII_ FP_TXD2 U2 GMII_ FP_RXD2 P1

GMII_ FP_TXD3 U1 GMII_ FP_RXD3 N6

GMII_ FP_TXD4 T8 GMII_ FP_RXD4 P6

GMII_ FP_TXD5 R8 GMII_ FP_RXD5 P5

GMII_ FP_TXD6 W1 GMII_ FP_RXD6 R5

GMII_ FP_TXD7 W2 GMII_ FP_RXD7 N8

GMII_ FP_TX_EN V1 GMII_ FP_RX_DV N7

GMII_ FP_TX_ER V3 GMII_ FP_RX_ER R4

GMII_ FP_TX_CLK R7 GMII_ FP_RX_CLK V4

Table 21 - Faceplate Ethernet PHY “U4” Pin Locations

2.5.2 USB 2.0 ULPI PHY

The USB 2.0 ULPI PHY is the NXP ISP1504A1. The device is a ULPI High Speed USB OTG transceiver that can interface to host, peripherals, and OTG cores. The PHY contains a complete USB physical front-end that supports high speed (480 Mbit/s), full-speed (12 Mbit/s), low-speed (1.5 Mbits/s). The following figure shows a high-level block diagram of the interface to the USB 2.0 ULPI PHY and the Virtex-5 FPGA.

Figure 15 - USB 2.0 ULPI PHY Interface


USB Net Name Spartan-6 Pin #

USB_DATA_0 AB5

USB_DATA_1 AC4

USB_DATA_2 AA4

USB_DATA_3 AA3

USB_DATA_4 Y6

USB_DATA_5 Y5

USB_DATA_6 AB4

USB_DATA_7 AC3

USB_CLKOUT R2

USB_NXT V7

USB_STP V6

USB_DIR U4

USB_RESET U3

Table 22 - USB Interface Pin Locations

2.5.3 RS232

The RS232 transceiver is a MAX3221 available from Maxim. This transceiver operates at 3.3 V with an internal charge pump to create the RS232 compatible output levels. This level converter supports a single channel used for transmit and receive data (TXD and RXD). The RS232 console interface is brought out on the DB9 connector labeled P3. The Spartan-6 LX150T

development board supports straight-through serial cables.

RS232

Drivers

TXD

RXD

2 (RD)

3 (TD)Rout1

Din1

Rin1

Dout1

Spartan-6

FPGA

RS232

Connector

Figure 16 - RS232 Interface


A male-to-female serial cable should be used to plug P3 into a standard PC serial port (male DB9). The following table shows

the FPGA pin-out and jumper settings for the RS232 interface.

Net Name Description Spartan-6

Pin #

RS232_RXD Received Data, RD AC2

RS232_TXD Transmit Data, TD AC1

Table 23 - RS232 Pin Locations

2.5.4 USB-RS232

The Spartan-6 LX150T PCI Express Development Board Implements a Cypress CP2102 device that provides a USB-to-RS232 bridge. The USB physical interface is brought out on a USB Type-B connector labeled ―JR1‖. The USB-to-RS232 bridge interface connects to the Spartan-6 FPGA through the following pins:

Net Name Spartan-6 Pin #

USB_RS232_RXD AE2

USB_RS232_TXD AE1

Table 24 – USB-to-RS232 Pin Locations

2.6 User Switches

Four momentary closure push buttons have been installed on the board and attached to the FPGA. These buttons can be programmed by the user and are ideal for logic reset and similar functions. Pull down resistors hold the signals low until the switch closure pulls them high (active high signals).

Net Name Reference Spartan-6

Pin #

SWITCH_PB1 SW2 M19

SWITCH_PB2 SW3 L20

SWITCH_PB3 SW4 L21

SWITCH_PB4 SW5 H20

Table 25 - Push Button Pin Locations

An eight-position dipswitch (SPST) has been installed on the board and attached to the FPGA. These switches provide digital inputs to user logic as needed. The signals are pulled low by 1K ohm resistors when the switch is open and tied high to 3.3 V when closed as shown in the following table.

Net Name Reference Voltage when

closed Spartan-6Pin

#

SWITCH0 SW6 – 1

3.3 V

K21

SWITCH1 SW6 – 2 G23

SWITCH2 SW6 – 3 G24

SWITCH3 SW6 – 4 J20

SWITCH4 SW6 – 5 J22

SWITCH5 SW6 – 6 E24

SWITCH6 SW6 – 7 E23

SWITCH7 SW6 – 8 K22

Table 26 - DIP Switch Pin Locations

2.7 User LEDs

Eight discrete LEDs are installed on the board and can be used to display the status of the internal logic. These LEDs are attached as shown below and are lit by forcing the associated FPGA I/O pin to a logic ‗1‘ and are off when the pin is either low (0) or not driven.


Net Name Reference Spartan-6

Pin #

LED0 D7 M18

LED1 D8 L19

LED2 D9 M21

LED3 D10 F22

LED4 D11 H22

LED5 D12 C25

LED6 D13 C26

LED7 D14 F23

Table 27 - LED Pin Locations

2.8 Configuration

The Spartan-6 LX150T development board supports several methods of configuring the FPGA. The possible configuration sources include Boundary-scan (JTAG cable), and SelectMap from the configuration PROMs. The blue LED labeled ―DONE‖ on the board illuminates to indicate when the FPGA has been successfully configured.

2.8.1 Configuration Modes

Upon power-up the FPGA will be enabled in a configuration mode defined by the jumpers on ―JP2‖. The default configuration mode is Master Select Map mode when no jumpers are installed which will allow the FPGA to be configured from the Platform Flash. JTAG device configuration can occur at any time regardless of the mode jumper‘s configuration. The following table shows the various configuration modes that are supported:

Config Mode M1 M0

Master Select Map 0 0

Slave Select Map 1 0

Slave Serial 1 1

Table 28 - Setting the Configuration Mode “JP2”

2.8.2 JTAG Chain

The Spartan-6 LX150T development board has five devices/connectors in the JTAG chain, the XCF32P configuration PROM, XCF08 configuration PROM, the Spartan-6 LX150T FPGA and the two FMC connectors. The following figure shows a high-level block diagram of the JTAG Chain on the development board.

JTAG_TDO

PC4

Connector FPGA_TDI

FPGA_TMS

FPGA_TCK

FMC #1

TDITD

OFPGA_TMS

FPGA_TCK

FPGA_TMS

FPGA_TCK

FMC #2

TDITD

OTD

I

TD

O

FPGA

TD

I

TD

O

XCF08P

TD

I

TD

O

XCF32P

JP4

J7

J9

Figure 17 - JTAG Chain on the Spartan-6 PCI Express Board

Configuring the JTAG chain to exclude or include one or both of the FMC connectors can be done using jumpers on J7 and JP4 to connect the TDO/TDI paths as desired as shown in the diagram above. Programming the Spartan-6 FPGA via Boundary-scan mode requires a JTAG download cable (not included in the kit). The Spartan-6 LX150T development board has a single connector to support the ribbon cable connection of the Parallel Cable IV and Platform Cable USB. The connector is labeled J9. For more information about JTAG download cables, perform a search

on the Xilinx web page http://www.xilinx.com using the key words ―Programming Cables‖. When using the flying leads connection of the Parallel Cable III, connect the leads to SAM header as indicated in the following table.

http://www.xilinx.com/


Signal Name J9 pin

TDO 3

TMS 5

TDI 7

VCC 2

GND 4

TCK 10

Table 29 - Flying Lead JTAG Header

2.9 I2C Buses, Devices, and Interfaces

The Spartan-6 LX150T development board implements two separate I2C buses to communicate to various devices and interfaces that can be configured to interconnect creating a single I2C bus using jumpers. One I2C bus primarily interfaces with the two FMC connectors. The second I2C bus interfaces primarily with the Real Time Clock, the Temp Sensor and the ALI (Avnet LCD Interface) interface. Those devices and interfaces are discussed in further detail in the following sections. By placing jumpers in the proper positions on JP5 and JP6, the two buses can be connected together to make a single all-

inclusive I2C bus. The diagram below shows the two I2C buses.

Spartan-6

FMC

#1

SCL0

FMC

#2

SDA0

RTC

SCL

Temp

Sensor

SDA

ALI

SCL1

SDA

1

3.3V

3.3V

Ban

k 3

I/O

(FM

C I2

C)

Ban

k 3

I/O

(AL

I I2

C)

JP5

JP6

1

Figure 18 - I2C Buses

2.9.1 Real Time Clock

The Spartan-6 LX150T development board has an on-board Maxim DS3232 Real Time Clock (RTC). The device utilizes an I2C interface to access control and data registers. The DS3232 is a low-cost temperature compensated crystal oscillator (TXCO) with a very accurate temperature compensated real-time clock and 236 bytes of battery backed SRAM. Refer to the Maxim DS3232 data sheet for more detailed information about this device. The following table shows how the DS3232 interface is connected to the Spartan-6 FPGA.

Signal Name Spartan-6 Pin #

RTC_RST# E25

RTC_32KHz E26

RTC_INT# J24

SCL Configurable (JP5) – AB3 or M10

SDA Configurable (JP6) - AB1 or N9

Table 30 - Real Time Clock Pin Locations


2.9.2 Temperature Sensor

The Spartan-6 LX150T development board has an on-board Maxim MAX7500 digital temperature sensor. The device utilizes an I2C interface to access control and data registers. The MAX7500 accurately measures temperature and converts the measurement to digital form using a high resolution sigma-delta ADC. Refer to the MAX7500 data sheet for more detailed information about this device. The following table shows how the MAX7500 interface is connected to the Spartan-6 FPGA.

Signal Name Spartan-6 Pin #

SCL Configurable (JP5) – AB3 or M10

SDA Configurable (JP6) - AB1 or N9

Table 31 - Temperature Sensor Pin Locations

2.9.3 ALI Interface (Avnet LCD Interface)

The Spartan-6 LX150T development board supports the Avnet LCD Interface (ALI) by having the on-board 50 pin connector used to interface to various LCDs. ALI is an Avnet specification with the purpose of making a common interface from any Avnet development board to an off-board LCD. The figure below is a high level diagram of how this is accomplished.

Avnet Display Kit

Avn

et

Dis

pla

y

Ad

ap

ter

Bo

ard

Display Panel,

Backlight, and

Touchscreen

Avnet Display Kit

Avn

et

Dis

pla

y

Ad

ap

ter

Bo

ard

Display Panel,

Backlight, and

Touchscreen

Display Panel,

Backlight, and

Touchscreen

Avnet Development BoardAvnet Development Board

Ribbon

Cable

Avnet LCD Interface (ALI)

Figure 19 - ALI Interface

Please refer to the ALI specification for more detailed information on the electrical and physical implementation of the interface.

http://www.files.em.avnet.com/files/218/avnet-display-spec-1%2000(1).pdf

2.9.4 FPGA Mezzanine Card (FMC) Low Pin Count (LPC) Interface

The Spartan-6 LX150T development board has two on-board FMC LPC connectors used as expansion connectors. These expansion connectors can be used with off-the-shelf or user designed FMC modules. The FMC expansion connectors are described in detail in Section 2.12.

Please be advised that due to limited I/O and global clock resources on the Spartan-6 LX150T FPGA FMC slot JX2 is not fully FMC compliant. FMC2 signal pairs LA19, LA20, LA21 and LA23 are not routed differentially and should be treated as single ended signals.

http://www.files.em.avnet.com/files/218/avnet-display-spec-1%2000(1).pdf


2.10 Power

The Spartan-6 LX150T development board power is developed from a +12 V input provided by the furnished power supply J16 OR from the +12 V rail of a PCI Express bus OR from the 4-pin ATX power connector JP7 OR from a 2.5 mm barrel jack J17

(not populated on production boards). All of the voltage rails used on the board are derived from the 12V source, either directly or indirectly. They are 5.0V, 3.3V, FMC_3.3V, 2.5V, 1.8V, 1.5V and 1.2V, MGT_CORE_1.2V, MGT_TERM_1.2V, DDR_REF_0.75V, and DDR_TERM_0.75V. The two MGT power supplies are designed with a dual footprint to accommodate either a TI or a National power solution. The production boards are populated with the TI solution, utilizing two TPS54317 3-Amp switching regulators to generate the MGT_TERM_1.2V and MGT_CORE_1.2V rails. By changing some of the component values, depopulating and populating some others, the National power solution implementing two LMZ10504 4-Amp switching regulators to generate the MGT voltage rails. Refer to the schematic design notes for the MGT power supplies for the details on which components to swap and/or change out. In stand-alone mode the board is connected to the external power supply via the six pin right angle connector J16. The power

supply shipped with the Spartan-6 LX150T development board can supply 12 V @ 5 Amps.

NOTICE!!! NOTICE!!! NOTICE!!!

THE 6-PIN CONNECTOR “J16” SHOULD NEVER BE PLUGGED INTO A PC’S ATX 6-PIN PCI EXPRESS POWER CONNECTOR.

THE TWO CONNECTORS ARE NOT COMPATIBLE AND WILL CAUSE DAMAGE TO THE PC POWER SUPPLY, THE

SPARTAN-6 S6LX150T PCI EXPRESS DEVELOPMENT BOARD, OR BOTH.

THE CONNECTOR “J16” WILL HAVE THE FOLLOWING LABEL ADHERED TO ITS TOP SIDE:

NOTICE!!! NOTICE!!! NOTICE!!!

The current requirements for the board are application specific. It should be noted that, per the PCI Express specification, maximum power available to a single x4 PCI Express add-in card is 25.2 watts (2.1 @ +12 V). Should the user want to use the development board in the PCI Express slot but require more than the max power provided over the card edge connector the 4-pin ATX power connector JP7 is available to provide additional power. The user can select between which 12 V source to use, either card edge or ATX, by selecting the correct position at SW12.

The main power switch to for the development board is SW11 and must be turned ON to supply any power to the board.


The figure below shows a high-level block diagram of the main power supplies on the development board.

PCI

Express

Card

Edge

Spartan-6

FG676

LMZ142035V @ 3A

DDR3

12V 5.0V

1.5V

TPS543171.2V @ 3A

(MGT_TERM)

TPS543171.2V @ 3A

(MGT_CORE)

6-pin

Bench Supply

J16

4-pin

ATX Connector

JP7

2.5mm

Barrel Jack

J17

(Not

Populated)

LMZ136103.3V @ 10A

(FMC_3.3V)

LMZ142031.8V @ 3A

LMZ136102.5V @ 10A

LMZ105041.5V @4A

LMZ142031.2V @ 3A

LMZ136103.3V @ 10A

LP2998

DDR_TERM_0.75V

DDR_REF_0.75V

2.5VLMZ105042.5V @4A

2.5V

1.8V

1.2V

3.3V

3.3V

1.2V

1.2V

FMC JX1

FMC JX2

FMC_3.3V

GTP

1.5V

Figure 20 - Board Power Supply

2.10.1 FPGA I/O Voltage (VCCO)

FPGA banks 3 and 5 are powered at VCCO = +3.3 V and banks 1 and 2 are powered at VCCO = +2.5 V. Bank 4 is powered at +1.5 V for the DDR3 controller. Bank 0 is selectable between +2.5V or +3.3V and services the FMC connector JX1. Depending on what logic levels are required for a module connected to JX1 the VCCO voltage can be selected by placing a jumper in the appropriate position at JP8.

The following table shows how the Spartan-6 FPGA banks are powered.

Bank # 1.8 V 1.5 V 2.5 V 3.3 V 2.5 V/3.3 V Selectable

Rail

0 X FMC1_VIO

1 X -

2 X -

3 X -

4 X -

5 X -

Table 32 - I/O Bank Voltages


2.10.2 FPGA Reference Voltage (Vref)

The Spartan-6 LX150T development board provides the reference voltage of +0.75 V to Bank 4 which is connected to the DDR3 memory interface. 2.10.3 GTP Voltage Regulators (AVCC, AVCCPLL, VTTRX, VTTTX, AVTTRCAL)

The Spartan-6 LX150T development board provides point-of-load regulation for the GTP supplies with high-precision, low drop-out linear regulators from Texas Instruments. The TPS54317 regulators provide up to 3.0 amps of current. The low input voltage requirement minimizes the voltage drop across the regulator saving the added cost of thermal solutions in most applications. The adjustable output range, down to 0.9 V, makes the TPS54317 switchers a good fit for the low voltage GTP supplies. The small 5.15 mm x 4.15 mm PQFP packages are ideal for space limited applications like PCI form-factor add-in cards. The following figure shows a high-level block diagram of the GTP power supplies. The two MGT power supplies are designed with a dual footprint to accommodate either a TI or a National power solution. The production boards are populated with the TI solution, utilizing two TPS54317 3-Amp switching regulators to generate the MGT_TERM_1.2V and MGT_CORE_1.2V rails. By changing some of the component values, depopulating and populating some others, the National power solution implementing two LMZ10504 4-Amp switching regulators to generate the MGT voltage rails can be used. Refer to the schematic design notes for the MGT power supplies for the details on which components to swap and/or change out. The following table contains estimated current utilization for the GTP rails based on the Spartan-6 datasheet.

Net Name MGT Rails Current Consumption per tile

Min Typical Max

MGT_TERM_1.2V MGTVTTTX - 27.4 -

MGTVTTRX - 13.6 -

MGT_CORE_1.2V MGTAVCC - 40.4 -

MGTAVCCPLL - 28.7 -

Table 33 - Typical Current Measurements per MGT Tile

2.11 Thermal Management

The Spartan-6 LX150T FPGA on the development board may require a heat sink to keep the junction temperate within the operating limits of the device. A heat sink requirement will be a function of the application in which the Spartan-6 LX150T FPGA is being used for. The amount of power that needs to be dissipated is design dependent. The main contributors to the overall power are utilization, frequency and the number of active RocketIO transceivers. The Spartan-6 LX150T development board does not come with a heat sink. Aavid is a known supplier that has provided heat sink solutions for Xilinx FPGAs in the past. More information is available on Aavid‘s web site: http://www.aavidthermalloy.com/products/bga/index.shtml.

2.12 Expansion Connectors

The Spartan-6 LX150T development board provides expansion capabilities for customized user application daughter cards and interfaces over two low pin count (LPC) FPGA Mezzanine Card (FMC) expansion connectors. For more details regarding FMC please view the FPGA Mezzanine Card specification at http://www.vita.com/fmc.html.

NOTE: FMC slot JX2 does not fully comply with the FMC specification. Please refer to Table 36 for details on non-compliant signals.

2.12.1 FMC Low Pin Count (LPC) Interface

The FMC specification defines the LPC interface to be a 160-pin connector arranged in a 4x40 array. The LPC connector is populates 160 of the 400 possible positions. The HPC (High Pin Count) version of the connector has all positions populated. The FMC LPC configuration implemented on the Spartan-6 LX150T development board uses two LPC connectors (SAMTEC part number ASP-134603-01), for a total of 136 user I/Os. The connectors are referenced JX1 and JX2 on the board.

The FMC specification defines five user signal types: Differential I/O, Differential Clock Inputs, Differential Clock Outputs, MGT I/O, and MGT Clock Inputs. Because the FPGA I/Os can be configured for either single-ended or differential use, the differential I/Os defined in the FMC specification can serve a dual role. All the differential I/O signals can be configured as either differential pairs or single-ended signals, as required by the end application. In providing differential signaling, higher performance LVDS interfaces can be implemented between Spartan-6 LX150T development board and an FMC LPC module. Connection to high speed A/Ds, D/As, and flat panel displays are possible with this signaling configuration. Applications that require single-ended signals only can use each differential pair as two single-ended signals, for a total of 68 single-ended I/O per LPC connector.

http://www.aavidthermalloy.com/products/bga/index.shtml

http://www.vita.com/fmc.html


Net Names Signal Description Pins per

Connector

FMC_LA**_P/N 34 Differential I/O Pairs 68

Total User I/O 68

FMC_CLK0_C2M_P/N 1 Differential Clock Pair (Carrier to Mezzanine)

2

FMC_CLK0_M2C_P/N 1 Differential Clock Pair (Mezzanine to Carrier)

2

Total Clock I/O 4

FMC_DP0_M2C_P/N 1 MGT Receive Differential Data Pair 2

FMC_DP0_C2M_P/N 1 MGT Transmit Differential Data Pair 2

FMC_GBTCLK0_M2C_P/N 1 MGT Differential Clock Pair 2

Total MGT I/O 6

Table 34 - FMC LPC Connector Signals

Figure 21 - FMC LPC Connector Pinout


Note: For the FMC LPC, the connector columns K, J, F, E, B, and A are not used and not shown in the above table.

The SAMTEC connector plug on the board (CC-LPC-10 part number: ASP-134603-01) mates with the SAMTEC low pin count receptacle (MC-LPC-10 part number: ASP-134604-01), located on FMC modules. FMC JX1 is connected exclusively to Bank 0 of the S6LX150T FPGA and allows the user to select VADJ to either 2.5 V or 3/3 V via jumper JP8.

Since the FMC connectors are connected to the I2C bus a geographical address must be given to the connector. The GA[1:0] inputs provide a means to give the connector an I2C address. For JX1 the address is hard wired to 0x00 by tying these inputs low through pull-down resistors. Connector JX2 is hard wired to address 0x01 via a pull-down resistor on GA0 and a pull-up resistor on GA1. The following diagram and table shows how FMC LPC connector JX1 is connected to the Spartan-6 LX150T FPGA.

LA[00:33]_P, LA[00:33]_N

VADJ

VREF_A_M2C

FMC JX1 LPC ConnectorSpartan-6 FPGA

Ban

k 0

FP

GA

IOV

CC

IO

JP8

VADJ = 2.5V or 3.3V

CLK[0:1]_M2C_P, CLK[0:1]_M2C_N

Ban

k 0

FP

GA

Glo

bal

Clo

ck

Inp

uts

GBTCLK0_M2C_P, GBTCLK0_M2C_NMG

T

Ref

Clo

ck

Inp

ut

DP[0]_M2C_P, DP[0]_M2C_N

DP[0]_C2M_P, DP[0]_C2M_N

RX

TXMG

Ts

GA[0:1]

Ban

k 3

SCLSDA

TDIFP

GA

JT

AG

TMSTCK

TRST_L

TDO

3P3 V AUX3P3V

12P0V

PRSTN_M2C_L

PG_C2M

Ban

k 3

0x00

FP

GA

Glo

bal

Clo

ck

Inp

uts

LA00_P_CC, LA00_N_CC

LA17_P_CC, LA17_N_CC

Vre

f

Figure 22 - FMC LPC Connector JX1 Block Diagram


Spartan-6 Pin

Location

Schematic Net Name

FMC Connector Pin Location

(JX1)

FMC Connector Symbol Name

- GND C1 GND

AE19 FMC1_DP0_C2M_P C2 DP0_C2M_P

AF19 FMC1_DP0_C2M_N C3 DP0_C2M_N

- GND C4 GND

- GND C5 GND

AC18 FMC1_DP0_M2C_P C6 DP0_M2C_P

AD18 FMC1_DP0_M2C_N C7 DP0_M2C_N

- GND C8 GND

- GND C9 GND

H17 FMC1_LA06_P C10 LA06_P

G17 FMC1_LA06_N C11 LA06_N

- GND C12 GND

- GND C13 GND

D21 FMC1_LA10_P C14 LA10_P

D22 FMC1_LA10_N C15 LA10_N

- GND C16 GND

- GND C17 GND

F14 FMC1_LA14_P C18 LA14_P

E14 FMC1_LA14_N C19 LA14_N

- GND C20 GND

- GND C21 GND

J13 FMC1_LA18_CC_P C22 LA18_P_CC

H13 FMC1_LA18_CC_N C23 LA18_N_CC

- GND C24 GND

- GND C25 GND

G12 FMC1_LA27_P C26 LA27_P

F11 FMC1_LA27_N C27 LA27_N

- GND C28 GND

- GND C29 GND

AB3 SCL_0 C30 SCL

AB1 SDA_0 C31 SDA

- GND C32 GND

- GND C33 GND

- PULL-DOWN C34 GA0

- +12.0V C35 12P0V

- - C36 GND

- +12.0V C37 12P0V

- - C38 GND

- FMC_3.3V C39 3P3V

- - C40 GND

- FMC1_VIO (PULL-UP) D1 PG_C2M

- GND D2 GND

- GND D3 GND

AC16 FMC1_GBTCLK0_M2C_P D4 GBTCLK0_M2C_P

AD16 FMC1_GBTCLK0_M2C_N D5 GBTCLK0_M2C_N

- GND D6 GND

- GND D7 GND

J15 FMC1_LA01_CC_P D8 LA01_P_CC

H15 FMC1_LA01_CC_N D9 LA01_N_CC

- GND D10 GND

F20 FMC1_LA05_P D11 LA05_P

E20 FMC1_LA05_N D12 LA05_N

- GND D13 GND



- GND D16 GND

C21 FMC1_LA13_P D17 LA13_P

B21 FMC1_LA13_N D18 LA13_N

- GND D19 GND

B12 FMC1_LA17_CC_P D20 LA17_P_CC

A12 FMC1_LA17_CC_N D21 LA17_N_CC

- GND D22 GND

J11 FMC1_LA23_P D23 LA23_P

G11 FMC1_LA23_N D24 LA23_N

- GND D25 GND



- GND D28 GND

A24 JTAG_TCK D29 TCK

G21 FPGA_TDO D30 TDI

- FMC1_TDO D31 TDO

- FMC_3.3V D32 3P3VAUX

F21 JTAG_TMS D33 TMS


AD3 FMC_TRST_L D34 TRST_L

- PULLD-DOWN D35 GA1

- FMC_3.3V D36 3P3V

- GND D37 GND

- FMC_3.3V D38 3P3V

- GND D39 GND

- FMC_3.3V D40 3P3V

- GND G1 GND

E13 FMC1_CLK1_M2C_P G2 CLK1_M2C_P

D13 FMC1_CLK1_M2C_N G3 CLK1_M2C_N

- GND G4 GND

- GND G5 GND

B14 FMC1_LA00_CC_P G6 LA00_P_CC

A14 FMC1_LA00_CC_N G7 LA00_N_CC

- GND G8 GND

G15 FMC1_LA03_P G9 LA03_P

F15 FMC1_LA03_N G10 LA03_N

- GND G11 GND



- GND G14 GND

B23 FMC1_LA12_P G15 LA12_P

A23 FMC1_LA12_N G16 LA12_N

- GND G17 GND

J16 FMC1_LA16_P G18 LA16_P

J17 FMC1_LA16_N G19 LA16_N

- GND G20 GND

F12 FMC1_LA20_P G21 LA20_P

E12 FMC1_LA20_N G22 LA20_N

- GND G23 GND

H9 FMC1_LA22_P G24 LA22_P

G9 FMC1_LA22_N G25 LA22_N

- GND G26 GND

F9 FMC1_LA25_P G27 LA25_P

E8 FMC1_LA25_N G28 LA25_N

- GND G29 GND



- GND G32 GND

B5 FMC1_LA31_P G33 LA31_P

A5 FMC1_LA31_N G34 LA31_N

- GND G35 GND

C3 FMC1_LA33_P G36 LA33_P

B3 FMC1_LA33_N G37 LA33_N

- GND G38 GND

- FMC1_VIO G39 VADJ_2.5V

- GND G40 GND

- FMC1_VREF_A_M2C H1 VREF_A_M2C

M9 FMC1_PRSNT_M2C_L H2 PRSNT_M2C_L

- GND H3 GND

C13 FMC1_CLK0_M2C_P H4 CLK0_M2C_P

A13 FMC1_CLK0_M2C_N H5 CLK0_M2C_N

- GND H6 GND

K14 FMC1_LA02_P H7 LA02_P

H14 FMC1_LA02_N H8 LA02_N

- GND H9 GND

G19 FMC1_LA04_P H10 LA04_P

F19 FMC1_LA04_N H11 LA04_N

- GND H12 GND

F18 FMC1_LA07_P H13 LA07_P

E18 FMC1_LA07_N H14 LA07_N

- GND H15 GND

B22 FMC1_LA11_P H16 LA11_P

A22 FMC1_LA11_N H17 LA11_N

- GND H18 GND

H12 FMC1_LA15_P H19 LA15_P

G13 FMC1_LA15_N H20 LA15_N

- GND H21 GND



- GND H24 GND



- GND H27 GND

F7 FMC1_LA24_P H28 LA24_P

F6 FMC1_LA24_N H29 LA24_N


- GND H30 GND

D5 FMC1_LA28_P H31 LA28_P

C5 FMC1_LA28_N H32 LA28_N

- GND H33 GND

B4 FMC1_LA30_P H34 LA30_P


- GND H36 GND

A3 FMC1_LA32_P H37 LA32_P


- GND H39 GND

- FMC1_VIO H40 VADJ_2.5V

Table 35 - FMC LPC Connector JX1 Pin Locations

The following diagram and table shows how FMC LPC connector JX2 is connected to the Spartan-6 LX150T FPGA.

LA[00:33]_P, LA[00:33]_N

VADJ

VREF_A_M2C

FMC JX2 LPC Connector Spartan-6 FPGA

Ban

k 1

an

d 2 F

PG

A

IOV

CC

IO

CLK[0:1]_M2C_P, CLK[0:1]_M2C_N

Ban

k 2

FP

GA

Glo

bal

Clo

ck

Inp

uts

GBTCLK0_M2C_P, GBTCLK0_M2C_NMG

T

Ref

Clo

ck

Inp

ut

DP[0]_M2C_P, DP[0]_M2C_N

DP[0]_C2M_P, DP[0]_C2M_N

RX

TXMG

Ts

GA[0:1]

SCLSDA

TDI

FP

GA

JT

AG

TMSTCK

TRST_L

TDO3P3 V AUX

3P3V12P0V

PRSTN_M2C_L

PG_C2M

Ban

k

3

0x01

Common with FMC

Common with FMC LPC JX1

Vre

f

VADJ

(2.5V)

LPC JX1

Figure 23 - FMC LPC Connector JX2 Block Diagram


Spartan-6

Pin Location

Schematic Net Name

FMC Connector Pin Location

(JX2)

FMC Connector Symbol Name

FMC Specification

Deviation

- GND C1 GND

AE21 FMC2_DP0_C2M_P C2 DP0_C2M_P

AF21 FMC2_DP0_C2M_N C3 DP0_C2M_N

- GND C4 GND

- GND C5 GND

AC20 FMC2_DP0_M2C_P C6 DP0_M2C_P

AD20 FMC2_DP0_M2C_N C7 DP0_M2C_N

- GND C8 GND

- GND C9 GND

V14 FMC2_LA06_P C10 LA06_P

V15 FMC2_LA06_N C11 LA06_N

- GND C12 GND

- GND C13 GND

W16 FMC2_LA10_P C14 LA10_P

Y16 FMC2_LA10_N C15 LA10_N

- GND C16 GND

- GND C17 GND

Y15 FMC2_LA14_P C18 LA14_P

AA16 FMC2_LA14_N C19 LA14_N

- GND C20 GND

- GND C21 GND

U25 FMC2_LA18_CC_P C22 LA18_P_CC

U26 FMC2_LA18_CC_N C23 LA18_N_CC

- GND C24 GND

- GND C25 GND

Y24 FMC2_LA27_P C26 LA27_P

Y26 FMC2_LA27_N C27 LA27_N

- GND C28 GND

- GND C29 GND

AB3 SCL_0 C30 SCL

AB1 SDA_0 C31 SDA

- GND C32 GND

- GND C33 GND

- PULL-DOWN C34 GA0

- +12.0V C35 12P0V

- - C36 GND

- +12.0V C37 12P0V

- - C38 GND

- FMC_3.3V C39 3P3V

- - C40 GND

- 2.5V (PULL-UP) D1 PG_C2M

- GND D2 GND

- GND D3 GND

AE17 FMC_GBTCLK0_M2C_P D4 GBTCLK0_M2C_P

AF17 FMC_GBTCLK0_M2C_N D5 GBTCLK0_M2C_N

- GND D6 GND

- GND D7 GND

V11 FMC_LA01_CC_P D8 LA01_P_CC Not Routed to

Global CLK Pins

V10 FMC_LA01_CC_N D9 LA01_N_CC Not Routed to

Global CLK Pins

- GND D10 GND

Y12 FMC_LA05_P D11 LA05_P

AA12 FMC_LA05_N D12 LA05_N

- GND D13 GND

AA21 FMC_LA09_P D14 LA09_P

AB21 FMC_LA09_N D15 LA09_N

- GND D16 GND

AA15 FMC_LA13_P D17 LA13_P

AB15 FMC_LA13_N D18 LA13_N

- GND D19 GND

W14 FMC_LA17_CC_P D20 LA17_P_CC Not Routed to

Global CLK Pins

Y13 FMC_LA17_CC_N D21 LA17_N_CC Not Routed to

Global CLK Pins

- GND D22 GND

AC5 FMC_LA23_P D23 LA23_P Routed Single

Ended


Y11 FMC_LA23_N D24 LA23_N Routed Single

Ended

- GND D25 GND

AE25 FMC_LA26_P D26 LA26_P

AE26 FMC_LA26_N D27 LA26_N

- GND D28 GND

A24 JTAG_TCK D29 TCK

G21 FMC2_TDI D30 TDI

- FMC2_TDO D31 TDO

- FMC_3.3V D32 3P3VAUX

F21 JTAG_TMS D33 TMS

AD3 FMC_TRST_L D34 TRST_L

- PULL-UP D35 GA1

- FMC_3.3V D36 3P3V

- GND D37 GND

- FMC_3.3V D38 3P3V

- GND D39 GND

- FMC_3.3V D40 3P3V

- GND G1 GND

AD14 FMC2_CLK1_M2C_P G2 CLK1_M2C_P

AF14 FMC2_CLK1_M2C_N G3 CLK1_M2C_N

- GND G4 GND

- GND G5 GND

AE13 FMC2_LA00_CC_P G6 LA00_P_CC

AF13 FMC2_LA00_CC_N G7 LA00_N_CC

- GND G8 GND

Y21 FMC2_LA03_P G9 LA03_P

AA22 FMC2_LA03_N G10 LA03_N

- GND G11 GND

AB22 FMC2_LA08_P G12 LA08_P

AC22 FMC2_LA08_N G13 LA08_N

- GND G14 GND

W17 FMC2_LA12_P G15 LA12_P

W18 FMC2_LA12_N G16 LA12_N

- GND G17 GND

AA7 FMC2_LA16_P G18 LA16_P


- GND G20 GND

AA17 FMC2_LA20_P G21 LA20_P Routed Single

Ended

AC23 FMC2_LA20_N G22 LA20_N Routed Single

Ended

- GND G23 GND

T19 FMC2_LA22_P G24 LA22_P

T20 FMC2_LA22_N G25 LA22_N

- GND G26 GND

V23 FMC2_LA25_P G27 LA25_P

W24 FMC2_LA25_N G28 LA25_N

- GND G29 GND

AA23 FMC2_LA29_P G30 LA29_P


- GND G32 GND

AD24 FMC2_LA31_P G33 LA31_P

AD26 FMC2_LA31_N G34 LA31_N

- GND G35 GND

U19 FMC2_LA33_P G36 LA33_P

U20 FMC2_LA33_N G37 LA33_N

- GND G38 GND

- 2.5V G39 VADJ_2.5V

- GND G40 GND

- NC H1 VREF_A_M2C

AD1 FMC2_PRSNT_M2C_L H2 PRSNT_M2C_L

- GND H3 GND

AE15 FMC2_CLK0_M2C_P H4 CLK0_M2C_P

AF15 FMC2_CLK0_M2C_N H5 CLK0_M2C_N

- GND H6 GND

AB13 FMC2_LA02_P H7 LA02_P

AA13 FMC2_LA02_N H8 LA02_N

- GND H9 GND

AA18 FMC2_LA04_P H10 LA04_P

AB17 FMC2_LA04_N H11 LA04_N

- GND H12 GND

AA19 FMC2_LA07_P H13 LA07_P


- GND H15 GND

U13 FMC2_LA11_P H16 LA11_P


V13 FMC2_LA11_N H17 LA11_N

- GND H18 GND


V16 FMC2_LA15_N H20 LA15_N

- GND H21 GND

W20 FMC2_LA19_P H22 LA19_P Routed Single

Ended

Y17 FMC2_LA19_N H23 LA19_N Routed Single

Ended

- GND H24 GND

U24 FMC2_LA21_P H25 LA21_P Routed Single

Ended

R26 FMC2_LA21_N H26 LA21_N Routed Single

Ended

- GND H27 GND

AB24 FMC2_LA24_P H28 LA24_P


- GND H30 GND

AC25 FMC2_LA28_P H31 LA28_P

AC26 FMC2_LA28_N H32 LA28_N

- GND H33 GND

T22 FMC2_LA30_P H34 LA30_P

T23 FMC2_LA30_N H35 LA30_N

- GND H36 GND


U22 FMC2_LA32_N H38 LA32_N

- GND H39 GND

- 2.5V H40 VADJ_2.5V

Table 36 - FMC LPC Connector JX2 Pin Locations

NOTE: FMC2 signal pairs LA19, LA20, LA21 and LA23 are not routed differentially and should be treated as single

ended signals.

3.0 Test Designs This section describes the factory test design that is pre-programmed into the configuration PROM as well as the Ethernet test provided on the Design Resource Center (DRC) web site: www.em.avnet.com/drc. The factory test design is used to verify some of the functionality of the board and may require additional test apparatus. If the configuration PROM has been erased, the bit file containing the test design is available on the Design Resource Center web site: www.em.avnet.com/drc. The Flash can be re-programmed by using the Xilinx iMPACT software. The bit file will have to be converted into an MCS file format using iMPACT.

The Ethernet and Factory test designs available on the DRC web site use a terminal session as the user interface. Using a straight-through serial cable, connect the Spartan-6 LX150T development board to a PC. Open a terminal session and configure it for 19200 baud, 8 data bits, no parity, 1 stop bit and no flow control (19200-8-N-1-N).

3.1 Factory Test

The Factory Test verifies the electrical connectivity of the DDR3 SDRAM, flash memory, FMC LPC Connectors, and the user LEDs and switches. The user can initiate the tests by typing ‗test <enter>‘ in a terminal session configured as shown in Section 3.0 (19200-8-N-1-N). Some of the tests require user inputs and observation (watching the LEDs and pressing the switches). Some of the tests require special test fixtures and/or apparatus for the tests to complete that are not included in the Spartan-6 LX150T Development Board kit. The cumulative results are displayed at the completion of test processes. Individual tests can be executed by typing ―help‖ at the prompt and then typing the proper command for the desired test.

3.2 Ethernet Test

The Ethernet Test design provides the user with the ability to ping the Spartan-6 LX150T development board to verify network connectivity via the on-board National 10/100/1000 Mbps Ethernet PHY. The National PHY supports auto-MDIX mode, which allows either a straight-through or a cross-over Ethernet cable to be used. The default IP address of the board is 192.168.1.44. To ping the board, plug an Ethernet cable into the RJ45 connector labeled ―J1‖. Then change the IP address of the board to match the subnet of the PC or network it‘s connected to using a terminal program configured as shown in Section 3.0 (19200-8-N-1-N). At the prompt, type ‗i‘ and then enter the new IP address for the board (first three fields must match the IP address of the PC: MMM.MMM.MMM.xxx; the last field must be different). Use periods ‗.‘ between fields and hit the <enter> key when finished. Then open a command shell on the PC (Start Menu -> Run, cmd) and type ‗ping MMM.MMM.MMM.xxx‘. You should see four replies to the ping request.




4.0 Revisions V1.0 Initial release for production board (BD-S6DEV-LX150T-G Revision C) March 10, 2010

V1.0 Initial release for production board (BD-S6DEV-LX150T-G Revision C)

March 10, 2010

V1.1 Added Section 2.2.2.1, Modified table 36, Updated Section 2.12

August 23, 2010

V1.2 Added errata for Section 2.3.4 ―Configuration Flash Memory‖

December 3, 2010


Appendix A

This section provides a description of the jumper settings for the Spartan-6 LX150T development board. The board is ready to use out of the box with the default jumper settings. The following figure depicts a map of the component side of the board with Jumper/Header/Connector locations detailed. The jumper sites are colored pink below.

Spartan-6

LED0 LED7

RJ45

Connector

J1

6-Pin

Power

J16

SFP

Connector

P2

USB

Connector

P1

RS232

P3SD Card

Connector

J7

SW2 SW3 SW4 SW5

SW7

J2

J4

FMC LPC Connector

JX1

JP

6

JP1

SW6

SW

11

SW8

SW10

J12

JP

5

JP

4

JP2

J13 J14 J15

ALI J10

JTAG

(J9)ATX

PWR

(JP7)

Barrel Jack

PWR

J17 (DNP)

SW9

JP3J6

J2

2

J7

USB-

RS232

Connector

JR1

SATA

J3

SW1

JP

8

JP

6

SW12

FMC LPC Connector

JX2

Figure 24 - Board Jumpers, Headers, Connectors

JP2 – Use to select the configuration mode for the FPGA. Default: All Open (Master SelectMap). See section 2.8.1 for more information. JP3 ―FLSH WP‖ – Flash Write-protect Enable, install a shunt in the 2:3 position to protect programmed data in the Flash memory. Default: JP14 1:2, read/write enabled (unprotected). JP8 – Selects the VCCO voltage for Bank 0. This selects the voltage level for the signals connected to the FMC LPC connector JX1. The jumper must be set to 2.5 V for differential signaling. If the signals are being used as single ended then 2.5V or 3.3V can be used. The following figure shows JP8 in its default configuration (FMC1_VIO = 2.5 V).

3.3V

2.5V

JP8

1

3

FMC1_VIO

(Bank 0 VCCO)

Figure 25 - FMC1_VIO “JP8"

JP1 ―PCI_PRSNT‖ – Selects the number of PCI Express lanes to advertise to the host PC. A single jumper is installed to connect the PRSNT1# pin to the PRSNT2# pin that corresponds to the desired lane width (x1 or x4). This allows the user to force fewer lanes to be used to target applications requiring less than 4 lanes. Default: JP1 3:4 (4 lanes). J9 ―JTAG‖ – A ribbon cable connector used by the Xilinx Parallel Cable IV and Platform Cable USB.


J4 ―HSWAP‖ – Enables pull-ups on the Spartan-6 I/O pins during configuration. Install a jumper to enable the configuration pull-ups. Default: Open; pull-ups disabled. J2 ―SFP EN‖ – SFP Enable, install a shunt to enable a module plugged into the Small Form Pluggable (SFP) cage labeled ―P2‖ on the board. Default: Closed (enabled). JP4 and JP7 ―JTAG‖ - These two jumpers work in conjunction with one another to configure the JTAG chain to either include or exclude the FMC LPC connectors JX1 and JX2. The default position, JP4 1:2, includes the two configuration PROMs and the Spartan-6 FPGA. Refer to Section 2.8.2 for more details. JP5 and JP6 ―SCL_AUX‖ and ―SDA_AUX‖ – These two jumpers work in conjunction with one another to configure the I2C bus to either include or exclude the FMC LPC connectors JX1 and JX2. The default position for both jumpers is 2:3, which includes the real time clock, temperature sensor and the ALI interface only. SW1 ―CONFIG‖ – Depressing and releasing this switch will force the FPAG to reconfigure itself in the configuration mode designated by the configuration mode jumper(s) J2. SW12 ―ATX/PCI POWER‖ – this switch allows the user to select which 12 V to draw power from. Either 12 V from the PCI Express card edge or from the 4-pin ATX power connector (JP7) are valid options. If powering the board from the 6-pin connector (J16) then this switch has no function. SW11 – This switch is the main power switch to the board. Regardless of what 12V source is being used to power the board this switch must be ion the ON position to power the board. SW7 – This switch is a master reset switch for the ICS874003-05 jitter attenuator device. Depressing and releasing this switch will reset U13. SW8 ―FS 2-1-0‖ – This 4-position switch is used to configure the output frequency of the ICS874003-05 jitter attenuator. Refer to Section 2.2.2 for more details. SW9 and SW10 ―PR[1:0] and OD[2:0]‖ – These switches control the output frequency of the CDM61002 LVDS clock synthesizer. Refer to section 2.4.1.1 for more details. SW2:5 – These are user push-button switches that can be used as GPIO to the Spartan-6 FPGA. The switch logic level is default LOW until the switch is depressed. When depressed, the logic level to the IO pin is HIGH (3.3 V). SW6 – This eight position dip-switch can be used as GPIO to the Spartan-6 FPGA. The switch(s) logic level is default LOW until the switch is toggled. When toggled ON, the logic level to the IO pin is HIGH (3.3 V).

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