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Version DateV1.0 7/29/2013

Revised ItemInitial release

Connector Model SOM-5894 A101-4Type 6 Rev. 2.1

System I/O A-B

A-B 0 / 1 0 / 1 A-B 0 / 1 0 / 1 NAA-B NA 0 / 1

A-B NA 0 / 1 A-B NA NA 0A-B 0 / 1 NA 0A-B 0 / 2 0 / 2 A-B 0 / 1 0 / 1 NAA-BA-B 0 / 2 NA NAA-B 0 / 1 0 / 1

A-B 4 / 8 4 / 8 A-B 0 / 1 0 / 1 0A-B 1 / 1 1 / 1 1(I217)A-B 1 / 2 A-B 1 / 1 1 / 1

A-B 1 / 2 1 / 2

C-D

NA 0 / 16

NA 0 / 1 NA NA 0NANA NA 0NA NA 0NA NA 0

C-D NA NA 0C-D NA NA 0C-D NA 0 / 3 C-D NA 0 / 4

A-B

0 / 1 0 / 1 0 4 / 4 4 / 4 4(IT8518E) 4 / 4 4 / 4 4(IT8518E)

A-B 1 / 1 1 / 1

A-B 1 / 1 1 / 1 1(IT8518E)A-B 0 / 1 0 / 1 1(IT8518E)A-B 1 / 1 1 / 1

A-B

A-B 1 / 1 1 / 1 Power Management

A-B 0 / 1 0 / 1 1(IT8518E)A-B 0 / 1 0 / 1 1(IT8518E)A-B NA NA 0A-B NA NA 0

A-B 0 / 3 0 / 3

A-B 1 / 1 1 / 1 1(IT8518E)

Type 10 Rev. 2.1Min / Max

Type 6 Rev. 2.1Min / Max

PCI Express Lanes 0 - 5 1 / 4 1 / 6 6(LynxPoint-M)

LVDS Channel A 1(CH7511) eDP on LVDS Channel A LVDS Channel B 1(CH7511)

VGA Port 1(LynxPoint-M) TV-Out Display Port InterfaceDDI 0 Serial Ports 1 -2 2(IT8518E) CAN interface on SER1 SATA / SAS Ports 1 / 2 1 / 4 4(LynxPoint-M) USB 3.0 Ports AC’97 / HDA Digital Interface 1(LynxPoint-M)

USB 2.0 Ports 8(LynxPoint-M) USB Client LAN 0 (10/100Base-T min) Express Card Support 0 / 2 2(IT8518E) LPC Bus 1(LynxPoint-M)

SPI 1(LynxPoint-M)

PCI Express Lanes 16-31 16(Haswell-Mbl+ECC)

PCI Express Graphics (PEG) 1(Hswell-Mbl) SDVO Channels 1-2 (muxed on PEG) PCI Express Lanes 6-15 0 / 2 1(LynxPoint-M) DVO Channels HDMI/DVI-D Channels DisplayPort Channels PCI Bus - 32 Bit PATA Port DisplayPort InterfaceDDI 1-3 3(LynxPoint-M)

USB 3.0 Ports 4(LynxPoint-M) System Management

SDIO (muxed on GPIO) General Purpose Inputs

General Purpose Outputs

SMBus 1(LynxPoint-M)

I2C

Watch Dog Timer

Speaker Out 1(LynxPoint-M)

External BIOS ROM support 0 / 2 0 / 2 2(LynxPoint-M)

Reset Functions 1(LynxPoint-M)

Thermal Protection

Battery Low Alarm Suspend Wake

Suspend/Wake 3(IT8518E/LynxPoint-M)

Power Button Support

A-B 1 / 1 1 / 1 1(IT8518E)A-B 4 / 4 4 / 4 4A-B 0 / 1 0 / 1 1(IT8518E)A-B 0 / 1 0 / 1 1(IT8518E)A-B 0 / 2 0 / 2 2(IT8518E)A-B 0 / 1 0 / 1

PowerA-B 12 / 12 12 / 12 12C-D 12 / 12 12 / 12 12

Power Good VCC_5V_SBY Contacts Sleep Inputs

Lid Inputs

Fan Control Signals

Trusted Platform Modules 1(SLB9635TT1.2)

VCC_12V Contacts VCC_12V Contacts

modules. Features identified up to Maximum (Max) may be additionally implemented by a module.

LayerMaterial

Signal-End Signals Signal-End Signals Signal-End Signals

No Type Impedance (Ω) Impedance (Ω)

Solder mask 0.5 4.2

L1 Signals Plating 1.0 4.2 6.5/8 48+/-10% 6/8 50+/-10% 5/7Copper Foil (0.5 Oz) 0.7 Prepreg 4.0 4.2

L2 Ground Copper Foil (1.0 Oz.) 1.2 3.9Core 47.6 3.9

L3 Power Copper Foil (1.0 Oz.) 1.2 3.9Prepreg 4.0 4.2

L4 SignalsCopper Foil (0.5 Oz) 0.7

4.2 6.5/8 48+/-10% 6/8 50+/-10% 5/7Plating 1.0

Solder mask 0.5 4.2Board Thickness (mil) 61.4Total Thickness (mil) 62.4Total Thickness (mm) 1.58

Thickness(mil)

Dielectric Constant(Er) Width/Space

(mil)Width/Space

(mil)Width/Space

(mil)

L1 Signal Layer

Prepreg

L2 Ground Layer

Core

L3 Power Layer

Prepreg

L4 Signal Layer

TotalThickness

62 mils

62 mils

Signal-End Signals Signal-End Signals Differential Signals Differential Signals Differential Signals Differential Signals

Impedance (Ω) Impedance (Ω) Impedance (Ω) Impedance (Ω) Impedance (Ω)

55+/-10% 4/6 60+/-10% 5/6 5/10 6/6.5 6/9

55+/-10% 4/6 60+/-10% 5/6 5/10 6/6.5 6/9

Width/Space (mil)

Width/Space (mil)

Width/Space (mil)

Width/Space (mil)

Width/Space (mil)

SE - 55+/-10%DP - 90+/-10%

SE - 55+/-10%DP - 100+/-10%

SE - 50+/-10%DP - 85+/-10%

SE - 55+/-10%DP - 90+/-10%

SE - 55+/-10%DP - 100+/-10%

SE - 50+/-10%DP - 85+/-10%

L1 Signal Layer

Prepreg

L2 Ground Layer

Core

L3 Power Layer

Prepreg

L4 Signal Layer

TotalThickness

62 mils

62 mils

Differential Signals Differential Signals

Impedance (Ω) Impedance (Ω)

6.5/6.5

6.5/6.5

Width/Space (mil)

SE - 50+/-10%DP - 90+/-10%

SE - 48+/-10%DP - 80+/-10%

SE - 50+/-10%DP - 90+/-10%

SE - 48+/-10%DP - 80+/-10%

LayerMaterial

Signal-End Signals Signal-End Signals Signal-End Signals

No Type Impedance (Ω) Impedance (Ω)

Solder mask 0.5 4.2

L1 Signals Plating 1.0 4.2 6.5/8 48+/-10% 6/8 50+/-10% 5/7Copper Foil (0.5 Oz) 0.7 Prepreg 4.0 4.2

L2 Ground Copper Foil (1.0 Oz.) 1.2 3.9Core 4.0 3.9

L3 IN1 Copper Foil (1.0 Oz.) 1.2 3.9 6.5/8 48+/-10% 6/8 50+/-10% 5/7

Prepreg 38.0 3.9

L4 IN2 Copper Foil (1.0 Oz.) 1.2 3.9 6.5/8 48+/-10% 6/8 50+/-10% 5/7

Core 4.0 3.9L5 Power Copper Foil (1.0 Oz.) 1.2 3.9

Prepreg 4.0 4.2

L6 SignalsCopper Foil (0.5 Oz) 0.7

4.2 6.5/8 48+/-10% 6/8 50+/-10% 5/7Plating 1.0

Solder mask 0.5 4.2Board Thickness (mil) 62.2 Total Thickness (mil) 63.2 Total Thickness (mm) 1.61

Thickness(mil)

Dielectric Constant(Er) Width/Space

(mil)Width/Space

(mil)Width/Space

(mil)

Signal-End Signals Signal-End Signals Differential Signals Differential Signals Differential Signals Differential Signals

Impedance (Ω) Impedance (Ω) Impedance (Ω) Impedance (Ω) Impedance (Ω)

55+/-10% 4/6 60+/-10% 5/6 5/10 6/6.5 6/9

55+/-10% 4/6 60+/-10% 5/6 5/10 6/10 6/17

55+/-10% 4/6 60+/-10% 5/6 5/10 6/10 6/17

55+/-10% 4/6 60+/-10% 5/6 5/10 6/6.5 6/9

Width/Space (mil)

Width/Space (mil)

Width/Space (mil)

Width/Space (mil)

Width/Space (mil)

SE - 55+/-10%DP - 90+/-10%

SE - 55+/-10%DP - 100+/-10%

SE - 50+/-10%DP - 85+/-10%

SE - 55+/-10%DP - 90+/-10%

SE - 55+/-10%DP - 100+/-10%

SE - 50+/-10%DP - 85+/-10%

SE - 55+/-10%DP - 90+/-10%

SE - 55+/-10%DP - 100+/-10%

SE - 50+/-10%DP - 85+/-10%

SE - 55+/-10%DP - 90+/-10%

SE - 55+/-10%DP - 100+/-10%

SE - 50+/-10%DP - 85+/-10%

Differential Signals Differential Signals

Impedance (Ω) Impedance (Ω)

6.5/6.5

6.5/8

6.5/8

6.5/6.5

Width/Space (mil)

SE - 50+/-10%DP - 90+/-10%

SE - 48+/-10%DP - 80+/-10%

SE - 50+/-10%DP - 90+/-10%

SE - 48+/-10%DP - 80+/-10%

SE - 50+/-10%DP - 90+/-10%

SE - 48+/-10%DP - 80+/-10%

SE - 50+/-10%DP - 90+/-10%

SE - 48+/-10%DP - 80+/-10%

Row A Type 10 Rev. 2.1 Type 6 Rev. 2.1 A1 GND (FIXED) Option GND (FIXED) A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 GND (FIXED) GND (FIXED) A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 GND (FIXED) GND (FIXED) A22

A23

A24

A25

A26

A27 A28 A29

A30 A31 GND (FIXED) GND (FIXED) A32

A33 A34 A35

A36

A37

A38

A39


A43

A44

A45

A46

A47

GBE0_MDI3- GBE0_MDI3- GBE0_MDI3+ GBE0_MDI3+ GBE0_LINK100# GBE0_LINK100# GBE0_LINK1000# GBE0_LINK1000# GBE0_MDI2- GBE0_MDI2- GBE0_MDI2+ GBE0_MDI2+ GBE0_LINK# GBE0_LINK# GBE0_MDI1- GBE0_MDI1- GBE0_MDI1+ GBE0_MDI1+

GBE0_MDI0- GBE0_MDI0- GBE0_MDI0+ GBE0_MDI0+ GBE0_CTREF GBE0_CTREF SUS_S3# SUS_S3# SATA0_TX+ SATA0_TX+ SATA0_TX- SATA0_TX- SUS_S4# SUS_S4# SATA0_RX+ SATA0_RX+ SATA0_RX- SATA0_RX-

USB_SSRX0- SATA2_TX+

USB_SSRX0+ SATA2_TX-

SUS_S5# SUS_S5#

USB_SSRX1- SATA2_RX+

USB_SSRX1+ SATA2_RX-

BATLOW# BATLOW# (S)ATA_ACT# (S)ATA_ACT# AC/HDA_SYNC AC/HDA_SYNC

AC/HDA_RST# AC/HDA_RST#

AC/HDA_BITCLK AC/HDA_BITCLK

AC/HDA_SDOUT AC/HDA_SDOUT BIOS_DIS0# BIOS_DIS0# THRMTRIP# THRMTRIP#

USB6- USB6-

USB6+ USB6+

USB_6_7_OC# USB_6_7_OC#

USB4- USB4-

USB4+ USB4+

USB2- USB2-

USB2+ USB2+


USB0- USB0-

USB0+ USB0+

VCC_RTC VCC_RTC

A48

A49

A50 A51 GND (FIXED) GND (FIXED) A52 RSVD

A53 RSVD

A54 SDIO_DAT0

A55 RSVD

A56 RSVD A57 GND GND A58


A62

A63 SDIO_DAT1

GND GND SDIO_DAT2

GND (FIXED) GND (FIXED)

eDP_VDD_EN


A82

A83

A84

A85 SDIO_DAT3

A86 RSVD RSVD

A87

A88

A89

EXCD0_PERST# EXCD0_PERST#

EXCD0_CPPE# EXCD0_CPPE#

LPC_SERIRQ LPC_SERIRQ

PCIE_TX5+

PCIE_TX5-

GPI0 GPI0

PCIE_TX4+

PCIE_TX4-

PCIE_TX3+ PCIE_TX3+

PCIE_TX3- PCIE_TX3-

PCIE_TX2+ PCIE_TX2+

PCIE_TX2- PCIE_TX2-

GPI1 GPI1

A64 PCIE_TX1+ PCIE_TX1+

A65 PCIE_TX1- PCIE_TX1- A66 A67 GPI2 GPI2

A68 PCIE_TX0+ PCIE_TX0+

A69 PCIE_TX0- PCIE_TX0- A70 A71 LVDS_A0+ eDP_TX2+ LVDS_A0+

A72 LVDS_A0- eDP_TX2- LVDS_A0-

A73 LVDS_A1+ eDP_TX1+ LVDS_A1+


A75 LVDS_A2+ eDP_TX0+ LVDS_A2+


A77 LVDS_VDD_EN LVDS_VDD_EN

A78 LVDS_A3+ LVDS_A3+

A79 LVDS_A3- LVDS_A3- A80 A81 LVDS_A_CK+ eDP_TX3+ LVDS_A_CK+

LVDS_A_CK- eDP_TX3- LVDS_A_CK-

LVDS_I2C_CK eDP_AUX+ LVDS_I2C_CK

LVDS_I2C_DAT eDP_AUX- LVDS_I2C_DAT

GPI3 GPI3

eDP_HPD eDP_HPD

PCIE_CLK_REF+ PCIE_CLK_REF+

PCIE_CLK_REF- PCIE_CLK_REF-

A90 GND (FIXED) GND (FIXED) A91 A92 A93 SDIO_CLK A94 A95 A96 A97 A98 A99 A100 GND (FIXED) GND (FIXED) A101 A102 A103 A104 A105 A106 A107 A108 A109 A110 GND (FIXED) GND (FIXED)

SPI_POWER SPI_POWER SPI_MISO SPI_MISO GPO0 GPO0 SPI_CLK SPI_CLK SPI_MOSI SPI_MOSI TPM_PP TPM_PP TYPE10# TYPE10# SER0_TX SER0_TX SER0_RX SER0_RX

SER1_TX CAN_TX SER1_TX SER1_RX CAN_RX SER1_RX LID# LID# VCC_12V VCC_12V VCC_12V VCC_12V VCC_12V VCC_12V VCC_12V VCC_12V VCC_12V VCC_12V VCC_12V VCC_12V

should be no connect.

Type 6 Rev. 2.1 I/F SOM-5894 A101-4Option PWR GND (FIXED)

GBE GBE0_MDI3- GBE GBE0_MDI3+ GBE GBE0_LINK100# GBE GBE0_LINK1000# GBE GBE0_MDI2- GBE GBE0_MDI2+ GBE GBE0_LINK# GBE GBE0_MDI1- GBE GBE0_MDI1+ PWR GND (FIXED) GBE GBE0_MDI0- GBE GBE0_MDI0+ GBE N/APSM SUS_S3#

SATA0 SATA0_TX+ SATA0 SATA0_TX- PSM SUS_S4#

SATA0 SATA0_RX+ SATA0 SATA0_RX- PWR GND (FIXED)

SATA2 SATA2_TX+ SATA2 SATA2_TX- PSM SUS_S5#

SATA2 SATA2_RX+ SATA2 SATA2_RX- PSM BATLOW# SATAAC97

AC97PWR GND (FIXED) AC97

AC97MISC BIOS_DIS0# PSM THRMTRIP# USB6 USB6- USB6 USB6+

USB_6_7 USB_6_7_OC# USB4 USB4- USB4 USB4+ PWR GND (FIXED) USB2 USB2- USB2 USB2+

USB_2_3 USB_2_3_OC# USB0 USB0- USB0 USB0+ PWR VCC_RTC

(S)ATA_ACT#

AC/HDA_SYNC

AC/HDA_RST#

AC/HDA_BITCLK

AC/HDA_SDOUT

EXCD0 EXCD0_PERST# EXCD0 EXCD0_CPPE#

LPC LPC_SERIRQ PWR GND (FIXED) PCIE PCIE_TX5+ PCIE PCIE_TX5-

SDIO_DAT0 GPIO GPI0 PCIE PCIE_TX4+ PCIE PCIE_TX4- PWR GND PCIE PCIE_TX3+ PCIE PCIE_TX3- PWR GND (FIXED) PCIE PCIE_TX2+ PCIE PCIE_TX2-

SDIO_DAT1 GPIO GPI1 PCIE PCIE_TX1+PCIE PCIE_TX1-PWR GND

SDIO_DAT2 GPIO GPI2PCIE PCIE_TX0+PCIE PCIE_TX0-PWR GND (FIXED) LVDS LVDS_A0+LVDS LVDS_A0-LVDS LVDS_A1+LVDS LVDS_A1-LVDS LVDS_A2+LVDS LVDS_A2-

eDP_VDD_EN LVDS LVDS_VDD_ENLVDS LVDS_A3+LVDS LVDS_A3-PWR GND (FIXED) LVDS LVDS_A_CK+LVDS LVDS_A_CK- LVDS LVDS_I2C_CK LVDS LVDS_I2C_DAT

SDIO_DAT3 GPIO GPI3 RSVD

RSVD

PCIE PCIE_CLK_REF+ PCIE PCIE_CLK_REF-

eDP_TX2+

eDP_TX2-

eDP_TX1+

eDP_TX1-

eDP_TX0+

eDP_TX0-

eDP_TX3+

eDP_TX3-

eDP_AUX+

eDP_AUX-

RSVD(KBD_RST# if R240 stuffed) DP1_HPD add R241 0 OHM

PWR GND (FIXED) SPI SPI_POWERSPI SPI_MISO

SDIO_CLK GPIO GPO0 SPI SPI_CLKSPI SPI_MOSI

MISC TPM_PPMTD TYPE10# GPSI SER0_TXGPSI SER0_RX PWR GND (FIXED) GPSI SER1_TX GPSI SER1_RXPSM LID#PWRPWRPWRPWRPWRPWRPWR GND (FIXED)

CAN_TX CAN_RX

VCC_12V VCC_12V VCC_12V VCC_12V VCC_12V VCC_12V

Row B Type 10 Rev. 2.1 Type 6 Rev. 2.1 B1 GND (FIXED) Option GND (FIXED) B2

B3

B4

B5

B6

B7

B8

B9

B10 B11 GND (FIXED) GND (FIXED) B12

B13

B14

B15

B16

B17

B18

B19


B23

B24

B25

B26

B27

B28

B29


B33

B34

B35

B36

B37

B38

B39


GBE0_ACT# GBE0_ACT#

LPC_FRAME# LPC_FRAME#

LPC_AD0 LPC_AD0

LPC_AD1 LPC_AD1

LPC_AD2 LPC_AD2

LPC_AD3 LPC_AD3

LPC_DRQ0# LPC_DRQ0#

LPC_DRQ1# LPC_DRQ1#

LPC_CLK LPC_CLK

PWRBTN# PWRBTN#

SMB_CK SMB_CK

SMB_DAT SMB_DAT

SMB_ALERT# SMB_ALERT#

SATA1_TX+ SATA1_TX+

SATA1_TX- SATA1_TX-

SUS_STAT# SUS_STAT#

SATA1_RX+ SATA1_RX+

SATA1_RX- SATA1_RX-

USB_SSTX0- SATA3_TX+

USB_SSTX0+ SATA3_TX-

PWR_OK PWR_OK

USB_SSTX1- SATA3_RX+

USB_SSTX1+ SATA3_RX-

WDT WDT

AC/HDA_SDIN2 AC/HDA_SDIN2



SPKR SPKR

I2C_CK I2C_CK

I2C_DAT I2C_DAT

THRM# THRM#

USB7- USB7-

USB7+ USB7+


USB5- USB5-

USB5+ USB5+

USB3- USB3-

B43

B44

B45

B46

B47

B48

B49

B50 B51 GND (FIXED) GND (FIXED) B52 RSVD

B53 RSVD

B54 SDIO_CMD

B55 RSVD

B56 RSVD

B57 SDIO_WP

B58


B62

B63 SDIO_CD#

GND (FIXED) GND (FIXED) DDI0_PAIR0+

DDI0_PAIR0-

DDI0_PAIR1+

DDI0_PAIR1-

DDI0_PAIR2+

DDI0_PAIR2-

DDI0_PAIR4+

DDI0_PAIR4-

GND (FIXED) GND (FIXED) DDI0_PAIR3+

B82 DDI0_PAIR3-

B83

B84

B85

USB3+ USB3+


USB1- USB1-

USB1+ USB1+

EXCD1_PERST# EXCD1_PERST#

EXCD1_CPPE# EXCD1_CPPE#

SYS_RESET# SYS_RESET#

CB_RESET# CB_RESET#

PCIE_RX5+

PCIE_RX5-

GPO1 GPO1

PCIE_RX4+

PCIE_RX4-

GPO2 GPO2

PCIE_RX3+ PCIE_RX3+

PCIE_RX3- PCIE_RX3-

PCIE_RX2+ PCIE_RX2+

PCIE_RX2- PCIE_RX2-

GPO3 GPO3

B64 PCIE_RX1+ PCIE_RX1+

B65 PCIE_RX1- PCIE_RX1-

B66 WAKE0# WAKE0#

B67 WAKE1# WAKE1#

B68 PCIE_RX0+ PCIE_RX0+

B69 PCIE_RX0- PCIE_RX0- B70 B71 LVDS_B0+

B72 LVDS_B0-

B73 LVDS_B1+

B74 LVDS_B1-

B75 LVDS_B2+

B76 LVDS_B2-

B77 LVDS_B3+

B78 LVDS_B3-

B79 LVDS_BKLT_EN eDP_BKLT_EN LVDS_BKLT_EN B80 B81 LVDS_B_CK+

LVDS_B_CK-

LVDS_BKLT_CTRL eDP_BKLT_CTRL LVDS_BKLT_CTRL

VCC_5V_SBY VCC_5V_SBY


B86

B87 B88 B89 DDI0_HPD B90 GND (FIXED) GND (FIXED) B91 DDI0_PAIR5+

B92 DDI0_PAIR5-

B93 DDI0_PAIR6+

B94 DDI0_PAIR6-

B95

B96 B97 B98 DDI0_CTRLCLK_AUX+ B99 DDI0_CTRLDATA_AUX- RSVD B100 GND (FIXED) GND (FIXED) B101 B102 B103 B104

B105

B106

B107

B108

B109 B110 GND (FIXED) GND (FIXED)


VCC_5V_SBY VCC_5V_SBY BIOS_DIS1# BIOS_DIS1#

VGA_RED

VGA_GRN

VGA_BLU

VGA_HSYNC

VGA_VSYNC

DDI0_DDC_AUX_SEL VGA_I2C_CK

USB_HOST_PRSNT VGA_I2C_DAT SPI_CS# SPI_CS#

RSVD

FAN_PWMOUT FAN_PWMOUT FAN_TACHIN FAN_TACHIN SLEEP# SLEEP# VCC_12V VCC_12V

VCC_12V VCC_12V

VCC_12V VCC_12V

VCC_12V VCC_12V

VCC_12V VCC_12V

VCC_12V VCC_12V

should be no

Type 6 Rev. 2.1 I/F SOM-5894 A101-4Option PWR GND (FIXED)

GBE GBE0_ACT# LPC LPC_FRAME# LPC LPC_AD0 LPC LPC_AD1 LPC LPC_AD2 LPC LPC_AD3 LPC LPC_DRQ0# LPC LPC_DRQ1# LPC LPC_CLK PWR GND (FIXED)

PSM PWRBTN# PSM SMB_CK PSM SMB_DAT PSM SMB_ALERT#

SATA1 SATA1_TX+ SATA1 SATA1_TX- PSM SUS_STAT#

SATA1 SATA1_RX+ SATA1 SATA1_RX- PWR GND (FIXED)

SATA3 SATA3_TX+ SATA3 SATA3_TX- PSM PWR_OK

SATA3 SATA3_RX+ SATA3 SATA3_RX- MISC WDT AC97

AC97

AC97PWR GND (FIXED)

MISC SPKR MISC I2C_CK MISC I2C_DAT PSM THRM# USB7 USB7- USB7 USB7+

USB_4_5 USB_4_5_OC# USB5 USB5- USB5 USB5+ PWR GND (FIXED)

USB3 USB3-

AC/HDA_SDIN2

AC/HDA_SDIN1

AC/HDA_SDIN0

USB3 USB3+ USB_0_1 USB_0_1_OC#

USB1 USB1- USB1 USB1+

EXCD1 EXCD1_PERST# EXCD1 EXCD1_CPPE#

PSM SYS_RESET# PSM CB_RESET# PWR GND (FIXED)

PCIE PCIE_RX5+ PCIE PCIE_RX5-

SDIO_CMD GPIO GPO1 PCIE PCIE_RX4+ PCIE PCIE_RX4-

SDIO_WP GPIO GPO2 PCIE PCIE_RX3+ PCIE PCIE_RX3- PWR GND (FIXED)

PCIE PCIE_RX2+ PCIE PCIE_RX2-

SDIO_CD# GPIO GPO3 PCIE PCIE_RX1+PCIE PCIE_RX1-PSM WAKE0#PSM WAKE1#PCIE PCIE_RX0+PCIE PCIE_RX0-PWR GND (FIXED)

DDI0/LVDS LVDS_B0+DDI0/LVDS LVDS_B0-DDI0/LVDS LVDS_B1+DDI0/LVDS LVDS_B1-DDI0/LVDS LVDS_B2+DDI0/LVDS LVDS_B2-DDI0/LVDS LVDS_B3+DDI0/LVDS LVDS_B3-

LVDS LVDS_BKLT_ENPWR GND (FIXED)

DDI0/LVDS LVDS_B_CK+DDI0/LVDS LVDS_B_CK-

LVDS LVDS_BKLT_CTRL PWR VCC_5V_SBY PWR VCC_5V_SBY

eDP_BKLT_EN

eDP_BKLT_CTRL

PWR VCC_5V_SBY PWR VCC_5V_SBY MISC BIOS_DIS1#

DDI0/VGA VGA_RED PWR GND (FIXED)

DDI0/VGA VGA_GRN DDI0/VGA VGA_BLU DDI0/VGA VGA_HSYNC DDI0/VGA VGA_VSYNC DDI0/VGA VGA_I2C_CK DDI0/VGA VGA_I2C_DAT

SPI SPI_CS# DDI0DDI0 RSVD PWR GND (FIXED) PSM FAN_PWMOUTPSM FAN_TACHINPSM SLEEP# PWR VCC_12V PWR VCC_12V PWR VCC_12V PWR VCC_12V PWR VCC_12V PWR VCC_12V PWR GND (FIXED)

RSVD

Row C Type 2 Rev. 2.0 Type 6 Rev. 2.0 C1 GND (FIXED) GND (FIXED) SDVO C2 GND C3 C4 C5 GND C6 C7 C8 GND C9 C10 C11 GND (FIXED) GND (FIXED) C12 C13 C14 GND C15 DDI1_PAIR6+ C16 DDI1_PAIR6- C17 RSVD C18 RSVD C19 C20 C21 GND (FIXED) GND (FIXED) C22 C23 C24 DDI1_HPD C25 DDI1_PAIR4 + C26 DDI1_PAIR4- C27 RSVD C28 RSVD C29 DDI1_PAIR5+ C30 DDI1_PAIR5- C31 GND (FIXED) GND (FIXED) C32 DDI2_CTRLCLK_AUX+ C33 DDI2_CTRLDATA_AUX- C34 C35 RSVD C36 DDI3_CTRLCLK_AUX+ C37 DDI3_CTRLDATA_AUX- C38 C39 DDI3_PAIR0+ C40 DDI3_PAIR0- C41 GND (FIXED) GND (FIXED) C42 DDI3_PAIR1+ C43 DDI3_PAIR1- C44 DDI3_HPD C45 RSVD C46 DDI3_PAIR2+ C47 DDI3_PAIR2- C48 RSVD C49 DDI3_PAIR3+ C50 DDI3_PAIR3- C51 GND (FIXED) GND (FIXED) C52

C53

IDE_D7 IDE_D6 USB_SSRX0- IDE_D3 USB_SSRX0+ IDE_D15 IDE_D8 USB_SSRX1- IDE_D9 USB_SSRX1+ IDE_D2 IDE_D13 USB_SSRX2- IDE_D1 USB_SSRX2+

IDE_D14 USB_SSRX3- IDE_IORDY USB_SSRX3+ IDE_IOR# PCI_PME# SDVO1_FLDSTALL+ PCI_GNT2# SDVO1_FLDSTALL- PCI_REQ2# PCI_GNT1# PCI_REQ1# PCIE_RX6+ PCI_GNT0# PCIE_RX6-

PCI_REQ0# PCIE_RX7+ PCI_RESET# PCIE_RX7- PCI_AD0 PCI_AD2 SDVO1_INT+ PCI_AD4 SDVO1_INT- PCI_AD6 PCI_AD8 PCI_AD10 SDVO1_TVCLKIN+ PCI_AD12 SDVO1_TVCLKIN-

PCI_AD14 PCI_C/BE1# PCI_PERR# DDI2_DDC_AUX_SEL PCI_LOCK# PCI_DEVSEL# PCI_IRDY# PCI_C/BE2# DDI3_DDC_AUX_SEL PCI_AD17 PCI_AD19

PCI_AD21 PCI_AD23 PCI_C/BE3# PCI_AD25 PCI_AD27 PCI_AD29 PCI_AD31 PCI_IRQA# PCI_IRQB#

PEG_RX0+ PEG_RX0+

PEG_RX0- PEG_RX0-

C54 C55

C56 C57 C58

C59 C60 GND (FIXED) GND (FIXED) C61

C62 C63 RSVD RSVD

RSVD RSVD

RSVD RSVD


GND

GND GND RSVD RSVD


C82 C83 RSVD RSVD C84 GND GND C85

C86 C87 GND GND C88

C89 C90 GND (FIXED) GND (FIXED) C91

C92 C93 GND GND C94

C95 C96 GND GND C97 RSVD RSVD C98

C99

TYPE0# TYPE0# PEG_RX1+ PEG_RX1+

PEG_RX1- PEG_RX1- TYPE1# TYPE1# PEG_RX2+ PEG_RX2+

PEG_RX2- PEG_RX2-

PEG_RX3+ PEG_RX3+

PEG_RX3- PEG_RX3-

C64 C65 PEG_RX4+ PEG_RX4+

C66 PEG_RX4- PEG_RX4- C67 C68 PEG_RX5+ PEG_RX5+


C72 PEG_RX6- PEG_RX6- C73 SDVO_DATA C74 PEG_RX7+ PEG_RX7+

C75 PEG_RX7- PEG_RX7- C76 C77 C78 PEG_RX8+ PEG_RX8+


PEG_RX9- PEG_RX9-

PEG_RX10+ PEG_RX10+

PEG_RX10- PEG_RX10-

PEG_RX11+ PEG_RX11+

PEG_RX11- PEG_RX11-

PEG_RX12+ PEG_RX12+

PEG_RX12- PEG_RX12-

PEG_RX13+ PEG_RX13+

PEG_RX13- PEG_RX13-

PEG_RX14+ PEG_RX14+

PEG_RX14- PEG_RX14-

C100 GND (FIXED) GND (FIXED) C101

C102 C103 GND GND C104

C105

C106

C107

C108

C109 C110 GND (FIXED) GND (FIXED) RSVD pins are reserved for future use and should be no connect. Do not tie the RSVD pins together.

PEG_RX15+ PEG_RX15+

PEG_RX15- PEG_RX15-

VCC_12V VCC_12V

VCC_12V VCC_12V

VCC_12V VCC_12V

VCC_12V VCC_12V

VCC_12V VCC_12V

VCC_12V VCC_12V

Type 6 Rev. 2.0 I/F SOM-5894 A101-4 DP HDMI/DVI PWR GND (FIXED)

IDE/PWR GNDIDE/USB USB_SSRX0- IDE/USB USB_SSRX0+ IDE/PWR GND IDE/USB USB_SSRX1- IDE/USB USB_SSRX1+ IDE/PWR GND IDE/USB USB_SSRX2- IDE/USB USB_SSRX2+

PWR GND (FIXED) IDE/USB USB_SSRX3- IDE/USB USB_SSRX3+ IDE/PWR GND PCI/DDI1 NCPCI/DDI1 NC

PCI RSVD PCI RSVD PCI PCIE_RX6+ PCI PCIE_RX6-

PWR GND (FIXED) PCI N/APCI N/A

PCI/DDI1 DDI1_HPD PCI/DDI1 NCPCI/DDI1 NC

PCI RSVD PCI RSVD

PCI/DDI1 NCPCI/DDI1 NC

PWR GND (FIXED) PCI/DDI2 DDI2_CTRLCLK_AUX+ PCI/DDI2 DDI2_CTRLDATA_AUX-PCI/DDI2 DDI2_DDC_AUX_SEL

PCI RSVD PCI/DDI3 DDI3_CTRLCLK_AUX+ PCI/DDI3 DDI3_CTRLDATA_AUX-PCI/DDI3 DDI3_DDC_AUX_SELPCI/DDI3 DDI3_PAIR0+ PCI/DDI3 DDI3_PAIR0-

PWR GND (FIXED) PCI/DDI3 DDI3_PAIR1+ PCI/DDI3 DDI3_PAIR1- PCI/DDI3 DDI3_HPD

PCI RSVD PCI/DDI3 DDI3_PAIR2+ PCI/DDI3 DDI3_PAIR2-


PWR GND (FIXED)

PCIE PEG_RX0+ PCIE PEG_RX0-

DP1_HPD HDMI1_HPD

DP2_AUX+ HDMI2_CTRLCLK DP2_AUX- HDMI2_CTRLDATA

DP3_AUX+ HDMI3_CTRLCLK DP3_AUX- HDMI3_CTRLDATA

DP3_LANE0+ TMDS3_DATA2+ DP3_LANE0- TMDS3_DATA2-

DP3_LANE1+ TMDS3_DATA1+ DP3_LANE1- TMDS3_DATA1- DP3_HPD HDMI3_HPD


DP3_LANE3+ TMDS3_CLK+ DP3_LANE3- TMDS3_CLK-

MTD TYPE0#

PCIE PEG_RX1+PCIE PEG_RX1-MTD TYPE1#

PCIE PEG_RX2+PCIE PEG_RX2-PWR GND (FIXED)

PCIE PEG_RX3+ PCIE PEG_RX3- RSVD RSVD RSVD RSVD

PCIE PEG_RX4+PCIE PEG_RX4-RSVD RSVD


PCIE PEG_RX6+PCIE PEG_RX6-

SDVO/DDI1 GNDPCIE PEG_RX7+PCIE PEG_RX7-PWR GNDRSVD RSVD


PCIE PEG_RX9+PCIE PEG_RX9-RSVD RSVD PWR GND PCIE PEG_RX10+PCIE PEG_RX10-PWR GND PCIE PEG_RX11+PCIE PEG_RX11-PWR GND (FIXED)

PCIE PEG_RX12+PCIE PEG_RX12-PWR GND PCIE PEG_RX13+PCIE PEG_RX13-PWR GND RSVD RSVD

PCIE PEG_RX14+PCIE PEG_RX14-

PWR GND (FIXED)

PCIE PEG_RX15+PCIE PEG_RX15-PWR GND PWR VCC_12V PWR VCC_12V PWR VCC_12V PWR VCC_12V PWR VCC_12V PWR VCC_12V PWR GND (FIXED)

RSVD pins are reserved for future use and should be no connect. Do not tie the RSVD pins together.

Row D Type 2 Rev. 2.0 Type 6 Rev. 2.0 D1 GND (FIXED) GND (FIXED) SDVO D2 GND D3 D4 D5 GND D6 D7 D8 GND D9 D10 D11 GND (FIXED) GND (FIXED) D12 D13 D14 GND D15 DDI1_CTRLCLK_AUX+ D16 DDI1_CTRLDATA_AUX- D17 RSVD D18 RSVD D19 D20 D21 GND (FIXED) GND (FIXED) D22 D23 D24 RSVD D25 RSVD D26 DDI1_PAIR0+ D27 DDI1_PAIR0- D28 RSVD D29 DDI1_PAIR1+ D30 DDI1_PAIR1- D31 GND (FIXED) GND (FIXED) D32 DDI1_PAIR2+ D33 DDI1_PAIR2- D34 D35 RSVD D36 DDI1_PAIR3+ D37 DDI1_PAIR3- D38 RSVD D39 DDI2_PAIR0+ D40 DDI2_PAIR0- D41 GND (FIXED) GND (FIXED) D42 DDI2_PAIR1+ D43 DDI2_PAIR1- D44 DDI2_HPD D45 RSVD D46 DDI2_PAIR2+ D47 DDI2_PAIR2- D48 RSVD D49 DDI2_PAIR3+ D50 DDI2_PAIR3- D51 GND (FIXED) GND (FIXED) D52

D53

IDE_D5 IDE_D10 USB_SSTX0- IDE_D11 USB_SSTX0+ IDE_D12 IDE_D4 USB_SSTX1- IDE_D0 USB_SSTX1+ IDE_REQ IDE_IOW# USB_SSTX2- IDE_ACK# USB_SSTX2+

IDE_IRQ USB_SSTX3- IDE_A0 USB_SSTX3+ IDE_A1 IDE_A2 SDVO1_CTRLCLK IDE_CS1# SDVO1_CTRLDATA IDE_CS3# IDE_RESET# PCI_GNT3# PCIE_TX6+ PCI_REQ3# PCIE_TX6-

PCI_AD1 PCIE_TX7+ PCI_AD3 PCIE_TX7- PCI_AD5 PCI_AD7 PCI_C/BE0# SDVO1_RED+ PCI_AD9 SDVO1_RED- PCI_AD11 PCI_AD13 SDVO1_GRN+ PCI_AD15 SDVO1_GRN-

PCI_PAR SDVO1_BLU+ PCI_SERR# SDVO1_BLU- PCI_STOP# DDI1_DDC_AUX_SEL PCI_TRDY# PCI_FRAME# SDVO1_CK+ PCI_AD16 SDVO1_CK- PCI_AD18 PCI_AD20 PCI_AD22

PCI_AD24 PCI_AD26 PCI_AD28 PCI_AD30 PCI_IRQC# PCI_IRQD# PCI_CLKRUN# PCI_M66EN PCI_CLK

PEG_TX0+ PEG_TX0+

PEG_TX0- PEG_TX0-

D54

D55

D56 D57 D58

D59 D60 GND (FIXED) GND (FIXED) D61

D62 RSVD RSVD RSVD RSVD

GND GND


GND

GND GND RSVD


D82 D83 RSVD RSVD D84 GND GND D85

D86 D87 GND GND D88

D89 D90 GND (FIXED) GND (FIXED) D91

D92 D93 GND GND D94

D95 D96 GND GND D97 D98

D99

PEG_LANE_RV# PEG_LANE_RV#

PEG_TX1+ PEG_TX1+

PEG_TX1- PEG_TX1- TYPE2# TYPE2# PEG_TX2+ PEG_TX2+

PEG_TX2- PEG_TX2-

PEG_TX3+ PEG_TX3+

PEG_TX3- PEG_TX3- D63 D64 D65 PEG_TX4+ PEG_TX4+

D66 PEG_TX4- PEG_TX4- D67 D68 PEG_TX5+ PEG_TX5+


D72 PEG_TX6- PEG_TX6- D73 SDVO_CLK D74 PEG_TX7+ PEG_TX7+

D75 PEG_TX7- PEG_TX7- D76 D77 IDE_CBLID# D78 PEG_TX8+ PEG_TX8+


PEG_TX9- PEG_TX9-

PEG_TX10+ PEG_TX10+

PEG_TX10- PEG_TX10-

PEG_TX11+ PEG_TX11+

PEG_TX11- PEG_TX11-

PEG_TX12+ PEG_TX12+

PEG_TX12- PEG_TX12-

PEG_TX13+ PEG_TX13+

PEG_TX13- PEG_TX13-

PEG_ENABLE# RSVD PEG_TX14+ PEG_TX14+

PEG_TX14- PEG_TX14-

D100 GND (FIXED) GND (FIXED) D101

D102 D103 GND GND D104

D105

D106

D107

D108

D109 D110 GND (FIXED) GND (FIXED) RSVD pins are reserved for future use and should be no connect. Do not tie the RSVD pins together.

PEG_TX15+ PEG_TX15+

PEG_TX15- PEG_TX15-

VCC_12V VCC_12V

VCC_12V VCC_12V

VCC_12V VCC_12V

VCC_12V VCC_12V

VCC_12V VCC_12V

VCC_12V VCC_12V

Type 6 Rev. 2.0 I/F SOM-5894 A101-1 DP HDMI/DVI PWR GND (FIXED)

IDE/PWR GND IDE/USB USB_SSTX0- IDE/USB USB_SSTX0+ IDE/PWR GND IDE/USB USB_SSTX1- IDE/USB USB_SSTX1+ IDE/PWR GND IDE/USB USB_SSTX2- IDE/USB USB_SSTX2+

PWR GND (FIXED) IDE/USB USB_SSTX3- IDE/USB USB_SSTX3+ IDE/PWR GND IDE/DDI1 DDI1_CTRLCLK_AUX+ IDE/DDI1 DDI1_CTRLDATA_AUX-

IDE RSVD IDE RSVD

PCI/PCIE PCIE_TX6+ PCI/PCIE PCIE_TX6-

PWR GND (FIXED) PCI/PCIE N/APCI/PCIE N/A

PCI RSVD PCI RSVD

PCI/DDI1 DDI1_PAIR0+ PCI/DDI1 DDI1_PAIR0-


PWR GND (FIXED) PCI/DDI1 DDI1_PAIR2+ PCI/DDI1 DDI1_PAIR2- PCI/DDI2

PCI RSVD PCI/DDI1 DDI1_PAIR3+ PCI/DDI1 DDI1_PAIR3- PCI/DDI3 RSVD PCI/DDI2 DDI2_PAIR0+ PCI/DDI2 DDI2_PAIR0-

PWR GND (FIXED) PCI/DDI2 DDI2_PAIR1+ PCI/DDI2 DDI2_PAIR1- PCI/DDI2 DDI2_HPD



PWR GND (FIXED)

PCIE PEG_TX0+PCIE PEG_TX0-

DP1_AUX+ HMDI1_CTRLCLK DP1_AUX- HMDI1_CTRLDATA




DDI1_DDC_AUX_SEL



DP2_LANE1+ TMDS2_DATA1+ DP2_LANE1- TMDS2_DATA1- DP2_HPD HDMI2_HPD



PCIE PEG_LANE_RV# PCIE PEG_TX1+PCIE PEG_TX1- MTD TYPE2#

PCIE PEG_TX2+PCIE PEG_TX2-PWR GND (FIXED)

PCIE PEG_TX3+PCIE PEG_TX3-RSVD RSVD RSVD RSVD

PCIE PEG_TX4+PCIE PEG_TX4-PWR GNDPCIE PEG_TX5+PCIE PEG_TX5-PWR GND (FIXED)

PCIE PEG_TX6+PCIE PEG_TX6-

SDVO/DDI1 GNDPCIE PEG_TX7+PCIE PEG_TX7-PWR GNDIDE RSVD

PCIE PEG_TX8+PCIE PEG_TX8-PWR GND (FIXED)

PCIE PEG_TX9+ PCIE PEG_TX9- RSVD RSVD PWR GND PCIE PEG_TX10+ PCIE PEG_TX10- PWR GND PCIE PEG_TX11+PCIE PEG_TX11- PWR GND (FIXED)

PCIE PEG_TX12+ PCIE PEG_TX12- PWR GND PCIE PEG_TX13+ PCIE PEG_TX13- PWR GND PCIE PEG_ENABLE#

PCIE PEG_TX14+ PCIE PEG_TX14-

PWR GND (FIXED)

PCIE PEG_TX15+ PCIE PEG_TX15- PWR GND PWR VCC_12V PWR VCC_12V PWR VCC_12V PWR VCC_12V PWR VCC_12V PWR VCC_12V PWR GND (FIXED)


Pin No. Gigabit Ethernet Description

A12

A13

A9

A6

A7

A2

Pin Type Pwr Rail / Tolerance

PICMG DG 1.0Module

Length[mils]

PICMG DG 1.0Baseboard

Length[mils]

DP - 95 Ω ± 20%SE - 55 Ω ± 15%

GBE0_MDI0-

I/O Analog

3.3V max Suspend

Gigabit Ethernet Controller 0: Media Dependent Interface Differential Pairs 0,1,2,3. The MDI can operate in 1000, 100 and 10 Mbit / sec modes. Some pairs are not used in some modes, per the following:

1000BASE-T 100BASE-TX 10BASE-T MDI[0]± B1_DA± TX± TX± MDI[1]± B1_DB± RX± RX± MDI[2]± B1_DC± MDI[3]± B1_DD±

Spacing - RX and TX pairs (inter-pair) - Min. 50milsfrom high-speed periodic signals - Min. 300milsfrom low-speed non periodic signals - Min. 100milsdigital ground and analog ground plane (between the magnetics Module and RJ45 connector) - Min. 60milsfrom edge of plane - Min. 40milsLength -COM Express Module to the magnetics Module - 5.0 inchesMagnetics Module to RJ45 connector - Max. 1.0 inchesLength matching - differential pairs (intra-pair) - Max. 5milsRX and TX pairs (inter-pair) - Max. 30milsVia Usage - Max. of 2 vias on TX/RX path

GBE0_MDI0+

GBE0_MDI1-

A10 GBE0_MDI1+

GBE0_MDI2-

GBE0_MDI2+

GBE0_MDI3-

A3

B2

A8

A4

A5

A14

CT

I/O Analog

3.3V max Suspend

Gigabit Ethernet Controller 0: Media Dependent Interface Differential Pairs 0,1,2,3. The MDI can operate in 1000, 100 and 10 Mbit / sec modes. Some pairs are not used in some modes, per the following:

1000BASE-T 100BASE-TX 10BASE-T MDI[0]± B1_DA± TX± TX± MDI[1]± B1_DB± RX± RX± MDI[2]± B1_DC± MDI[3]± B1_DD±

Spacing - RX and TX pairs (inter-pair) - Min. 50milsfrom high-speed periodic signals - Min. 300milsfrom low-speed non periodic signals - Min. 100milsdigital ground and analog ground plane (between the magnetics Module and RJ45 connector) - Min. 60milsfrom edge of plane - Min. 40milsLength -COM Express Module to the magnetics Module - 5.0 inchesMagnetics Module to RJ45 connector - Max. 1.0 inchesLength matching - differential pairs (intra-pair) - Max. 5milsRX and TX pairs (inter-pair) - Max. 30milsVia Usage - Max. of 2 vias on TX/RX path

GBE0_MDI3+

GBE0_ACT# OD CMOS

3.3V / 3.3V Suspend Gigabit Ethernet Controller 0 activity indicator, active low.

GBE0_LINK# OD CMOS

3.3V / 3.3V Suspend Gigabit Ethernet Controller 0 link indicator, active low.

GBE0_LINK100# OD CMOS

3.3V / 3.3V Suspend

Gigabit Ethernet Controller 0 100 Mbit / sec link indicator, active low.

GBE0_LINK1000# OD CMOS

3.3V / 3.3V Suspend

Gigabit Ethernet Controller 0 1000 Mbit / sec link indicator, active low.

GBE0_CTREF REF GND min 3.3V max

Reference voltage for Carrier Board Ethernet channel 0 magnetics center tap. The reference voltage is determined by the requirements of the module PHY and may be as low as 0V and as high as 3.3V. The reference voltage output shall be current limited on the module. In the case in which the reference is shorted to ground, the current shall be limited to 250 mA or less.

I/O Analog

GND min 3.3V max Transformer Magnetics Module center taps

External Ethernet magnetics shall be implemented on the Carrier Board.

10/100/1000 Ethernet Insertion Loss Budget

10/100/1000 Ethernet Insertion Loss Budget, 100 MHz Segment Loss (dB) Notes

0.08 0.02 0.15

24.00 Cable and cable connectors, integrated magnetics, per source spec. Total 24.25

ASAP - As short as possibleDP - Differential PairSE - Single End

Intel LAN MDI Differential Trace Calculator Rev1.6

Microstrip trace routing for 10/100/1000BASE-T LAN MDI

LA Up to 3 inches of module trace @ 0.28 dB / GHz / inch LB COM ExpressTM connector at 100 MHz measured value LC Up to 5 inches of Carrier Board trace @ 0.28 dB / GHz / inch LD

COM ExpressTM Ethernet implementations should conform to insertion loss values less than or equal to those shown in the table above. The insertion loss values shown account for frequency dependent material losses only. Cross talk losses are separate from material losses in the Gb Ethernet specification.

“Device Down” implementations, in which the Ethernet target device is implemented on the Carrier Board (for instance, an Ethernet switch), may add the insertion loss for the RJ45 Ethernetjack and integrated magnetics to the Carrier Board budget. This insertion loss value is typically 1 dB. The Carrier Board insertion loss budget then becomes LC + 1 dB, or 1.15 dB.

User adjustable inputs are shown in Blue text, below.Any user adjustable cell fill color that becomes Red is an "out of bounds" value

USER Inputs Condition Description

Er = 4.60

w = 4.00 mils w = trace width

h =

4mils

t =

2.1mils

s = 7.00 mils

L = 0.00 inches L = desired length of trace in inches

w/h = 1Results

*Zdiff =

99.8974535046805

ohms

2 < Er <5

Er value at ~40 MHz, for the dielectric material, which is closest to the trace.For MDI traces, tell your circuit board fab vendor to use an Er value for ~40 MHz. [Do NOT use the Er value for 1 GHz or higher.]

2.4 < h < 13 h = the distance between the adjacent plane layer and the microstrip traces. [It should be between 2.4 mils and 13 mils.]

1.4 < t < 2.3t = trace thickness after plating. After plating, copper thickness is usually 1.4 to 2.3 mils. (Prior to plating, copper is often 0.6 to 0.7 mils.)

s = the edge-to-edge separation between the two traces within a differential pair

0.1 < w/h < 3

93 < Zdiff < 107

Zdiff = the differential impedance of the two adjacent traces. Assumes no additional adjacent metal.Decrease Zdiff - Er↑, w↑, h↓, t↑, s↓Increase Zdiff - Er↓, w↓, h↑, t↓, s↑

0ohms

Trace C =

0

pF

Stripline routing for 10/100/1000BASE-T LAN MDI Traces

User Inputs Condition Description

3.90

3.90

w = 4.00 mils w = trace width

h1 thin = 6.00 mils

h2 thick = 6.00 mils

t = 0.70 mils t = trace thicknesss = 7.00 mils s = the edge-to-edge separation between the two tracesL = 4.00 inches L = length of desired trace

0.05511811023622 OK Zsingle may be valid for t/b<0.25 AND w/(b-t)<0.35

0.333333333333333 OK

Trace RDC = RDC < 2 is functional,RDC < 1.41 is spec compliant

Adjust trace width (w) and separation (s), or other parameters to get Zdiff as close to 100 ohms as the board materials and fab etching process will allow.Decrease RDC - w↑, t↑, L↓

C < 33

Circuit board fab vendors have their own tools for calculating impedance, and may recommend slightly different widths and/or space, etc.Decrease C - Er↓, w↓, h↑, t↓, s↑, L↓

Er1 (Er of thinner dielectric) = 2 < Er < 5 Er value at ~40 MHz, for the 'h1 dielectric material', which is

closest to the trace.Er2 (Er of thicker

dielectric) = 2 < Er < 5 Er value at ~40 MHz, for the 'h2 dielectric material', which is closest to the trace.

w >3

20% h2 thick < h1 thin <= h2 thickh1 thin > 2.3

Must be <= H2 thickness, AND Must be > H2*0.2, AND Must be > 2.3

h1 thin <= h2 thick < 5 * h1 thinh2 thick > 2.3

Must be >= H1 thickness, AND Must be < H1*5, AND Must be > 2.3

0.45 < t < 2.6s > 4

t/b = t/b < 0.25w/(b-t) = w/(b-t) < 0.35

t/(h1+h2+t) = 0.05511811023622OK

Zdiff is valid for t/(h1+h2+t)<0.25 and w/(h1+h2)<0.49

w/(h1+h2) = 0.333333333333333Average Er = 3.9

b (synth) = 12.33 mils

b (synth) = weighted average of h1, h2, & t12.70 If h2 <= 2.55*h1

22.00 If 2.55 < h2 <= 4.25*h1

24.70 If h2 > 4.25*h1

Results

Zsingle = 54.48 ohms

*Zdiff =

101.670774844353ohms

Trace R =

1.17941507311586ohms

Trace Cp =

13.5372320791791

pF

0ohms

1.17942857142857ohms

1.17942857142857ohms

t/(h1+h2+t) < 0.25

w/(h1+h2) < 0.49Weighted average = ((thin Er * thick H2)+(thick Er *thin H1))/(H1+H2)

Zsingle = the calculated, single-ended trace impedance (assuming no adjacent traces or metal)

93 < Zdiff < 107

Zdiff = the differential impedance of the two adjacent traces. Assumes no additional adjacent metal.Decrease Zdiff - Er↑, w↑, h↓, t↑, s↓Increase Zdiff - Er↓, w↓, h↑, t↓, s↑

RDC < 2 is functional,RDC < 1.41 is spec compliant

Decrease R - w↑, t↑, L↓

C < 33 Decrease Cp - Er↓, w↓, h↑, t↓, s↑, L↓

Length vs ResistanceDC

MS Trace RDC = RDC < 2 is functional,RDC < 1.41 is spec compliant

Decrease R - w↑, t↑, L↓SL Trace RDC = RDC < 2 is functional,RDC < 1.41 is spec compliant

MS+SL Trace RDC = RDC < 2 is functional,RDC < 1.41 is spec compliant

D69

t+(((h2/h1)-1)*h1)+((h1+h2)/(h2/h1))

D70

t+1.55*h1+((h1+h2)/(h2/h1))

D71

t+h1+h1+((h1+h2)/(h2/h1))

MS Trace C =

0

pF

SL Trace C =

13.5372320791791

pF

Length vs Capacitance

C < 33

Decrease Cp - Er↓, w↓, h↑, t↓, s↑, L↓

C < 33

MS+SL Trace C =

13.5372320791791

pF

Decrease Cp - Er↓, w↓, h↑, t↓, s↑, L↓

C < 33

6/10/30 6/10/30 612.79 173.34 612.79

6/10/30 6/10/30 586.81 199.95 586.81

6/10/30 6/10/30 628.38 162.63 628.38

6/10/30 6/10/30 628.43 162.04 628.43

6/10/30 6/10/30 590.31 197.07 590.31

6/10/30 6/10/30 589.4 197.33 589.4

6/10/30 6/10/30 630.76 160.04 630.76

SOM-5894 BaseboardWidth/ Space/ Other space [mils]

I217Checklist

Length[mils]

SOM-5894 A101-4Module Inner Length[mils]

SOM-5894 A101-4Module Outer Length[mils]

SOM-5894 A101-4Baseboard Inner

Length[mils]

SOM-5894 A101-4Baseboard Outer

Length[mils]

SOM-5894 A101-4Total Inner

Length[mils]

Inner LayerDP - 100 Ω ± 15%SE - 50Ω ± 10%

Outer LayerDP - 100 Ω ± 15%SE - 50Ω ± 10%

82579LM to RJ-45 w/ Magnetics

Segment Length Matching <10

Segment Length Matching <10

Trace C < 33 pFTrace R < 2 Ω is functional, < 1.41 Ω is spec compliant







6/10/30 6/10/30 626.47 164.17 626.47

6/12/12 6/12/12 ASAP

6/12/12 6/12/12 ASAP

6/12/12 6/12/12 ASAP

6/12/12 6/12/12 ASAP

50/20/20 50/20/20 ASAP

6/12/12 6/12/12 L < 100


J16

0.1uF to center taps

Trace C Trace R

< 33 pF L < 30

612.79 1145.93 4.65 0.24

0.1400000000001

586.81 1145.79 4.49 0.23

628.38 1156.1 4.75 0.25

0.28999999999996

628.43 1155.81 4.75 0.25

590.31 1169.4 4.51 0.23

0

589.4 1169.4 4.50 0.23

630.76 1153 4.77 0.25

0.02999999999997

SOM-5894 A101-4Total Outer

Length[mils]SOM-5894 A101-4Total Length[mils]

Intra-pair Length Matching[mils]

< 2 Ω is functional< 1.41 Ω is spec compliant

626.47 1152.97 4.74 0.25

0.02999999999997

Pin No. Description

A30 6/12/12

6/12/12

A32 6/12/12

A33 6/12/12

B30 6/12/12

B29 6/12/12

B28 6/12/12


AC97 Audio / High Definition Audio Pin Type Pwr Rail /

Tolerance PICMG DG 1.0

Module Length[mils]


Length[mils]SOM-5894 Baseboard

Width/ Space/ Other space [mils]

Inner LayerSE - 50 Ω ± 10%

AC/HDA_RST# O CMOS

3.3V / 3.3V Suspend

Reset output to AC97 CODEC, active low.

A29 AC/HDA_SYNC O CMOS

3.3V / 3.3V

48kHz fixed-rate, sample-synchronization signal to the CODEC(s).

AC/HDA_BITCLK I/O CMOS

3.3V / 3.3V

12.228 MHz serial data clock generated by the external CODEC(s).

AC/HDA_SDOUT O CMOS

3.3V / 3.3V

Serial TDM data output to the CODEC.


AC/HDA_SDIN0 I CMOS

3.3V / 3.3V Suspend

Serial TDM data inputs from CODEC 0.

AC/HDA_SDIN1 I CMOS

3.3V / 3.3V Suspend

Serial TDM data inputs from CODEC 1.

AC/HDA_SDIN2 I CMOS

3.3V / 3.3V Suspend

Serial TDM data inputs CODEC 2.

500 < L < 5000 2000 < L < 17500 L < = 500

6/12/12 2000 < L < 17500 3469.52 3469.52

6/12/12 2000 < L < 17500 3469.98 3469.98

6/12/12 2000 < L < 17500 3566.43 3566.43

6/12/12 2000 < L < 17500 3665.37 3665.37 98.94

500 < L < 7500 1000 < L < 21000 L < = 500

6/12/12 1000 < L < 21000 3469.96 3469.96

6/12/12 1000 < L < 21000 3480.93 3480.93

6/12/12 1000 < L < 21000 3474.92 3474.92


LynxPoint-MChecklist

Length[mils]

SOM-5894 A101-4Module

Length[mils]

SOM-5894 A101-4Baseboard


AC/HDA_SDOUT to

AC/HDA_BITCLK Length

Matching[mils]

SDIN Series Termination to

Codec Length[mils]

Outer LayerSE - 50 Ω ± 15%

LynxPoint-M to Codec


LynxPoint-M to Codec

Pin No. Serial ATA Pin Type Description

A16

A17

A19

A20

B16

B17

B19

B20

A22

A23

A25

Pwr Rail / Tolerance

PICMG DG 1.0Module

Length[mils]


Length[mils]DP - 100 Ω +/-20%SE - 55 Ω +/-15%Total Length - Max 7.0 inches on PCB (COM Express Module and Carrier Board. The length of the SATA cable is specified

SATA0_TX+ O SATA

AC coupled on module

Serial ATA or SAS Channel 0 transmit differential pair.

Length - Max. 2 inches

Spacing -RX and TX pairs (inter-pair) - Min. 20milsfrom high-speed periodic signals - Min. 50milsfrom low-speed non periodic signals - Min. 20milsfrom edge of plane - Min. 40milsLength - Max. 3 inchesLength matching - differential pairs (intra-pair) - Max. 5milsRX and TX pairs (inter-pair) - No strict electrical requirements. Keep difference within a 3.0 inch delta to minimize latency. Do not serpentine to meet trace length guidelines for the RX and TX path.Via Usage - Try to minimize number of viasAC Coupling capacitors - The AC coupling capacitors for the TX and RX lines are incorporated on the COM Express Module.

SATA0_TX-

SATA0_RX+ I SATA


Serial ATA or SAS Channel 0 receive differential pair.

SATA0_RX-

SATA1_TX+ O SATA



SATA1_TX-

SATA1_RX+ I SATA



SATA1_RX-

SATA2_TX+ O SATA



SATA2_TX-

SATA2_RX+ I SATA



A26

B22

B23

B25

B26

A28

I SATA




Spacing -RX and TX pairs (inter-pair) - Min. 20milsfrom high-speed periodic signals - Min. 50milsfrom low-speed non periodic signals - Min. 20milsfrom edge of plane - Min. 40milsLength - Max. 3 inchesLength matching - differential pairs (intra-pair) - Max. 5milsRX and TX pairs (inter-pair) - No strict electrical requirements. Keep difference within a 3.0 inch delta to minimize latency. Do not serpentine to meet trace length guidelines for the RX and TX path.Via Usage - Try to minimize number of viasAC Coupling capacitors - The AC coupling capacitors for the TX and RX lines are incorporated on the COM Express Module.

SATA2_RX-

SATA3_TX+ O SATA



SATA3_TX-

SATA3_RX+ I SATA



SATA3_RX-

(S)ATA_ACT# O CMOS 3.3V / 3.3V ATA (parallel and serial) or SAS activity indicator,

active low.

SATA Insertion Loss Budget

SATA Gen 1 Insertion Loss Budget, 1.5 GHz Segment Loss (dB) Notes

1.26 Up to 3.0 inches of module trace @ 0.28 dB / GHz / inch Coupling Caps 0.40

0.25 3.07 Up to 7.2 inches of Carrier Board trace @ 0.28 dB / GHz / inch6.00 Source specification cable and cable connector allowance

Total 10.98 SATA Gen 2 Insertion Loss Budget, 3.0 GHz

Segment Loss (dB) Notes1.68 Up to 2.0 inches of module trace @ 0.28 dB / GHz / inch

Coupling Caps 0.40 0.38 2.52 Up to 3.0 inches of Carrier Board trace @ 0.28 dB / GHz / inch

The Serial ATA source specification provides insertion loss figures only for the SATA cable. There are several cable types defined with insertion losses ranging from 6 dB up to 16 dB. Cross talk losses are separate from material losses in the SATA specification.The COM ExpressTM SATA Insertion loss budgets presented below represent the material losses and do not include cross talk losses. The COM ExpressTM SATA Insertion loss budgets are a guideline: module and Carrier Board vendors should not exceed the values shown in the tables below.

LA

LB COM ExpressTM connector at 1.5 GHz measured value LC

LD

LA

LB COM ExpressTM connector at 3.0 GHz measured value LC

6.00 Source specification cable and cable connector allowance Total 10.98


LD

1000<L<4000

6.5/10/20 6/6.5/20 2000 < L < 12000 1712.16

6.5/10/20 6/6.5/20 2000 < L < 12000 1711.33

6.5/10/20 6/6.5/20 2000 < L < 12000 1757.47

6.5/10/20 6/6.5/20 2000 < L < 12000 1756.93

6.5/10/20 6/6.5/20 2000 < L < 12000 1467.53

6.5/10/20 6/6.5/20 2000 < L < 12000 1467.16

6.5/10/20 6/6.5/20 2000 < L < 12000 1262.31

6.5/10/20 6/6.5/20 2000 < L < 12000 1263.73

6.5/10/20 6/6.5/20 2000 < L < 12000 1786.82

6.5/10/20 6/6.5/20 2000 < L < 12000 1787.65

6.5/10/20 6/6.5/20 2000 < L < 12000 1897.67


LynxPoint-MChecklist Length[mils]


Length[mils]COME to SATA

Conn.

Inner LayerDP - 85 Ω ± 10%SE - 48 Ω ± 10%

Outer LayerDP - 85 Ω ± 15%SE - 50 Ω ± 15%

1. SATA Gen 1 - 2000 < L < 12000 COME to SATA Conn. - 1000 < L < 4000

6.5/10/20 6/6.5/20 2000 < L < 12000 1898.03

6.5/10/20 6/6.5/20 2000 < L < 12000 1479.96

6.5/10/20 6/6.5/20 2000 < L < 12000 1480.1

6.5/10/20 6/6.5/20 2000 < L < 12000 1375.74

6.5/10/20 6/6.5/20 2000 < L < 12000 1375.26

6/12/12 6/12/12 ASAP

1

1. SATA Gen 1 - 2000 < L < 12000 COME to SATA Conn. - 1000 < L < 40002. SATA Gen 2/3 w/Repaeter - L < 14500 COME to Repeater - L < 2500 Repeater to SATA Conn. - L < 4000

3. eSATA Gen 1/2 w/Repeater - L < 15000 COME to Repeater - L < 3000 Repeater to eSATA Conn. - L < 3000

2000<L<12000 L < 10

1712.160.830000000000155

1711.33

1757.470.539999999999964

1756.93

1467.530.369999999999891

1467.16

1262.311.42000000000007

1263.73

1786.820.830000000000155

1787.65

1897.670.3599999999999

SOM-5894 A101-4Total Length[mils]


1898.03

0.3599999999999

1479.960.139999999999873

1480.1

1375.740.480000000000018

1375.26

Pin No. IDE Pin Type Description

C14

C13

D7

C10

C8

C4

D6

D2

C3

C2

C6

C7

D3

D4

D5


PICMG DG 1.0Module

Length[mils]


Length[mils]Maximum Transfer Rate @ ATA100 - 100 MB/secSE - 55 Ω +/-15%

IDE_IOR# I CMOS

3.3V / 3.3V I/O read line from IDE device.

Spacing - from edge of plane - Min. 40milsLength - Max. 7.0 inchesLength matching - strobe and data signals - Max. 450milsdata signals - Max. 200milsstrobe signals 'IDE_IOR' and 'IDE_IOW' - Max. 100milsReference plane - GND referenced preferredVia Usage - Try to minimize number of vias

IDE_IORDY I CMOS

3.3V / 5V

IDE device I/O ready input. Pulled low by the IDE device to extend the cycle.

IDE_D0 I/O CMOS

3.3V / 5V Bidirectional data to / from IDE device.

IDE_D1 I/O CMOS


IDE_D2 I/O CMOS


IDE_D3 I/O CMOS


IDE_D4 I/O CMOS


IDE_D5 I/O CMOS


IDE_D6 I/O CMOS


IDE_D7 I/O CMOS


IDE_D8 I/O CMOS


IDE_D9 I/O CMOS


IDE_D10 I/O CMOS


IDE_D11 I/O CMOS


IDE_D12 I/O CMOS


C9

C12

C5

D13

D14

D15

D9

D8

D10

D16

D17

D18

D12

D77

ASAP - As short as possibleDP - Differential Pair

Spacing - from edge of plane - Min. 40milsLength - Max. 7.0 inchesLength matching - strobe and data signals - Max. 450milsdata signals - Max. 200milsstrobe signals 'IDE_IOR' and 'IDE_IOW' - Max. 100milsReference plane - GND referenced preferredVia Usage - Try to minimize number of vias

IDE_D13 I/O CMOS


IDE_D14 I/O CMOS


IDE_D15 I/O CMOS


IDE_A0 O CMOS

3.3V / 3.3V Address lines to IDE device.

IDE_A1 O CMOS


IDE_A2 O CMOS


IDE_IOW# O CMOS

3.3V / 3.3V

I/O write line to IDE device. Data latched on trailing (rising) edge.

IDE_REQ I CMOS

3.3V / 5V

IDE Device DMA Request. It is asserted by the IDE device to request a data transfer.

IDE_ACK# O CMOS

3.3V / 3.3V IDE Device DMA Acknowledge.

IDE_CS1# O CMOS

3.3V / 3.3V IDE Device Chip Select for 1F0h to 1FFh range.

IDE_CS3# O CMOS

3.3V / 3.3V IDE Device Chip Select for 3F0h to 3FFh range.

IDE_RESET# O CMOS

3.3V / 3.3V Reset output to IDE device, active low.

IDE_IRQ I CMOS

3.3V / 5V Interrupt request from IDE device.

IDE_CBLID# I CMOS

3.3V / 5V

Input from off-module hardware indicating the type of IDE cable being used. High indicates a 40-pin cable used for legacy IDE modes. Low indicates that an 80-pin cable with interleaved grounds is used. Such a cable is required for Ultra-DMA 66, 100 and 133 modes.

SE - Single End

Pin No. Pin Type Description

General Purpose

A68

A69

A64

A65

A61

A62

A58

A59

A55

A56

PCI Express Lanes


PICMG DG 1.0Module

Length[mils]


Length[mils]

Transfer Rate / PCIe Lane - 2.5 GBit/sDP - 92 Ω +/-10% (covers Gen1 100 Ω +/-20% and Gen2 85 Ω +/-20% requirements)SE - 55 Ω +/-15%Total length - Max. 21.0 inches.

PCIE_TX0+

O PCIE


PCI Express Differential Transmit Pairs 0 through 5 Spacing -

RX and TX pairs (inter-pair) - Min. 20milsfrom high-speed periodic signals - Min. 50milsfrom low-speed non periodic signals - Min. 20milsfrom edge of plane - Min. 40milsLength -PCIe device - Max.15.85 inches @ 0.28dB/GHz/inchPCIe slot - Max. 9.00 inches @ 0.28dB/GHz/inchLength matching -differential pairs (intra-pair) - Max. 5milsRX and TX pairs (inter-pair) - No strict electrical requirements. Keep difference within a 3.0 inch delta to minimize latency.REFCLK+ and REFCLK- (intra-pair) - Max. 5milsreference clock pairs (inter-pair) - No electrical requirements.Reference plane - GND referenced preferredVia Usage - Max. 2 vias per TX trace, Max. 4 vias per RX traceAC coupling capacitors - The AC coupling capacitors for the TX lines are incorporated on the COM Express Module. The AC coupling capacitors for RX signal lines have to be implementedon the customer COM Express Carrier Board. Capacitor type: X7R, 100nF +/-10%, 16V, shape 0402.

PCIE_TX0-

PCIE_TX1+

PCIE_TX1-

PCIE_TX2+

PCIE_TX2-

PCIE_TX3+

PCIE_TX3-

PCIE_TX4+

PCIE_TX4-

A52

A53

D19

D20

D22

D23

B68

B69

B64

B65

B61

O PCIE


PCI Express Differential Transmit Pairs 0 through 5 Spacing -

RX and TX pairs (inter-pair) - Min. 20milsfrom high-speed periodic signals - Min. 50milsfrom low-speed non periodic signals - Min. 20milsfrom edge of plane - Min. 40milsLength -PCIe device - Max.15.85 inches @ 0.28dB/GHz/inchPCIe slot - Max. 9.00 inches @ 0.28dB/GHz/inchLength matching -differential pairs (intra-pair) - Max. 5milsRX and TX pairs (inter-pair) - No strict electrical requirements. Keep difference within a 3.0 inch delta to minimize latency.REFCLK+ and REFCLK- (intra-pair) - Max. 5milsreference clock pairs (inter-pair) - No electrical requirements.Reference plane - GND referenced preferredVia Usage - Max. 2 vias per TX trace, Max. 4 vias per RX traceAC coupling capacitors - The AC coupling capacitors for the TX lines are incorporated on the COM Express Module. The AC coupling capacitors for RX signal lines have to be implementedon the customer COM Express Carrier Board. Capacitor type: X7R, 100nF +/-10%, 16V, shape 0402.

PCIE_TX5+

PCIE_TX5-

PCIE_TX6+

PCIE_TX6-

PCIE_TX7+

PCIE_TX7-

PCIE_RX0+

I PCIE

AC coupled off module

PCI Express Differential Receive Pairs 0 through 5

PCIE_RX0-

PCIE_RX1+

PCIE_RX1-

PCIE_RX2+

B62

B58

B59

B55

B56

B52

B53

C19

C20

C22

C23


x16 Graphics

I PCIE


PCI Express Differential Receive Pairs 0 through 5

Spacing - RX and TX pairs (inter-pair) - Min. 20milsfrom high-speed periodic signals - Min. 50milsfrom low-speed non periodic signals - Min. 20milsfrom edge of plane - Min. 40milsLength -PCIe device - Max.15.85 inches @ 0.28dB/GHz/inchPCIe slot - Max. 9.00 inches @ 0.28dB/GHz/inchLength matching -differential pairs (intra-pair) - Max. 5milsRX and TX pairs (inter-pair) - No strict electrical requirements. Keep difference within a 3.0 inch delta to minimize latency.REFCLK+ and REFCLK- (intra-pair) - Max. 5milsreference clock pairs (inter-pair) - No electrical requirements.Reference plane - GND referenced preferredVia Usage - Max. 2 vias per TX trace, Max. 4 vias per RX traceAC coupling capacitors - The AC coupling capacitors for the TX lines are incorporated on the COM Express Module. The AC coupling capacitors for RX signal lines have to be implementedon the customer COM Express Carrier Board. Capacitor type: X7R, 100nF +/-10%, 16V, shape 0402.

PCIE_RX2-

PCIE_RX3+

PCIE_RX3-

PCIE_RX4+

PCIE_RX4-

PCIE_RX5+

PCIE_RX5-

PCIE_RX6+

PCIE_RX6-

PCIE_RX7+

PCIE_RX7-

PCI Express Lanes


PICMG DG 1.0Module

Length[mils]


Length[mils]

D52

D53

D55

D56

D58

D59

D61

D62

D65

D66

D68

D69

D71

D72

D74

D75

D78

D79

D81

D82

D85

D86

D88

D89

D91

PEG_TX0+

O PCIE


PCI Express Graphics transmit differential pairs. Some of these are multiplexed with SDVO lines (see SDVO section). These are the same lines as PCIE_TX[16:31] + and - in module pin-out types 4 and 5.


PEG_TX0-

PEG_TX1+

PEG_TX1-

PEG_TX2+

PEG_TX2-

PEG_TX3+

PEG_TX3-

PEG_TX4+

PEG_TX4-

PEG_TX5+

PEG_TX5-

PEG_TX6+

PEG_TX6-

PEG_TX7+

PEG_TX7-

PEG_TX8+

PEG_TX8-

PEG_TX9+

PEG_TX9-

PEG_TX10+

PEG_TX10-

PEG_TX11+

PEG_TX11-

PEG_TX12+

D92

D94

D95

D98

D99

D101

D102

C52

C53

C55

C56

C58

C59

C61

C62

C65

C66

C68

C69

C71

C72

C74

O PCIE


PCI Express Graphics transmit differential pairs. Some of these are multiplexed with SDVO lines (see SDVO section). These are the same lines as PCIE_TX[16:31] + and - in module pin-out types 4 and 5.


PEG_TX12-

PEG_TX13+

PEG_TX13-

PEG_TX14+

PEG_TX14-

PEG_TX15+

PEG_TX15-

PEG_RX0+

I PCIE


PCI Express Graphics receive differential pairs. Some of these are multiplexed with SDVO lines (see SDVO section). These are the same lines as PCIE_RX[16:31] + and - in module pin-out types 4 and 5.

PEG_RX0-

PEG_RX1+

PEG_RX1-

PEG_RX2+

PEG_RX2-

PEG_RX3+

PEG_RX3-

PEG_RX4+

PEG_RX4-

PEG_RX5+

PEG_RX5-

PEG_RX6+

PEG_RX6-

PEG_RX7+

C75

C78

C79

C81

C82

C85

C86

C88

C89

C91

C92

C94

C95

C98

C99

C101

C102

PCI Express Clock

A88

A89

D54

I PCIE


PCI Express Graphics receive differential pairs. Some of these are multiplexed with SDVO lines (see SDVO section). These are the same lines as PCIE_RX[16:31] + and - in module pin-out types 4 and 5.

Spacing - RX and TX pairs (inter-pair) - Min. 20milsfrom high-speed periodic signals - Min. 50milsfrom low-speed non periodic signals - Min. 20milsfrom edge of plane - Min. 40milsLength -PCIe device - Max.15.85 inches @ 0.28dB/GHz/inchPCIe slot - Max. 9.00 inches @ 0.28dB/GHz/inchLength matching -differential pairs (intra-pair) - Max. 5milsRX and TX pairs (inter-pair) - No strict electrical requirements. Keep difference within a 3.0 inch delta to minimize latency.REFCLK+ and REFCLK- (intra-pair) - Max. 5milsreference clock pairs (inter-pair) - No electrical requirements.Reference plane - GND referenced preferredVia Usage - Max. 2 vias per TX trace, Max. 4 vias per RX traceAC coupling capacitors - The AC coupling capacitors for the TX lines are incorporated on the COM Express Module. The AC coupling capacitors for RX signal lines have to be implementedon the customer COM Express Carrier Board. Capacitor type: X7R, 100nF +/-10%, 16V, shape 0402. PEG_RX7-

PEG_RX8+

PEG_RX8-

PEG_RX9+

PEG_RX9-

PEG_RX10+

PEG_RX10-

PEG_RX11+

PEG_RX11-

PEG_RX12+

PEG_RX12-

PEG_RX13+

PEG_RX13-

PEG_RX14+

PEG_RX14-

PEG_RX15+

PEG_RX15-

PCIE0_CLK_REF+ O CMOS

3.3V / 3.3V

Reference clock output for all PCI Express and PCI Express Graphics lanes.

Length matching -REFCLK+ and REFCLK- (intra-pair) - Max. 5mils PCIE0_CLK_REF-

PEG_LANE_RV# I CMOS

3.3V / 3.3V

PCI Express Graphics lane reversal input strap. Pull low on the carrier board to reverse lane order. Be aware that the SDVO lines that share this interface do not necessarily reverse order if this strap is low.

D97 PEG_ENABLE# I CMOS

3.3V / 3.3V

Strap to enable PCI Express x16 external graphics interface. Pull low to disable internal graphics and enable the x16 interface.

PCI Express Insertion Loss Budget with Slot Card

PCI Express Insertion Loss Budget, 1.25 GHz with Carrier Board Slot Card

Notes

1.19

0.25

1.25

2.65

Total 13.20 13.20 dB loss.

Segment

Loss (dB)max. Length[mm/inches]

LA3.46

130/5.15Allowance for 5.15 inches of module trace 3.45 dB loss @ 0.28 dB / GHz / inch and 1.66 dB crosstalk allowance. Coupling caps not included.

Coupling Caps

1.19 dB loss. From PCI Express Card Electromechanical Spec., Rev. 1.1, parameters (LST – LSR). Includes crosstalk allowance of 0.79 dB.

LB COM ExpressTM connector at 1.25 GHz measured value: 0.25 dB loss.

LC4.4

228/9.0Allowance for 9 inches of Carrier Board trace 4.40 db loss @ 0.28 dB / GHz / inch and a 1.25 dB crosstalk allowance.

LD1.25 dB loss. PCI Express Card Electromechanical Spec Rev 1.1 “guard band” allowance for slot connector – includes 1.0 dB connector loss.

LE2.65 dB loss. From PCI Express Card Electromechanical Spec., Rev. 1.1(without coupling caps; LAR). Implied crosstalk allowance is 1.25 dB.

The module transmit and receive insertion loss budgets are different due to the presence of the coupling caps in the module transmit path. The module transmit path insertion loss budget shall be 4.65 dB (3.46 dB + 1.19 dB). The module receive path insertion loss budget shall be 3.46 dB. COM ExpressTM connector loss is accounted for separately.The Carrier Board transmit and receive insertion loss budgets are the same in this case. The Carrier Board insertion loss budget shall be 4.40 dB. COM ExpressTM connector and slot card connector losses are accounted for separately.

The slot card transmit and receive insertion loss budgets are different due to the presence of the coupling caps in the slot card’s transmit path. The slot card’s transmit path insertion loss budget is 3.84 dB (2.65 dB + 1.19 dB) per the PCI Express Card Electromechanical Specification Revision 1.1. The slot card’s receive path insertion loss budget is 2.65 dB per the same specification. Slot card connector loss is accounted for separately.

PCI Express Insertion Loss Budget, 2.5 GHz with Carrier Board Slot Card

Notes

127/5.0 Allowance for module trace. Coupling cap effects included within simulation.

COM Express™ connector simulated at 2.5 GHz. 113/4.45 Allowance for Carrier Board.

PCI Express Card slot connector simulated at 2.5 GHz.

80/3.15

Total 320/12.6 PCIe GEN2 Data clocked architecture

PCI Express Insertion Loss Budget with Carrier Board PCIE Device

Segment

max. Length [mm/inches]

LA

LB LC

LD

LE Slot Card trace length from PCI Express Card Electromagnetical Spec., Rev. 1.1

For “device up” PCIe Gen 2 operation, the Module PCIe maximum trace length is restricted to 5.0 inches and the Carrier Board maximum trace to 4.45 inches. Shorter lengths will yield additional margin and are encouraged where possible. Results assumed FR4 dielectrics.Other dielectrics with lower losses could be considered, but were not simulated.

It should be noted that a use case exists that might result in reduced PCI Express bandwidth. This use case is tied to Carrier boards with a PCI Express slot (device up). PCI Express Gen 1 and Gen 2 signaling rates use the same PCI Express connector – there is no mechanical keying mechanism to identify the capabilities of the PCI Express slot or the PCI Express board plugged into the slot. This can lead to the situation where the Module and PCI Express board attempt a PCI Express Gen2 signaling rate connection over a Carrier that does not meet the routing guidelines for Gen 2 signaling rates. In a worst case scenario the devices might connect at Gen2 signaling rate with a high number of errors impacting the actual data throughput. It should be noted that there is a Carrier EEPROM on the Carrier which would allow the Module to determine the Carrier board capabilities but this is not a requirement in COM.0.

The insertion losses previously allowed for the slot card and slot card connector are re-allocated for use on the Carrier Board, allowing longer Carrier Board trace lengths and more Carrier Board design flexibility. The module and COM ExpressTM connector loss budgets remain the same.

PCI Express Insertion Loss Budget, 1.25 GHz with Carrier Board PCIE Device

1.19

0.25

13.20 13.20 dB loss

PCI Express Insertion Loss Budget, 2.5 GHz with Carrier Board PCIE Device

Notes

Segment

Loss (dB)max. Length[mm/inches]

Notes

LA3.46

131/5.15 Allowance for 5.15 inches of module trace 3.46 dB loss @ 0.28 dB / GHz / inch and 1.66 dB crosstalk allowance. Coupling caps not included.

Coupling Caps

1.19 dB loss. From PCI Express Card Electromechanical Spec., Rev. 1.1, parameters (LST– LSR). Includes crosstalk allowance of 0.79 dB.

LB COM ExpressTMconnector at 1.25 GHz measured value: 0.25 dB loss

LC8.3

402/15.85 Allowance for 15.85 inches of Carrier Board trace 8.30 dB loss @ 0.28 dB / GHz / inch and a 2.75 dB crosstalk allowance.

Total

The module transmit and receive insertion loss budgets are different due to the presence of the coupling caps in the module transmit path. The module transmit path insertion loss budget shall be 4.65 dB (3.46 dB + 1.19 dB). The module receive path insertion loss budget shall be 3.46 dB. COM ExpressTM connector loss is accounted for separately.

The Carrier Board transmit and receive insertion loss budgets are different due to the presence of the coupling caps in the Carrier Board transmit path. The Carrier Board transmit path insertion loss budget shall be 9.49 dB (8.30 dB + 1.19 dB). The Carrier Board receive path insertion loss shall be 8.30 dB. COM ExpressTM connector loss is accounted for separately.

Segment

max. Length [mm/inches]

LA 127/5.0 Allowance for module trace. Coupling cap effects included within simulation.

LB COM Express™ connector simulated at 2.5 GHz. LC 203/8.0 Allowance for Carrier Board trace.

Total 330/13.0 PCIe GEN2 Data clocked architecture For “device down” PCIe Gen 2 operation, the Module PCIe maximum trace length is restricted to 5.0 inches and the Carrier Board maximum trace to 8.0 inches. Shorter lengths will yield additional margin and are encouraged where possible. Results assumed FR4 dielectrics. Other dielectrics with lower losses could be considered, but were not simulated.

6.5/10/15 6/6.5/15 L<10500

N/A

2447.45

6.5/10/15 6/6.5/15 L<10500 2447.05

6.5/10/15 6/6.5/15 L<10500

N/A

2148.02

6.5/10/15 6/6.5/15 L<10500 2148.1

6.5/10/15 6/6.5/15 L<10500

N/A

2073.81

6.5/10/15 6/6.5/15 L<10500 2074.43

6.5/10/15 6/6.5/15 L<10500

N/A

2011.39

6.5/10/15 6/6.5/15 L<10500 2010.95

6.5/10/15 6/6.5/15 L<10500

N/A

2067.19

6.5/10/15 6/6.5/15 L<10500 2066.46



Haswell-MblChecklist Length[mils]

SOM-5894 A1014Module

Length[mils]RX - COME to Caps

Length[mils]



2. LynxPoint-M to Device Down - Gen2 - L < 10500 TX - COME to Device - L < 4100 RX - COME to Caps - L < 1800, Caps to Device - L < 2300

6.5/10/15 6/6.5/15 L<10500

N/A

2299.15

6.5/10/15 6/6.5/15 L<10500 2298.41

6.5/10/15 6/6.5/15 L<10500

N/A

1257.87

6.5/10/15 6/6.5/15 L<10500 1257.23

N/A N/A N/A N/A N/A N/A

L<1800

6.5/10/15 6/6.5/15 L<10500

N/A

2130.59

6.5/10/15 6/6.5/15 L<10500 2130.81

6.5/10/15 6/6.5/15 L<10500

N/A

2290.01

6.5/10/15 6/6.5/15 L<10500 2290.52

6.5/10/15 6/6.5/15 L<10500

N/A

2151.21




6.5/10/15 6/6.5/15 L<10500

N/A

2151.8

6.5/10/15 6/6.5/15 L<10500

N/A

1834.93

6.5/10/15 6/6.5/15 L<10500 1834.46

6.5/10/15 6/6.5/15 L<10500

N/A

1600.63

6.5/10/15 6/6.5/15 L<10500 1600.69

6.5/10/15 6/6.5/15 L<10500

N/A

1457.38

6.5/10/15 6/6.5/15 L<10500 1457.71

6.5/10/15 6/6.5/15 L<10500

N/A

1440.65

6.5/10/15 6/6.5/15 L<10500 1440.5

N/A N/A N/A N/A N/A



Haswell-MblChecklist Length[mils]

RX - COME to CapsLength[mils]



1. Haswell-Mbl to GFX Device - Reduced Swing - 2000 < L < 10000 RX - COME to Caps < 500

7/8/20 6.5/6.5/20N/A 2000<L<10000

1681.6

7/8/20 6.5/6.5/20 1681.09

7/8/20 6.5/6.5/20N/A 2000<L<10000

1678.79

7/8/20 6.5/6.5/20 1678.75

7/8/20 6.5/6.5/20N/A 2000<L<10000

1507.46

7/8/20 6.5/6.5/20 1506.75

7/8/20 6.5/6.5/20N/A 2000<L<10000

1511.34

7/8/20 6.5/6.5/20 1510.76

7/8/20 6.5/6.5/20N/A 2000<L<10000

1477.55

7/8/20 6.5/6.5/20 1476.62

7/8/20 6.5/6.5/20N/A 2000<L<10000

1474.33

7/8/20 6.5/6.5/20 1474.04

7/8/20 6.5/6.5/20N/A 2000<L<10000

1455.77

7/8/20 6.5/6.5/20 1456.75

7/8/20 6.5/6.5/20N/A 2000<L<10000

1453.4

7/8/20 6.5/6.5/20 1453.71

7/8/20 6.5/6.5/20N/A 2000<L<10000

1339.53

7/8/20 6.5/6.5/20 1339.73

7/8/20 6.5/6.5/20N/A 2000<L<10000

1341.43

7/8/20 6.5/6.5/20 1340.91

7/8/20 6.5/6.5/20N/A 2000<L<10000

1603.55

7/8/20 6.5/6.5/20 1604.5

7/8/20 6.5/6.5/20N/A 2000<L<10000

1605.42

7/8/20 6.5/6.5/20 1605.77

7/8/20 6.5/6.5/20N/A 2000<L<10000

1462.82

7/8/20 6.5/6.5/20N/A 2000<L<10000

1463.27

7/8/20 6.5/6.5/20N/A 2000<L<10000

1462.51

7/8/20 6.5/6.5/20 1462.96

7/8/20 6.5/6.5/20N/A 2000<L<10000

1513.92

7/8/20 6.5/6.5/20 1514.37

7/8/20 6.5/6.5/20N/A 2000<L<10000

1513.3

7/8/20 6.5/6.5/20 1511.45

L<500

7/8/20 6.5/6.5/20N/A 2000<L<10000

2125.08

7/8/20 6.5/6.5/20 2125.88

7/8/20 6.5/6.5/20N/A 2000<L<10000

2112.2

7/8/20 6.5/6.5/20 2112.66

7/8/20 6.5/6.5/20N/A 2000<L<10000

1853.53

7/8/20 6.5/6.5/20 1853.33

7/8/20 6.5/6.5/20N/A 2000<L<10000

1953.88

7/8/20 6.5/6.5/20 1954.09

7/8/20 6.5/6.5/20N/A 2000<L<10000

2218.61

7/8/20 6.5/6.5/20 2218.56

7/8/20 6.5/6.5/20N/A 2000<L<10000

2021.56

7/8/20 6.5/6.5/20 2022.51

7/8/20 6.5/6.5/20N/A 2000<L<10000

1643.6

7/8/20 6.5/6.5/20 1643.64

7/8/20 6.5/6.5/20N/A 2000<L<10000

1638.63




7/8/20 6.5/6.5/20N/A 2000<L<10000

1638.26

7/8/20 6.5/6.5/20N/A 2000<L<10000

1639.09

7/8/20 6.5/6.5/20 1639.86

7/8/20 6.5/6.5/20N/A 2000<L<10000

1803.56

7/8/20 6.5/6.5/20 1804.46

7/8/20 6.5/6.5/20N/A 2000<L<10000

1612.03

7/8/20 6.5/6.5/20 1611.37

7/8/20 6.5/6.5/20N/A 2000<L<10000

1609.41

7/8/20 6.5/6.5/20 1609.54

7/8/20 6.5/6.5/20N/A 2000<L<10000

1902.04

7/8/20 6.5/6.5/20 1903.02

7/8/20 6.5/6.5/20N/A 2000<L<10000

1921.28

7/8/20 6.5/6.5/20 1920.54

7/8/20 6.5/6.5/20N/A 2000<L<10000

2268.95

7/8/20 6.5/6.5/20 2269.57

7/8/20 6.5/6.5/20N/A 2000<L<10000

1937.26

7/8/20 6.5/6.5/20 1937.73

6.5/17/15 6/9/152000<L<14000 N/A

3034.07

6.5/17/15 6/9/15 3033.27

6/8/8 6/8/8 N/A ASAP



1. LynxPoint-M to Device Down - 2000 < L < 14000

6/8/8 6/8/8 ASAP N/A



1

2

1


2. Haswell-Mbl to GFX Connector - Full Swing - 1500 < L < 7000

3. LynxPoint-M to Device Down - Gen2 w/Repeater - TX - L < 11450 + Repeater spec, RX - L < 15150 + Repeater spec, TX - COME to Repeater - L < 1800, Repeater to Caps - L < 500 RX - COME to Caps - L < 4000, Caps to Repeater - L < 500

3. Haswell-Mbl to GFX Connector - Reduced Swing - 1000 < L < 4500

4. LynxPoint-M to ExpressCard or Mini Card Connector - Gen1 - L < 13000 COME to Conn. - L < 4500

5. LynxPoint-M to ExpressCard or Mini Card Connector - Gen2 - L < 8500 COME to Conn. - L < 2300

6. LynxPoint-M to ExpressCard or Mini Card Connector - Gen2 w/Repeater - TX - L < 11450 + Repeater spec, RX - L < 15150 + Repeater spec, TX - COME to Repeater - L < 1800, Repeater to Caps - L < 500 RX - COME to Caps - L < 4000, Caps to Repeater - L < 5001. LynxPoint-M to Device Down - 2000 < L < 140002. LynxPoint-M to ExpressCard or Mini Card Connector - 2000 < L < 12500

Repeater Drive spe

L<4100 L<10500 L < 5

2447.45

0.399999999999636

2447.05

2148.02

0.079999999999927

2148.1

2073.81

0.619999999999891

2074.43

2011.39

0.440000000000055

2010.95

2067.19

0.730000000000018

2066.46

RX - Caps to Device

Length[mils]

TX - COME to Device



O2

Please input Repeater Drive spec. first if used !

2299.15

0.740000000000237

2298.41

1257.87

0.639999999999873

1257.23

N/A N/A N/A N/A N/A

L<2300

Repeater Drive spe

L<10500 L < 5

2130.59

0.2199999999998

2130.81

2290.01

0.509999999999764

2290.52

2151.21

0.590000000000146

2151.8

0.590000000000146

1834.93

0.470000000000027

1834.46

1600.63

0.059999999999945

1600.69

1457.38

0.329999999999927

1457.71

1440.65

0.150000000000091

1440.5

N/A N/A N/A

2000<L<10000 L < 5

RX - Caps to Device

Length[mils]

TX - COME to Device



1681.60.509999999999991

1681.091678.79

0.0399999999999641678.751507.46

0.7100000000000361506.751511.34

0.5799999999999271510.761477.55

0.9300000000000641476.621474.33

0.2899999999999641474.041455.77

0.9800000000000181456.75

1453.40.309999999999945

1453.711339.53

0.2000000000000451339.731341.43

0.5199999999999821340.911603.55

0.9500000000000461604.5

1605.420.349999999999909

1605.771462.82

0.450000000000046

1463.270.450000000000046

1462.510.450000000000046

1462.961513.92

0.4499999999998181514.37

1513.31.84999999999991

1511.45

2000<L<10000 L < 5

2125.080.800000000000182

2125.88

2112.20.460000000000036

2112.66

1853.530.200000000000045

1853.331953.88

0.2099999999998091954.09

2218.610.050000000000182

2218.56

2021.560.950000000000046

2022.51

1643.60.040000000000191

1643.641638.63

0.370000000000118

1638.260.370000000000118

1639.090.769999999999982

1639.861803.56

0.9000000000000911804.461612.03

0.6600000000000821611.371609.41

0.1299999999998821609.541902.04

0.9800000000000181903.021921.28

0.7400000000000091920.54

2268.950.620000000000346

2269.57

1937.260.470000000000027

1937.73

2000<L<14000 L < 25

3034.070.800000000000182

3033.27

Pin No. Pin Type

A49

B48

A48


ExpressCard Support Pwr Rail / Tolerance

EXCD0_CPPE# I CMOS 3.3V /

3.3V EXCD1_CPPE#

EXCD0_PERST# O CMOS 3.3V /

3.3V B47 EXCD1_PERST#

Description


PICMG DG 1.0Module

Length[mils]


Length[mils]

PCI ExpressCard: PCI Express capable card request, active low, one per card

PCI ExpressCard: reset, active low, one per card

6/8/8 6/8/8 ASAP

6/8/8 6/8/8 ASAP

6/8/8 6/8/8 ASAP

6/8/8 6/8/8 ASAP


IT8518EChecklist

Length[mils]


Length[mils]

Inner LayerSE - 50Ω ± 10%

Outer LayerSE - 50Ω ± 15%

IT8518E to ExpressCard Socket

Pin No. DDI

D34

C34

C38

B95


DDI1_DDC_AUX_SEL I CMOS

3.3V / 3.3V


3.3V / 3.3V


3.3V / 3.3V


3.3V / 3.3V

Description Pin Availability Module

T6

T6

T6

T10

Selects the function of DDI[1:3]_CTRLCLK_AUX+ and DDI[1:3]_CTRLDATA_AUX-. This pin shall have a 1M pull-down to logic ground on the Module. If this input is floating the AUX pair is used for the DP AUX+/- signals. If pulled-high the AUX pair contains the CRTLCLK and CTRLDATA signals.

Selects the function of DDI[0]_CTRLCLK_AUX+ and DDI[0]_CTRLDATA_AUX-. This pin shall have a 1M pull-down to logic ground on the Module. If this input is floating the AUX pair is used for the DP AUX+/- signals. If pulled-high the AUX pair contains the CRTLCLK and CTRLDATA signals.

Baseboard

6/8/8 6/8/8 ASAP

6/8/8 6/8/8 ASAP

6/8/8 6/8/8 ASAP

N/A N/A N/A


DDC/DP_AUX Selection circuit

Checklist Length[mils]



N/A N/A N/A


Length[mils]



Pin No. DDI-SDVO

B71 B72 B73 B74 B75 B76 B81 B82 B77 B78 B91 B92 B93 B94 D26 D27 D29 D30 D32 D33 D36 D37 C25 C26 C29 C30 C15 C16

B98

B99

D15

D16

SDVO Loss Budget


SDVO0_RED+ O PCIE

AC coupled off Module SDVO0_RED-

SDVO0_GRN+ O PCIE

AC coupled off Module SDVO0_GRN-

SDVO0_BLU+ O PCIE

AC coupled off Module SDVO_BLU-

SDVO0_CK+ O PCIE

AC coupled off Module SDVO0_CK-

SDVO0_INT+ I PCIE

AC coupled off Module SDVO0_INT-

SDVO0_TVCLKIN+ I PCIE

AC coupled off Module SDVO0_TVCLKIN-

SDVO0_FLDSTALL+ I PCIE

AC coupled off Module SDVO0_FLDSTALL-

SDVO1_RED+ O PCIE

AC coupled off Module SDVO1_RED-

SDVO1_GRN+ O PCIE

AC coupled off Module SDVO1_GRN-

SDVO1_BLU+ O PCIE

AC coupled off Module SDVO1_BLU-

SDVO1_CK+ O PCIE

AC coupled off Module SDVO1_CK-

SDVO1_INT+ I PCIE

AC coupled off Module SDVO1_INT-

SDVO1_TVCLKIN+ I PCIE

AC coupled off Module SDVO1_TVCLKIN-

SDVO1_FLDSTALL+ I PCIE

AC coupled off Module SDVO1_FLDSTALL-

SDVO0_CTRLCLK I/O OD CMOS

3.3V / 3.3V

SDVO0_CTRLDATA I/O OD CMOS

3.3V / 3.3V

SDVO1_CTRLCLK I/O OD CMOS

3.3V / 3.3V

SDVO1_CTRLDATA I/O OD CMOS

3.3V / 3.3V

Carriers that support SDVO: • DDI[n]_DDC_AUX_SEL shall be pulled to 3.3V on the Carrier with a 100K Ohm resistor to configure the DDI[n]_AUX pair as the DDC channel. • DC blocking capacitors shall be placed on the Carrier for the SDVO RED, GRN, BLU, CK, INT, TVCLKIN, and FLDSTALL signals.The DDI signals can be used to support a variety of video interfaces. The circuits required to realize the different video interfaces will be determined by a future PICMG Carrier Design Guide subcommittee. At this time, thew only requirement placed on Modules for the DDI signals is the maximum trace length specified below.

SDVO Insertion Loss Budget

127/5.0 Allowance for module trace. Coupling cap effects included within simulation. COM Express™ connector simulated at 2.5 GHz.

TBD Allowance for Carrier Board trace. Total TBD

The TBD values will be determined by a future PICMG Carrier Design Guide.

PU - Pull UpPD - Pull DownJS - Jumper SelectionNL - No Loaded

Segment max. Length [mm/inches] Notes

LA LB LC

x.xV - Power active in S0x.xVSB - Power active in S0~S5x.xVDUAL - Power active from x.xV in S0,S1 and from x.xVSB in S3,S4,S5


T10

T6

T10

T6

SDVO Loss Budget

Serial Digital Video red output differential pair Serial Digital Video green output differential pair Serial Digital Video blue output differential pair Serial Digital Video clock output differential pair. Serial Digital Video interrupt input differential pair. Serial Digital Video TVOUT synchronization clock input Serial Digital Video Field Stall input differential pair. Serial Digital Video red output differential pair Serial Digital Video green output differential pair Serial Digital Video blue output differential pair Serial Digital Video clock output differential pair. Serial Digital Video interrupt input differential pair. Serial Digital Video TVOUT synchronization clock input Serial Digital Video Field Stall input differential pair.

SDVO I2C clock line -to set up SDVO peripherals. SDVO I2C data line -to set up SDVO peripherals. SDVO I2C clock line -to set up SDVO peripherals. SDVO I2C data line -to set up SDVO peripherals.

be pulled to 3.3V on the Carrier with a 100K Ohm resistor to configure the DDI[n]_AUX pair as the DDC

be placed on the Carrier for the SDVO RED, GRN, BLU, CK, INT, TVCLKIN, and FLDSTALL signals.The DDI signals can be used to support a variety of video interfaces. The circuits required to realize the different video interfaces will be determined by a future PICMG Carrier Design Guide subcommittee. At this time, thew only requirement placed on Modules for the DDI signals is the maximum trace length specified below.

SDVO Insertion Loss Budget

Allowance for module trace. Coupling cap effects included within simulation. COM Express™ connector simulated at 2.5 GHz. Allowance for Carrier Board trace.



Notes

V in S0,S1 and from x.xVSB in S3,S4,S5

Baseboard

Pin No. DDI-TMDS

B71 B72 B73 B74 B75 B76 B81 B82 D26 D27 D29 D30 D32 D33 D36 D37 D39 D40 D42 D43 D46 D47 D49 D50 C39 C40 C42 C43 C46 C47 C49 C50

B98

B99


TMDS0_DATA2+ O PCIE

AC coupled off Module TMDS0_DATA2-

TMDS0_DATA1+ O PCIE


TMDS0_DATA0+ O PCIE


TMDS0_CLK+ O PCIE

AC coupled off Module TMDS0_CLK-

TMDS1_DATA2+ O PCIE


TMDS1_DATA1+ O PCIE


TMDS1_DATA0+ O PCIE


TMDS1_CLK+ O PCIE


TMDS2_DATA2+ O PCIE


TMDS2_DATA1+ O PCIE


TMDS2_DATA0+ O PCIE


TMDS2_CLK+ O PCIE


TMDS3_DATA2+ O PCIE


TMDS3_DATA1+ O PCIE


TMDS3_DATA0+ O PCIE


TMDS3_CLK+ O PCIE


HMDI0_CTRLCLK I/O OD CMOS

3.3V / 3.3V

HMDI0_CTRLDATA I/O OD CMOS

3.3V / 3.3V

D15

D16

C32

C33

C36

C37

B89 I C24 I

D44 I

C44 I

TMDS Loss Budget

HMDI1_CTRLCLK I/O OD CMOS

3.3V / 3.3V

HMDI1_CTRLDATA I/O OD CMOS

3.3V / 3.3V

HDMI2_CTRLCLK I/O OD CMOS

3.3V / 3.3V

HDMI2_CTRLDATA I/O OD CMOS

3.3V / 3.3V

HDMI3_CTRLCLK I/O OD CMOS

3.3V / 3.3V

HDMI3_CTRLDATA I/O OD CMOS

3.3V / 3.3V

HDMI0_HPD 3.3V / 3.3V




When implementing HDMI level shifters shall be used on the TMDS signals. Bi-directional level shifters shall be used between the 3.3V and 5V CTRLCLK and CTRLDATA signals with 2.2kΩ pull-ups to 3.3V and 5V.

Carriers that support TMDS (DVI/HDMI): • DDI[n]_DDC_AUX_SEL shall be pulled to 3.3V on the Carrier with a 100K Ohm resistor to configure the DDI[n]_AUX pair as the DDC channel. • Bi-directional level translators shall be placed on the Carrier DDI[n]_CTRLDATA_AUX- and DDI[n]_CTRLCLK_AUX+ to convert the 3.3V DDC channel on the Module to the 5V DDC channel for the TMDS display. • Pull-up resistors shall be placed on the Carrier from 3.3V (Module side of level translator) and 5V (display side of level translator) and the [n]_CTRLDATA_AUX- and DDI[n]_CTRLCLK_AUX+ signals. The pull-up resistor should be 2k. • Level translators Shall be placed on the Carrier DDI[n]_PAIR[0:3] signals. • DC blocking capacitors shall be placed on the Carrier for the DDI[n]_PAIR[0:3] signals. • The Carrier shall include a blocking FET on DDI[n]_HPD to prevent back-drive current from damaging the module.

The DDI signals can be used to support a variety of video interfaces. The circuits required to realize the different video interfaces will be determined by a future PICMG Carrier Design Guide subcommittee. At this time, thew only requirement placed on Modules for the DDI signals is the maximum trace length specified below.

TMDS Insertion Loss Budget


COM Express™ connector simulated at 2.5 GHz.

TBD Allowance for Carrier Board trace.

Total TBD




LA

LB

LC



HDMI/DVI TMDS lanes 2 differential pairs

T10 HDMI/DVI TMDS lanes 1 differential pairs


HDMI/DVI TMDS Clock differential pair


T6












HDMI/DVI I2C control clock T10

HDMI/DVI I2C control data

HDMI/DVI I2C control clock

T6






HDMI/DVI Hot-Plug Detect T10 HDMI/DVI Hot-Plug Detect

T6 HDMI/DVI Hot-Plug Detect

HDMI/DVI Hot-Plug Detect

TMDS Loss Budget

be used on the TMDS signals. Bi-directional level shifters shall be used between the 3.3V and 5V CTRLCLK and CTRLDATA signals with 2.2kΩ pull-ups to 3.3V and 5V.

be pulled to 3.3V on the Carrier with a 100K Ohm resistor to configure the DDI[n]_AUX pair as the DDC

be placed on the Carrier DDI[n]_CTRLDATA_AUX- and DDI[n]_CTRLCLK_AUX+ to convert the 3.3V DDC channel on the Module to the 5V DDC channel for the TMDS display.

be placed on the Carrier from 3.3V (Module side of level translator) and 5V (display side of level translator) and the [n]_CTRLDATA_AUX- and DDI[n]_CTRLCLK_AUX+ signals. The pull-up resistor should be 2k.

be placed on the Carrier DDI[n]_PAIR[0:3] signals. be placed on the Carrier for the DDI[n]_PAIR[0:3] signals.

include a blocking FET on DDI[n]_HPD to prevent back-drive current from damaging the module.

The DDI signals can be used to support a variety of video interfaces. The circuits required to realize the different video interfaces will be determined by a future PICMG Carrier Design Guide subcommittee. At this time, thew only requirement placed on Modules for the DDI signals is the maximum trace length specified below.

TMDS Insertion Loss Budget

Allowance for module trace. Coupling cap effects included within simulation.


Allowance for Carrier Board trace.



Notes


Baseboard

N/A NA

6.5/10/15 6/6.5/15 L < 70006.5/10/15 6/6.5/15 L < 70006.5/10/15 6/6.5/15 L < 70006.5/10/15 6/6.5/15 L < 70006.5/10/15 6/6.5/15 L < 70006.5/10/15 6/6.5/15 L < 70006.5/10/15 6/6.5/15 L < 70006.5/10/15 6/6.5/15 L < 70006.5/10/15 6/6.5/15 L < 70006.5/10/15 6/6.5/15 L < 70006.5/10/15 6/6.5/15 L < 70006.5/10/15 6/6.5/15 L < 70006.5/10/15 6/6.5/15 L < 70006.5/10/15 6/6.5/15 L < 70006.5/10/15 6/6.5/15 L < 70006.5/10/15 6/6.5/15 L < 70006.5/10/15 6/6.5/15 L < 70006.5/10/15 6/6.5/15 L < 70006.5/10/15 6/6.5/15 L < 70006.5/10/15 6/6.5/15 L < 70006.5/10/15 6/6.5/15 L < 70006.5/10/15 6/6.5/15 L < 70006.5/10/15 6/6.5/15 L < 70006.5/10/15 6/6.5/15 L < 7000

N/A N/A


Haswell-MblChecklist

Length[mils]



Haswell-Mbl to HDMI/DVI Conn. - L < 7000 Level Shifter to HDMI/DVI Conn. - L < 1000



Haswell-Mbl to HDMI/DVI Conn. - L < 15000 COME to Level Shifter - L< 5000 Level Shifter to HDMI/DVI Conn. - L < 1500

6/12/12 6/12/12 L < 15000

6/12/12 6/12/12 L < 15000

6/12/12 6/12/12 L < 15000

6/12/12 6/12/12 L < 15000

6/12/12 6/12/12 L < 15000

6/12/12 6/12/12 L < 15000

N/A N/A6/12/12 6/12/12 ASAP6/12/12 6/12/12 ASAP6/12/12 6/12/12 ASAP



L < 1000 L < 7000

NA NA NA NA

2650.05 2650.052649.54 2649.542554.64 2554.642554.56 2554.562556.35 2556.352556.66 2556.662560.06 2560.062559.6 2559.6

2487.31 2487.312487.46 2487.462390.54 2390.542390.05 2390.052389.82 2389.822389.32 2389.322439.78 2439.782439.42 2439.422569.75 2569.752569.67 2569.672470.19 2470.192470.17 2470.172669.19 2669.192668.92 2668.922469.96 2469.962470.15 2470.15

L < 5000 L < 1500 L < 15000

N/A N/A N/A N/A


Length[mils]

COME to Level Shifter

Length[mils]

Level Shifter to HDMI/DVI Conn


1818.35 1818.35

2417.72 2417.72

3504.31 3504.31

3440.94 3440.94

2940.17 2940.17

2804.86 2804.86

N/A N/A N/A

L < 5 L < 1000

NA NA

0.510000000000218

95.490.079999999999927

0.309999999999945

0.460000000000036

0.150000000000091

98.140.489999999999782

0.5

0.360000000000127

0.079999999999927

199.230.019999999999982

0.269999999999982

0.190000000000055

N/A N/A


Inter-pair Length Matching[mils]

N/A N/A

Pin No. DDI-DisplayPort

B71 B72 B73 B74 B75 B76 B81 B82 D26 D27 D29 D30 D32 D33 D36 D37 D39 D40 D42 D43 D46 D47 D49 D50 C39 C40 C42 C43 C46 C47 C49 C50

Pin No. DDI-DisplayPort

B98 B99 D15 DP1_AUX+ D16 C32 C33


DP0_LANE0+

O PCIE

AC coupled off Module

DP0_LANE0- DP0_LANE1+ DP0_LANE1- DP0_LANE2+ DP0_LANE2- DP0_LANE3+ DP0_LANE3- DP1_LANE0+

O PCIE



O PCIE



O PCIE


DP3_LANE0- DP3_LANE1+ DP3_LANE1- DP3_LANE2+ DP3_LANE2- DP3_LANE3+ DP3_LANE3-


DP0_AUX+ I/O PCIE

AC coupled on Module DP0_AUX-

I/O PCIE


DP2_AUX+ I/O PCIE


C36 C37

B89 3.3V / 3.3V

C24 3.3V / 3.3V

D44 3.3V / 3.3V

C44 3.3V / 3.3V

DisplayPort Loss Budget

DisplayPort Insertion Loss Budget



TBD Allowance for Carrier Board trace.

Total TBD

DP3_AUX+ I/O PCIE


DP0_HPD I CMOS

DP1_HPD I CMOS

DP2_HPD I CMOS

DP3_HPD I CMOS

When implementing DisplayPort on the Carrier Board, the DP_AUX+ line shall have a pulldown resistor to GND. The resistor value should be 100kΩ. The DP_AUX- line shall have a pull-up resistor to 2.5V. The resistor value should be 100kΩ. The resistors shall be placed on the DisplayPort connector side of the AC coupling capacitors. The DP_HP signal shall include a blocking FET to prevent back-drive current damage. The DP_HP signal shall be pulled-down to GND with a 110kΩ resistor.

Carriers that support DisplayPort (DisplayPort only or dual mode): • DC blocking capacitors shall be placed on the Carrier for the DDI[n]_PAIR[0:3] signals. • The Carrier shall include a blocking FET on DDI[n]_HPD to prevent back-drive current from damaging the module.The DDI signals can be used to support a variety of video interfaces. The circuits required to realize the different video interfaces will be determined by a future PICMG Carrier Design Guide subcommittee. At this time, thew only requirement placed on Modules for the DDI signals is the maximum trace length specified below.


LA

LB

LC


PU - Pull UpPD - Pull DownJS - Jumper SelectionNL - No Loadedx.xV - Power active in S0x.xVSB - Power active in S0~S5x.xVDUAL - Power active from x.xV in S0,S1 and from x.xVSB in S3,S4,S5


T10

T6


T10

T6

Uni-directional main link for the transport of isochronous streams and secondary-data packets




Half-duplex bi-directional AUX channel for services such as link configuration or maintenance and EDID access Half-duplex bi-directional AUX channel for services such as link configuration or maintenance and EDID access Half-duplex bi-directional AUX channel for services such as link configuration or maintenance and EDID access

T6

T10

T6

DisplayPort Loss Budget

DisplayPort Insertion Loss Budget

Allowance for module trace. Coupling cap effects included within simulation.


Allowance for Carrier Board trace.

Half-duplex bi-directional AUX channel for services such as link configuration or maintenance and EDID access

Detection of Hot Plug / Unplug and notification of the link layer Detection of Hot Plug / Unplug and notification of the link layer Detection of Hot Plug / Unplug and notification of the link layer Detection of Hot Plug / Unplug and notification of the link layer

When implementing DisplayPort on the Carrier Board, the DP_AUX+ line shall have a pulldown resistor to GND. The resistor value should have a pull-up resistor to 2.5V. The resistor value should be 100kΩ. The resistors shall be placed on

the DisplayPort connector side of the AC coupling capacitors. The DP_HP signal shall include a blocking FET to prevent back-drive current be pulled-down to GND with a 110kΩ resistor.

Carriers that support DisplayPort (DisplayPort only or dual mode): be placed on the Carrier for the DDI[n]_PAIR[0:3] signals.

include a blocking FET on DDI[n]_HPD to prevent back-drive current from damaging the module.The DDI signals can be used to support a variety of video interfaces. The circuits required to realize the different video interfaces will be determined by a future PICMG Carrier Design Guide subcommittee. At this time, thew only requirement placed on Modules for the DDI signals is the maximum trace length specified below.

Notes

Baseboard

N/A N/A

6.5/10/15 6/6.5/15 L<72006.5/10/15 6/6.5/15 L<72006.5/10/15 6/6.5/15 L<72006.5/10/15 6/6.5/15 L<72006.5/10/15 6/6.5/15 L<72006.5/10/15 6/6.5/15 L<72006.5/10/15 6/6.5/15 L<72006.5/10/15 6/6.5/15 L<72006.5/10/15 6/6.5/15 L<72006.5/10/15 6/6.5/15 L<72006.5/10/15 6/6.5/15 L<72006.5/10/15 6/6.5/15 L<72006.5/10/15 6/6.5/15 L<72006.5/10/15 6/6.5/15 L<72006.5/10/15 6/6.5/15 L<72006.5/10/15 6/6.5/15 L<72006.5/10/15 6/6.5/15 L<72006.5/10/15 6/6.5/15 L<72006.5/10/15 6/6.5/15 L<72006.5/10/15 6/6.5/15 L<72006.5/10/15 6/6.5/15 L<72006.5/10/15 6/6.5/15 L<72006.5/10/15 6/6.5/15 L<72006.5/10/15 6/6.5/15 L<7200

Baseboard

N/A N/A

6.5/10/15 6/6.5/15 L<130006.5/10/15 6/6.5/15 L<130006.5/10/15 6/6.5/15 L<130006.5/10/15 6/6.5/15 L<13000



Length[mils]



1. Haswell-Mbl to DisplayPort Connector - HBR/HBR2 - L < 7200



Length[mils]



1. Haswell-Mbl to DisplayPort Connector - AUX Channel - L < 13000

6.5/10/15 6/6.5/15 L<130006.5/10/15 6/6.5/15 L<13000

N/A N/A

6/12/12 6/12/12 ASAP

6/12/12 6/12/12 ASAP

6/12/12 6/12/12 ASAP

1

1



1. Haswell-Mbl to DisplayPort Connector - HBR/HBR2 - L < 7200

2. Haswell-Mbl to DisplayPort Connector - HBR/HBR2 w/Redriver - L < 11500 COME to DisplayPort Connector - L < 5600 COME to Caps - L < 3600 Caps to Redriver - L < 100 Redriver to Caps - L < 1100 Caps to DisplayPort Connector - L < 600

1. Haswell-Mbl to DisplayPort Connector - AUX Channel - L < 13000

2. Haswell-Mbl to DisplayPort Connector - Aux Channel w/Redriver - L < 14000 COME to DisplayPort Connector - L < 7000 COME to Caps - L < 4200 Caps to Redriver - L < 100 Redriver to Caps - L < 100 Caps to DisplayPort Connector - L < 4200

N/A N/A N/A N/A

2650.052649.542554.642554.562556.352556.662560.062559.6

2487.312487.462390.542390.052389.822389.322439.782439.422569.752569.672470.192470.172669.192668.922469.962470.15

N/A N/A N/A N/A

2633.742634.143907.3

3907.63


Length[mils]


Length[mils]

3055.253056.25

N/A

L<7200 L < 5

N/A N/A N/A N/A

2650.05 0.5100000000002182649.542554.64 0.0799999999999272554.562556.35 0.3099999999999452556.662560.06 0.4600000000000362559.62487.31 0.1500000000000912487.462390.54 0.4899999999997822390.052389.82 0.52389.322439.78 0.3600000000001272439.422569.75 0.0799999999999272569.672470.19 0.0199999999999822470.172669.19 0.2699999999999822668.922469.96 0.1900000000000552470.15

L<13000 L < 5

N/A N/A N/A N/A

2633.74 0.4000000000000912634.143907.3 0.3299999999999273907.63

COME to Display Conn.



COME to Display Conn.



3055.25 13056.25

N/A N/A

L < 1000

N/A

95.4900000000002

98.1399999999999

199.23

N/A



Pin No. PCI Bus Pin Type Description

C24D22C25D23C26D24C27D25C28D27C29D28C30D29C32D30D37C39D38C40D39C42D40C43D42C45D43C46D44C47D45C48D26C33


PICMG DG 1.0Module

Length[mils]


Length[mils]

Address/Data Control signals

Transfer Rate @ 33MHz - 132 MB/secSE - 55 Ω +/-15%

PCI_AD0

I/O CMOS

3.3V / 5V PCI bus multiplexed address and data lines

Spacing - from edge of plane - Min. 40milsLength -data and control signal - Max. 10 inchesclock signal - Max. 8.88 inchesLength matching - single ended signals - Max. 200milsclock signals - Max. 200milsReference plane - GND referenced preferredVia Usage - Try to minimize number of viasDecoupling capacitors for each PCI slot - Min. 1x22µF, 2x 100nF @ VCC 5VMin. 2x22µF, 4x 100nF @ VCC 3.3VMin. 1x22µF, 2x 100nF @ +12V (if used)Min. 1x22µF, 2x 100nF @ -12V (if used)The decoupling capacitors for the power rails should be placed as close as possible to the slot power pins, connected with wide traces.

PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31 PCI_C/BE0#

I/O CMOS

3.3V / 5V PCI bus byte enable lines, active low PCI_C/BE1#

C38C44

C36

D36

C37

D35

D34

D32

C34

C22C19C17D20C20C18C16D19

C23

C35

D33

C15

D48

C49C50D46D47

D49

I/O CMOS

3.3V / 5V PCI bus byte enable lines, active low


PCI_C/BE2# PCI_C/BE3#

PCI_DEVSEL# I/O CMOS

3.3V / 5V PCI bus Device Select, active low.

PCI_FRAME# I/O CMOS

3.3V / 5V PCI bus Frame control line, active low.

PCI_IRDY# I/O CMOS

3.3V / 5V PCI bus Initiator Ready control line, active low.

PCI_TRDY# I/O CMOS

3.3V / 5V PCI bus Target Ready control line, active low.

PCI_STOP# I/O CMOS

3.3V / 5V

PCI bus STOP control line, active low, driven by cycle initiator.

PCI_PAR I/O CMOS

3.3V / 5V PCI bus parity

PCI_PERR# I/O CMOS

3.3V / 5V

Parity Error: An external PCI device drives PERR# when it receives data that has a parity error.

PCI_REQ0# I CMOS

3.3V / 5V PCI bus master request input lines, active low. PCI_REQ1#

PCI_REQ2# PCI_REQ3# PCI_GNT0#

O CMOS

3.3V / 5V PCI bus master grant output lines, active low. PCI_GNT1#

PCI_GNT2# PCI_GNT3#

PCI_RESET# O CMOS

3.3V / 5V Suspend PCI Reset output, active low.

PCI_LOCK# I/O CMOS

3.3V / 5V PCI Lock control line, active low.

PCI_SERR# I/O OD CMOS

3.3V / 5V

System Error: SERR# may be pulsed active by any PCI device that detects a system error condition.

PCI_PME# I CMOS

3.3V / 5V Suspend

PCI Power Management Event: PCI peripherals drive PME# to wake system from low-power states S1–S5.

PCI_CLKRUN# I/O CMOS

3.3V / 5V

Bidirectional pin used to support PCI clock run protocol for mobile systems.

PCI_IRQA# I CMOS

3.3V / 5V PCI interrupt request lines. PCI_IRQB#

PCI_IRQC# PCI_IRQD#

PCI_M66EN I CMOS

3.3V / 5V

operation. If the module is not capable of supporting 66 MHz PCI operation, this input maybe a no-connect on the module.

Clock

D50

IDSEL


PCI_CLK O CMOS

3.3V / 3.3V PCI 33MHz clock output.

I COMS

3.3V / 5V

address for PCI configuration cycles. The IDSEL pin of each device is typically connected to one of the AD lines to set a unique configuration address.

Carrier Board PCI Resource Allocation

IDSEL

PCI Clock

PCI Clocks

On COM ExpressTM modules with Type 2 and 3 pin-outs four off-module PCI devices shall be supported. The off-module devices are referred to as Slot 0,1,2,3 devices. They may be PCI slots (connectors) on the Carrier Board, or they may be actual PCI devices on the Carrier Board itself. The PCI implementation shall support four REQ / GNT pairs for off-module use.

Slot / DeviceSignal Slot / Device 0 Slot / Device 1

Slot / Device 2 Slot / Device 3

PCI_AD[20] PCI_AD[21] PCI_AD[22] PCI_AD[23]

PCI_CLK replica PCI_CLK replica PCI_CLK replica PCI_CLK replica

INTA# PCI_IRQ[A]# PCI_IRQ[B]# PCI_IRQ[C]# PCI_IRQ[D]# INTB# (if used) PCI_IRQ[B]# PCI_IRQ[C]# PCI_IRQ[D]# PCI_IRQ[A]# INTC# (if used) PCI_IRQ[C]# PCI_IRQ[D]# PCI_IRQ[A]# PCI_IRQ[B]# INTD# (if used) PCI_IRQ[D]# PCI_IRQ[A]# PCI_IRQ[B]# PCI_IRQ[C]#

REQ0# (if used) PCI_REQ[0]# PCI_REQ[1]# PCI_REQ[2]# PCI_REQ[3]# REQ1# (if used) PCI_REQ[1]# PCI_REQ[2]# PCI_REQ[3]# PCI_REQ[0]# REQ2# (if used) PCI_REQ[2]# PCI_REQ[3]# PCI_REQ[0]# PCI_REQ[1]# REQ3# (if used) PCI_REQ[3]# PCI_REQ[0]# PCI_REQ[1]# PCI_REQ[2]#

GNT0# (if used) PCI_GNT[0]# PCI_GNT[1]# PCI_GNT[2]# PCI_GNT[3]# GNT1# (if used) PCI_GNT[1]# PCI_GNT[2]# PCI_GNT[3]# PCI_GNT[0]# GNT2# (if used) PCI_GNT[2]# PCI_GNT[3]# PCI_GNT[0]# PCI_GNT[1]# GNT3# (if used) PCI_GNT[3]# PCI_GNT[0]# PCI_GNT[1]# PCI_GNT[2]#

PCI Clocks — Carrier Board PCI Device PCI Clocks — Slot Card PCI Device

COM ExpressTM specifies only a single copy of the PCI clock for off-moduleCarrier Board target device use. If only one Carrier Board PCI device is implemented, then that single clock may be routed to the device. If more than one Carrier Board PCI device is implemented, then the Carrier Board should replicate the PCI clock using a zero delay buffer. The zero delay buffer if used should support spread spectrum clocking. See the Carrier Design Guide for specific commendations of buffers that support spread spectrum clocking. The Module EEPROM spread spectrum clocking bit should be set appropriately so that the Module can determine the capabilities of the Carrier Board. The PCI Local Bus Specification requires that PCI clocks be synchronous within a 2 ns window at the destination devices; that the maximum propagation delay for the clock be 10 ns, and that PCI slot based add-on cards implement a PCI clock trace length of 2.5 inches. COM ExpressTM Carrier Board implementations should allow 1.6 ns +/- 0.1 ns for the PCI clock propagation delay from the COM ExpressTM module connector pin to the destination device pin. Propagation delay varies with construction details such as trace geometry, PCB stack up, and PCB material dielectric constant. Propagation delay values of 140 ps / inch to 180 ps / inch are common for outer layer traces. A propagation delay value of 180 ps / inch is common for inner layer traces. Using 180 ps /inch as the propagation delay value for an inner layer Carrier Board PCI clock, then the COM ExpressTM Carrier Board delay of 1.6 ns works out to 8.88 inches of trace. If the destination device is on an add on card, then the propagation delay associated with the 2.5 inches of add on card trace are deducted from the 1.6 ns. Using 160 ps / inch as a typical value for an outer layer slot card clock trace, the 2.5 inches of slot card clock trace length work out to a propagation delay of 0.4 ns. The Carrier Board PCI clock delay in this example would be 1.6 ns – 0.4 ns or 1.2 ns.The following definitions and equations apply: TMD Propagation delay: module PCI clock source to on-module PCI device TMC Propagation delay: module PCI clock source to module connector PCI clock pin TCD Propagation delay: module connector to Carrier Board device. Fixed by COM ExpressTM Specification at 1.6 ns TCS Propagation delay: module connector to slot connector pin LSD Length: slot card connector pin to slot card device. Fixed by PCI Local Bus Specification at 2.5 inches PSD Inverse propagation speed: slot card connector pin to slot card device (units of time / length) Determined by slot card PCB design; typical value 160 ps / inch TMD = TMC + TCD

TMD = TMC + TCS + LSD * PSD

TCS = TCD – LSD * PSD

The parameters TMD and TMC apply to module designs. Module designers should minimize TMC, and then arrange that TMD satisfies the relation TMD = TMC + TCD.

TMD = TMC + TCD


TMD = TMC + TCS + LSD * PSDTCS = TCD – LSD*PSD

Pin No. USB Pin Type Description

A46A45B46B45A43A42B43B42A40A39B40B39A37A36B37B36

D4 O PCIE D3D7 O PCIE D6

D10 O PCIE D9D13 O PCIE D12


PICMG DG 1.0Module

Length[mils]Transfer rate / Port - Up to 2.0 GBit/sDP - 90 Ω +/-15%SE - 45 Ω +/-10%Total length - Max. 17.0 inches

USB0+

I/O USB

3.3V / 3.3V Suspend USB differential pairs, channels 0 through 7 Length -

Max 3.0 inches

USB0- USB1+ USB1- USB2+ USB2- USB3+ USB3- USB4+ USB4- USB5+ USB5- USB6+ USB6- USB7+ USB7-

USB_SSTX0+ AC coupled on Module

Additional transmit signal differential pairs for the SuperSpeed USB data path. USB_SSTX0-







C4 I PCIE C3C7 I PCIE C6

C10 I PCIE C9C13 I PCIE C12

B44

A44

B38

A38

USB_SSRX0+ AC coupled on Module

Additional receive signal differential pairs for the SuperSpeed USB data path. USB_SSRX0-







USB_0_1_OC# I CMOS

3.3V / 3.3V Suspend

USB over-current sense, USB channels 0 and 1. A pull-up for this line shall be present on the module. An open drain driver from a USB current monitor on the Carrier Board may drive this line low. Do not pull this line high on the Carrier Board.

USB_2_3_OC# I CMOS

3.3V / 3.3V Suspend


USB_4_5_OC# I CMOS

3.3V / 3.3V Suspend


USB_6_7_OC# I CMOS

3.3V / 3.3V Suspend


USB_VCC Power 5V / 5VSuspend

1. Intel recommends one 220 µF and two 470 pF capacitors for every two power lines. 2. Either a thermister or a power distribution switch (with short circuit and thermal protection) is required

All USB interfaces shall be USB 2.0 compliant. The minimum of 4 USB channels provides support for keyboard, mouse, CD/DVD drive, and one additional device. Up to four of the eight USB 2.0 ports can support the extended signaling for SuperSpeed USB 3.0. Note that this usage is not required and the actual Carrier Board usage of the USB port is not defined by this specification. USB7 may optionally be configured as a USB client.

USB Insertion Loss Budget

USB Insertion Loss Budget, 400 MHz Segment Loss (dB) Notes

0.67 Up to 6 inches of module trace @ 0.28 dB / GHz / inch0.05 COM ExpressTM connector at 400 MHz measured value1.68 Up to 14 inches of Carrier Board trace @ 0.28 dB / GHz / inch1.00 USB connector and ferrite loss5.80 USB cable and far end connector loss, per source specification

No termination is required on USB pairs. A common mode choke is advisable if USB pairs on the Carrier Board are routed to a connector for use with an external cable.Signals USB_0_1_OC#, USB_2_3_OC#, USB_4_5_OC# and USB_6_7_OC# are used to flag a USB over-current situation. Carrier Board USB current monitors may pull these lines to GND with open drain drivers to indicate that the monitor’s current limit has been exceeded. Do not pull up these lines to 3.3V on the Carrier Board – this shall be done on the module. If a USB 2.0 Debug port is present it should be routed to port 0.

The Module shall provide the termination for the signals below. The following signals should be pulled-up to 3.3V Standby with a 10kΩ resistor• USB_[0,2,4,6]_[1,3,5,7]_OC#

LA

LB

LC

LD

LE

Total 9.20


COM ExpressTM USB implementations should conform to insertion loss values less than or equal to those shown in the table above. The insertion loss values shown account for frequency dependent material losses only. Cross talk losses are separate from material losses in the USB specification.

"Device Down” implementations, in which the USB target device is implemented on the Carrier Board, may add the ferrite and USB connector insertion loss values to the Carrier Board budget.

The Carrier Board insertion loss budget then becomes LC + LD, or 2.68 dB.

3000 < L < 10000

6.5/10/15 6/6.5/15 3000 < L < 10000 3028.87 3028.876.5/10/15 6/6.5/15 3000 < L < 10000 3029.31 3029.316.5/10/15 6/6.5/15 3000 < L < 10000 2383.84 2383.846.5/10/15 6/6.5/15 3000 < L < 10000 2383.24 2383.246.5/10/15 6/6.5/15 3000 < L < 10000 3274.91 3274.916.5/10/15 6/6.5/15 3000 < L < 10000 3274.82 3274.826.5/10/15 6/6.5/15 3000 < L < 10000 2779 27796.5/10/15 6/6.5/15 3000 < L < 10000 2779.32 2779.326.5/10/15 6/6.5/15 3000 < L < 10000 2721.53 2721.536.5/10/15 6/6.5/15 3000 < L < 10000 2721.21 2721.216.5/10/15 6/6.5/15 3000 < L < 10000 3692.1 3692.16.5/10/15 6/6.5/15 3000 < L < 10000 3692.1 3692.16.5/10/15 6/6.5/15 3000 < L < 10000 2858.71 2858.716.5/10/15 6/6.5/15 3000 < L < 10000 2859.39 2859.396.5/10/15 6/6.5/15 3000 < L < 10000 2561.61 2561.616.5/10/15 6/6.5/15 3000 < L < 10000 2561.8 2561.8

3000<L<10000

6.5/10/20 6/6.5/20 3000<L<10000 1086.15 1086.156.5/10/20 6/6.5/20 3000<L<10000 1086.85 1086.856.5/10/20 6/6.5/20 3000<L<10000 982.49 982.496.5/10/20 6/6.5/20 3000<L<10000 983.05 983.056.5/10/20 6/6.5/20 3000<L<10000 1039.73 1039.736.5/10/20 6/6.5/20 3000<L<10000 1038.85 1038.856.5/10/20 6/6.5/20 3000<L<10000 940.29 940.296.5/10/20 6/6.5/20 3000<L<10000 939.26 939.26



Width/ Space/ Other space [mils]LynxPoint-M



Length[mils]



Transfer rate / Port - Up to 2.0 GBit/s - 90 Ω +/-15% - 45 Ω +/-10%

Total length - Max. 17.0 inches



LynxPoint-M to USB Connector

(inter-pair) - Min. 20milsfom high-speed periodic signals - Min. 50milsfrom low-speed non periodic signals - Min. 20milsfrom edge of plane - Min. 40milsLength - Max 14.0 inchesLength matching -differential pairs (intra-pair) - 150milsReference plane - GND referenced preferredVia Usage -



1. LynxPoint-M to USB ConnectorTotal Length - 3000 < L < 10000

6.5/10/20 6/6.5/20 3000<L<10000 1485.64 1485.646.5/10/20 6/6.5/20 3000<L<10000 1484.94 1484.946.5/10/20 6/6.5/20 3000<L<10000 1359.17 1359.176.5/10/20 6/6.5/20 3000<L<10000 1358.35 1358.356.5/10/20 6/6.5/20 3000<L<10000 1368.19 1368.196.5/10/20 6/6.5/20 3000<L<10000 1367.2 1367.26.5/10/20 6/6.5/20 3000<L<10000 1404.6 1404.66.5/10/20 6/6.5/20 3000<L<10000 1405.49 1405.49

6/12/12 6/12/12 ASAP

6/12/12 6/12/12 ASAP

6/12/12 6/12/12 ASAP

6/12/12 6/12/12 ASAP



1

1. LynxPoint-M to USB ConnectorTotal Length - 3000 < L < 10000

2. LynxPoint-M to RedriverTotal Length - L < 14000 COME to Redriver - L < 4000

L < 20 L < 500

0.440000000000055

0.600000000000364

0.089999999999691

0.320000000000164

0.320000000000164

0

0.679999999999836

0.190000000000055

L < 5 L < 600

0.699999999999818

0.559999999999945

0.880000000000109

1.02999999999997


ESD to USB Conn.Length[mils]

0.700000000000046

0.820000000000164

0.990000000000009

0.8900000000001

Pin No. LVDS Flat Panel Pin Type Description

-

A78

A79

A81

A82

B71

B72

B73

B74

B75

B76

B77

B78


PICMG DG 1.0Module

Length[mils]

DP - 100 Ω +/-20%SE - 55 Ω +/-15%Total length - Max. 8.75 inches

A71 LVDS_A0+

O LVDS LVDS Channel A differential pairs


A72 LVDS_A0-

A73 LVDS_A1+

A74 LVDS_A1-

A75 LVDS_A2+

A76 LVDS_A2-

LVDS_A3+

LVDS_A3-

LVDS_A_CK+ O LVDS LVDS Channel A differential clock

LVDS_A_CK-

LVDS_B0+

O LVDS LVDS Channel B differential pairs

LVDS_B0-

LVDS_B1+

LVDS_B1-

LVDS_B2+

LVDS_B2-

LVDS_B3+

LVDS_B3-

B81

B82

A83

A84

A77

B79

B83



LVDS_B_CK+ O LVDS LVDS Channel B differential clock

LVDS_B_CK-

LVDS_I2C_CK O CMOS

3.3V / 3.3V I2C clock output for LVDS display use

LVDS_I2C_DAT I/O OD CMOS

3.3V / 3.3V I2C data line for LVDS display use

LVDS_VDD_EN O CMOS

3.3V / 3.3V LVDS panel power enable

LVDS_BKLT_EN O CMOS

3.3V / 3.3V LVDS panel backlight enable

LVDS_BKLT_CTRL O CMOS

3.3V / 3.3V LVDS panel backlight brightness control

The LVDS flat panel differential pairs (LVDS_A[0:3]+/-, LVDS_B[0:3]+/-. LVDS_A_CK+/-, LVDS_B_CK+/-) shall have 100Ω terminations across the pairs at the destination. This may be on the Carrier Board, if the Carrier Board implements a LVDS de-serializer on-board.

not used LVDS lines may be left open.

ASAP

5/10/20 5/10/20 ASAP 2214.32 2214.32

5/10/20 5/10/20 ASAP 2215.87 2215.87

5/10/20 5/10/20 ASAP 2214.36 2214.36

5/10/20 5/10/20 ASAP 2215.4 2215.4

5/10/20 5/10/20 ASAP 2215.28 2215.28

5/10/20 5/10/20 ASAP 2215.26 2215.26

5/10/20 5/10/20 ASAP 2214.88 2214.88

5/10/20 5/10/20 ASAP 2214.68 2214.68

5/10/20 5/10/20 ASAP 2215.44 2215.44

5/10/20 5/10/20 ASAP 2215.06 2215.06

5/10/20 5/10/20 ASAP 2214.66 2214.66

5/10/20 5/10/20 ASAP 2215.76 2215.76

5/10/20 5/10/20 ASAP 2215.28 2215.28

5/10/20 5/10/20 ASAP 2214.76 2214.76

5/10/20 5/10/20 ASAP 2214.96 2214.96

5/10/20 5/10/20 ASAP 2214.81 2214.81

5/10/20 5/10/20 ASAP 2215.15 2215.15

5/10/20 5/10/20 ASAP 2214.76 2214.76



Width/ Space/ Other space [mils]CH7511



Length[mils]



DP - 100 Ω +/-20%SE - 55 Ω +/-15%Total length - Max. 8.75 inches



CH7511 to LVDS Connector

Spacing - pair to pairs (inter-pair) - Min. 20milsfrom high-speed periodic signals - Min. 20milsfrom low-speed non periodic signals - Min. 20milsfrom edge of plane - Max. 40milsLength - Max. 6.75 inchesLength matching - differential pairs (intra-pair) - Max. 20milsclock and data pairs (inter-pair) - Max. 20milsdata pairs (inter-pair) - Max. 40milsReference plane - GND referenced preferredVia Usage - Max. of 2 vias per line

5/10/20 5/10/20 ASAP 2215.06 2215.06

5/10/20 5/10/20 ASAP 2214.89 2214.89

5/7/7 5/7/7 ASAP

5/7/7 5/7/7 ASAP

5/7/7 5/7/7 ASAP

5/7/7 5/7/7 ASAP

5/7/7 5/7/7 ASAP


Spacing - pair to pairs (inter-pair) - Min. 20milsfrom high-speed periodic signals - Min. 20milsfrom low-speed non periodic signals - Min. 20milsfrom edge of plane - Max. 40milsLength - Max. 6.75 inchesLength matching - differential pairs (intra-pair) - Max. 20milsclock and data pairs (inter-pair) - Max. 20milsdata pairs (inter-pair) - Max. 40milsReference plane - GND referenced preferredVia Usage - Max. of 2 vias per line



L < 5 L < 10

1.54999999999973

1.54999999999973

1.03999999999996

0.019999999999982

0.200000000000273

0.380000000000109

1.10000000000036

0.519999999999982

0.150000000000091

0.389999999999873



0.170000000000073

1.54999999999973

Pin No. Analog VGA Pin Type Description

RGB

B89

B92

B93

B94

B95

B96



PICMG DG 1.0Module

Length[mils]

VGA_RED O Analog 0.7 V p-p Red for monitor. Analog DAC output, designed to

drive a 37.5Ω equivalent load.

B91 VGA_GRN O Analog 0.7 V p-p Green for monitor. Analog DAC output, designed

to drive a 37.5Ω equivalent load.

VGA_BLU O Analog 0.7 V p-p Blue for monitor. Analog DAC output, designed

to drive a 37.5Ω equivalent load.

VGA_HSYNC O CMOS

3.3V / 3.3V Horizontal sync output to VGA monitor

VGA_VSYNC O CMOS

3.3V / 3.3V Vertical sync output to VGA monitor

VGA_I2C_CK O CMOS

3.3V / 3.3V

DDC clock line (I2C port dedicated to identify VGA monitor capabilities)

VGA_I2C_DAT I/O OD CMOS

3.3V / 3.3V DDC data line.

If analog VGA is used, the VGA_RED, VGA_GRN, and VGA_BLU signals shall each be terminated on the Carrier Board through a 150 Ω resistor to ground. These resistors should be placed close to the VGA connector on the Carrier Board. These lines may be left unterminated if the analog VGA function is not used.

6/20/30 4/20/30 6/20/30 4/20/30 L < 15100 2755

6/20/30 4/20/30 6/20/30 4/20/30 L < 15100 2753.6

6/20/30 4/20/30 6/20/30 4/20/30 L < 15100 2754.19

6/12/20 6/12/20 L < 15100 3632.95

6/12/20 6/12/20 L < 15100 3758.24

6/5/10 6/5/10 L < 20500 2981.43

6/5/10 6/5/10 L < 20500 2876.53







Length[mils]

Inner LayerSE - COME to

R_150Ω - 50Ω ± 10%

Inner LayerSE - R_150Ω to

VGA - 75Ω ± 10%

Outer LayerSE - COME to

R_150Ω - 50Ω ± 15%

Outer LayerSE - R_150Ω to

VGA - 75Ω ± 15%LynxPoint-M to VGA Connector





L < 6300 L < 15100 L < 200 L < 300

2755

1.400000000000092753.6

2754.19

L < 6500 L < 15100 L < 200 L < 500

3632.95125.29

3758.24

L < 6000 L < 20500

2981.43

-104.92876.53




DAC - R_150Ω to VGA Conn.

SYNC - ESD to VGA Conn.

Length[mils]

0 < DAT - CLK < 1000

Pin No. TV Out Pin Type Description

B97

B99



PICMG DG 1.0Module

Length[mils]

TV_DAC_A O Analog

TVDAC Channel A Output supports the following: Composite video: CVBS Component video: Chrominance (Pb) analog signal S-Video: not used

B98 TV_DAC_B O Analog

TVDAC Channel B Output supports the following: Composite video: not used Component video: Luminance (Y) analog signal. S-Video: Luminance analog signal.

TV_DAC_C O Analog

TVDAC Channel C Output supports the following: Composite video: not used Component: Chrominance (Pr) analog signal. S-Video: Chrominance analog signal.



Length[mils]

Pin No.

B10

B4

B5

B6

B7

B3

B8

B9

A50


LPC Interface Pin Type Pwr Rail / Tolerance Description

PICMG DG 1.0Module

Length[mils]

Transfer Rate @ 33MHzSE - 55 Ω +/-15%

LPC_CLK O CMOS

3.3V / 3.3V

LPC clock output - 33MHz nominal Carrier Board LPC devices should be clocked with the LPC clock provided by the module interface. LPC clock length guidelines are the same as those for the PCI clock.

LPC_AD0

I/O CMOS

3.3V / 3.3V

LPC multiplexed address, command and data bus

LPC_AD1

LPC_AD2

LPC_AD3

LPC_FRAME# O CMOS

3.3V / 3.3V LPC frame indicates the start of an LPC cycle

LPC_DRQ0# I CMOS

3.3V / 3.3V LPC serial DMA request

LPC_DRQ1#

LPC_SERIRQ I/O CMOS

3.3V / 3.3V LPC serial interrupt

L < 15000

6/20/20 6/20/20 L < 15000 4447.14 4447.14

6/12/12 6/12/12 ASAP

6/12/12 6/12/12 ASAP

6/12/12 6/12/12 ASAP

6/12/12 6/12/12 ASAP

6/12/12 6/12/12 ASAP

6/12/12 6/12/12 ASAP

6/12/12 6/12/12 ASAP

6/12/12 6/12/12 ASAP







Length[mils]



Transfer Rate @ 33MHz - 16 MBit/s - 55 Ω +/-15%



LynxPoint-M to LPC Device

Spacing - from edge of plane - Min. 40milsLength - data and control signal - Max 15.0 inchesclock signal - Max. 8.88 inchesLength matching - single ended signals - Max. 200milsclock signals - Max. 200milsReference plane - GND referenced preferredVia Usage - Try to minimize number of vias

Pin No. SPI Pin Type Description

A94 SPI_CLK Clock from Module to Carrier SPI

A95 Data out from Module to Carrier SPI

B97

A92 Data in to Module from Carrier SPI

A91 O

Effect of the BIOS disable signals


O CMOS

3.3V Suspend / 3.3V

SPI_MOSI O CMOS

3.3V Suspend / 3.3V

SPI_CS# O CMOS

3.3V Suspend / 3.3V

Chip select for Carrier Board SPI - SPI0 or SPI1

SPI_MISO I CMOS

3.3V Suspend / 3.3V

SPI_POWER 3.3V Suspend / 3.3V

Power supply for Carrier Board SPI – sourced from Module – nominally 3.3V. The Module shall provide a minimum of 100mA on SPI_POWER. Carriers shall use less than 100mA of SPI_POWER. SPI_POWER shall only be used to power SPI devices on the Carrier

SPI. The SPI bus is used to support a SPI-compatible flash devices. The SPI flash device can be up to 16 MB (128 Mb). The SPI bus is clocked at either 20 MHz, 25 MHz, 33 MHz or 50 MHz. SPI devices selected should support one of these frequencies. SPI support is introduced in COM.0 R2.0 for all Types.

The Module shall provide the termination for the signals below. The following signals should be pulled-up to 3.3V with a 10kΩ resistor• BIOS_DISABLE# When supporting Carrier Board based SPI devices, the SPI_MISO line shall have a series resistor of 33Ω.

On COM.0 R1.0, there is a single pin dedicated to the BIOS Disable function. The pin is A34, named BIOS_DISABLE#. If the Carrier Board leaves BIOS_DISABLE# floating, then the Module boots from the BIOS on the Module. That Module BIOS can be on any bus the Module designer chooses (LPC. SPI, etc.). If the Carrier Board pulls BIOS_DISABLE# to GND, then the on-Module BIOS is disabled and the Module boots from a Carrier Board firmware hub on the LPC bus.

In COM.0 R2.0, the Carrier based BIOS options have been expanded to support SPI devices. A second BIOS DISABLE pin (BIOS_DIS1#) has been added to allow for multiple Carrier implementations for external BIOS devices. The BIOS_DISABLE# pin has been renamed to BIOS_DIS0#. Additional pins have been added to bring the SPI signals to the Carrier. These pins are defined in Table 4.12 above.

The Table 4.13 below allows for Carrier Board LPC FWH operation that is backward compatible with COM.0 Rev.1 Carriers. It also allows two Carrier SPI options: SPI0 on Carrier and SPI1 on the Module, or SPI0 on the Module and SP1 on the Carrier.

BIOS_DIS1# BIOS_DIS0# Chipset SPI CS1# Destination

Chipset SPI CS0# Destination Carrier SPI_CS#

1 1 Module Module High

1 0 Module Module High

0 1 Module Carrier SPI0

0 0 Carrier Module SPI1

SPI Power

Module Vs Carrier Board Pull-ups

5.7 SPI Devices

Figure 5-10: Typical SPI topology

The BIOS Entry point may be in SPI0 or SPI1 as determined by the descriptor table in the SPI0 device. The Module may have one or two SPI devices, or a FWH. Carrier Boards may have zero or one SPI device, and may have zero or one LPC FWH.

With special circuitry on the Module it's possible to have a single SPI device, but allow the Module GBE, ME and Platform data to stay with the Module even in the case of a Carrier Board SPI BIOS entry per Ref Line 2 above. The Module SPI would include a descriptor table, BIOS code, GBE parameters, ME parameters, and platform data. For table line entries 0 and 1 above, the Module SPI device would be selected by SPI CS0# from the chipset. For table line entry 2 above, the Module SPI device would be selected by chipset SPI CS1# instead of CS0#. This would be achieved by low cost circuitry on the Module. The Module SPI device descriptor table and the Module BIOS code would be used in table line entries 0, 1 and 3.

An alternative arrangement would be to have two SPI devices on the Module. The descriptor table and the actual BIOS are in SPI0, and that the GBE LAN data, ME data and platform data reside in SPI1. Then a Carrier Board SPI option is allowed (table line ref 2) in which the actual BIOS is on the Carrier, and the Module specific data stays with the Module in SPI1. The Module SPI1 device has to be write-enabled. The Carrier SPI0 device could be write protected if desired (as is the case in some regulated industries such as casino gaming).

Note that in the case of the BIOS boot from Carrier FWH (table line ref 1), the module SPI devices are still enabled and active. They are used by the GBE LAN hardware and the management engine. They can keep the BIOS code as well, but it is not used. The ICH pin straps cause an LPC FWH BIOS boot.

Introducing a SPI_POWER pin is desirable because some Module implementations will have the SPI power domain in power state S0 and others in S5. It is easier for Carrier board designers to take the Carrier SPI power from a pin on the Module.

There shall not be any Carrier Board pull-ups or pull-downs on the seven SPI related signals. All such terminations shall be on the Module. The Module designer shall determine the correct power domain that these signals are terminated to.

All Module types may implement a SPI bus. The SPI bus is replacing the LPC bus for BIOS EEPROM devices. If a Module supports an external BIOS is shall support an external SPI BIOS and may support an external LPC BIOS. The diagram below depicts a typical SPI topology. Note that other SPI configurations are possible including Module or Carrier based CS1# SPI device. See Section 4.3.12 'SPI Interface' for other implementation options.

(LA1 + LB1), (LA2 + LB2), (LA3 + LC3 + LB3), (LA4 + LB4) max length 2” match all within .1”LD2, LD3, LD4, LD5 max length .25” (maximum stub length to COM.0 connector)LE2, LE3, LE4, LE5 max length 4.5” match within .1”(LA4 + LB4), (LA2 + LB2) match within .5” (match CLK & MOSI within .5” Module)(LA4 + LD4), (LA2 + LD2) match within .4” (match CLK & MOSI within .5” Carrier Board)(LA4 + LB4), (LA1 + LB1) match within .5” (match CLK & CS within .5” Module)(LA4 + LD4), (LA1 + LA5) match within .4” (match CLK & CS within .5” Carrier Board)R1 = 33Ω

Description Module Baseboard

Clock from Module to Carrier SPI

Data out from Module to Carrier SPI

Data in to Module from Carrier SPI

Effect of the BIOS disable signals

Chip select for Carrier Board SPI - may be sourced from chipset SPI0 or SPI1

Power supply for Carrier Board SPI – sourced from Module – nominally 3.3V. The Module shall provide a minimum of 100mA on SPI_POWER.Carriers shall use less than 100mA of SPI_POWER. SPI_POWER

only be used to power SPI devices on the Carrier

SPI. The SPI bus is used to support a SPI-compatible flash devices. The SPI flash device can be up to 16 MB (128 Mb). The SPI bus is clocked at either support one of these frequencies. SPI support is introduced in COM.0 R2.0 for all

The Module shall provide the termination for the signals below. The following signals should be pulled-up to 3.3V with a 10kΩ resistor

have a series resistor of 33Ω.

On COM.0 R1.0, there is a single pin dedicated to the BIOS Disable function. The pin is A34, named BIOS_DISABLE#. If the Carrier Board leaves BIOS_DISABLE# floating, then the Module boots from the BIOS on the Module. That Module BIOS can be on any bus the Module designer chooses (LPC. SPI, etc.). If the Carrier Board pulls BIOS_DISABLE# to GND, then the on-Module BIOS is disabled and the Module boots from a Carrier Board

In COM.0 R2.0, the Carrier based BIOS options have been expanded to support SPI devices. A second BIOS DISABLE pin (BIOS_DIS1#) has been added to allow for multiple Carrier implementations for external BIOS devices. The BIOS_DISABLE# pin has been renamed to BIOS_DIS0#. Additional pins have been added to bring the SPI signals to the Carrier. These pins are defined in Table 4.12 above.

The Table 4.13 below allows for Carrier Board LPC FWH operation that is backward compatible with COM.0 Rev.1 Carriers. It also allows two Carrier SPI options: SPI0 on Carrier and SPI1 on the Module, or SPI0 on the Module and SP1 on the Carrier.

SPI Descriptor Bios Entry Ref Line

Module SPI0/SPI1 0

Module Carrier FWH 1

Carrier SPI0/SPI1 2

Module SPI0/SPI1 3

SPI Power

Module Vs Carrier Board Pull-ups

5.7 SPI Devices

Figure 5-10: Typical SPI topology

be in SPI0 or SPI1 as determined by the descriptor table in the SPI0 device. The Module may have one or two SPI devices, or have zero or one LPC FWH.

With special circuitry on the Module it's possible to have a single SPI device, but allow the Module GBE, ME and Platform data to stay with the Module even in the case of a Carrier Board SPI BIOS entry per Ref Line 2 above. The Module SPI would include a descriptor table, BIOS code, GBE parameters, ME parameters, and platform data. For table line entries 0 and 1 above, the Module SPI device would be selected by SPI CS0# from the chipset. For table line entry 2 above, the Module SPI device would be selected by chipset SPI CS1# instead of CS0#. This would be achieved by low cost circuitry on the Module. The Module SPI device descriptor table and the Module BIOS code would be used in table line entries 0, 1 and 3.

An alternative arrangement would be to have two SPI devices on the Module. The descriptor table and the actual BIOS are in SPI0, and that the GBE LAN data, ME data and platform data reside in SPI1. Then a Carrier Board SPI option is allowed (table line ref 2) in which the actual BIOS is on the

be write-enabled. The Carrier SPI0 device could be write protected if desired (as is the case in some regulated industries such as casino gaming).

Note that in the case of the BIOS boot from Carrier FWH (table line ref 1), the module SPI devices are still enabled and active. They are used by the GBE

They can keep the BIOS code as well, but it is not used. The ICH pin straps cause an LPC FWH BIOS boot.

Introducing a SPI_POWER pin is desirable because some Module implementations will have the SPI power domain in power state S0 and others in S5. It is easier for Carrier board designers to take the Carrier SPI power from a pin on the Module.

not be any Carrier Board pull-ups or pull-downs on the seven SPI related signals. All such terminations shall be on the Module. The Module

implement a SPI bus. The SPI bus is replacing the LPC bus for BIOS EEPROM devices. If a Module supports an external BIOS is support an external LPC BIOS. The diagram below depicts a typical SPI topology. Note that other SPI

configurations are possible including Module or Carrier based CS1# SPI device. See Section 4.3.12 'SPI Interface' for other implementation options.

(LA1 + LB1), (LA2 + LB2), (LA3 + LC3 + LB3), (LA4 + LB4) max length 2” match all within .1”

6/20/20 6/20/20 1500 < L < 7000 3461.94

6/12/12 6/12/12 1500 < L < 7000 5001.4

6/12/12 6/12/12 1500 < L < 7000 5291.64

6/12/12 6/12/12 1500 < L < 7000 3573.18

10/20/20 10/20/20 ASAP


LynxPoint-MChecklist Length[mils]

SOM-5894 A101-4Module Length[mils]



LynxPoint-M to SPI Device

1500 < L < 7000 L < 500

3461.94

5001.4 1539.465291.64 1829.73573.18



Intra-pair to SPI_CLK Length Matching[mils]

Pin No. GPSI Pin Type

A98 5V / 12V

A101 5V / 12V

A99 5V / 12V

A102 5V / 12V


SER0_TX O CMOS

SER1_TX O CMOS

SER0_RX I CMOS

SER1_RX I CMOS

These signals use reclaimed VCC_12V pins. See section 5.10 'Protecting COM.0 Pins Reclaimed From the VCC_12V Pool' for additional design considerationsAny of the Module asynchronous serial ports, if implemented on an Intel X86 architecture Module platform,mapped serial ports that are register compatible with the National Semiconductor 16550 UARTs that were used in the


General purpose serial port transmitter

General purpose serial port transmitter

General purpose serial port receiver

General purpose serial port receiver

These signals use reclaimed VCC_12V pins. See section 5.10 'Protecting COM.0 Pins Reclaimed From the VCC_12V

Any of the Module asynchronous serial ports, if implemented on an Intel X86 architecture Module platform, shall be I/O mapped serial ports that are register compatible with the National Semiconductor 16550 UARTs that were used in the

IT8518E Length[mils]

6/8/8 6/8/8 ASAP

6/8/8 6/8/8 ASAP

6/8/8 6/8/8 ASAP

6/8/8 6/8/8 ASAP


SOM-5894 A101-4Module Length[mils]




Length[mils]

Pin No. Miscellaneous Pin Type Description

B33

B34

B32

A34

B88 3.3V / 3.3V

A86

A87

B27

B101 3.3V / 12V

B102 3.3V / 12V


PICMG DG 1.0Module

Length[mils]

I2C_CK O CMOS

3.3V / 3.3V General purpose I2C port clock output

I2C_DAT I/O OD CMOS

3.3V / 3.3V General purpose I2C port data I/O line

SPKR O CMOS

3.3V / 3.3V

Output for audio enunciator - the "speaker" in PC-AT systems

BIOS_DISABLE# BIOS_DIS0# I CMOS

3.3V / 3.3V

Module BIOS disable input. Pull low to disable module BIOS. Used to allow off-module BIOS implementations.

BIOS_DIS1# I CMOS

Selection straps to determine the BIOS boot device

KBD_RST# I CMOS

3.3V / 3.3V

Input to module from (optional) external keyboard controller that can force a reset. Pulled high on the module. This is a legacy artifact of the PC-AT.

KBD_A20GATE I CMOS

3.3V / 3.3V

Input to module from (optional) external keyboard controller that can be used to control the CPU A20 gate line. The A20GATE restricts the memory access to the bottom megabyte and is a legacy artifact of the PC-AT. Pulled low on the module.

WDT O CMOS

3.3V / 3.3V

Output indicating that a watchdog time-out event has occurred.

FAN_PWMOUT* O OD CMOS

Fan speed control. Uses the Pulse Width Modulation (PWM) technique to control the fan’s RPM.

FAN_TACHIN* I OD CMOS

Fan tachometer input for a fan with a two pulse output.

A96 3.3V / 12V

SUSCLK

TPM_PP* I CMOS

Trusted Platform Module (TPM) Physical Presence pin. Active high. TPM chip has an internal pull down. This signal is used to indicate Physical Presence to the TPM.

O CMOS

3.3V / 3.3V Suspend

This clock is an output of the RTC generator circuit to use by other chips for refresh clock.

Watchdog Timer

Output Options and Characteristics

Watchdog Enable and Strobe

COM ExpressTM modules may implement a watchdog timer output to the Carrier Board. If the watchdog timer (WDT) is implemented, it should have the characteristics described below.

The watchdog should implement the following output options:

• Reset: the module shall reset. Module pins PCI_RST# , IDE_RST# and CB_RESET# shall be pulsed low. The module WDT pin goes high until the unit resets. • NMI (non-maskable interrupt) is generated. The module WDT pin goes high and stays high until cleared by software. • Output to module WDT pin only. The WDT pin stays high until cleared by software. • Disabled: the module WDT pin is driven low.

The above output options may be realized by software configurable hardware or by module build options. The watchdog output shall come up as a logic low and shall be disabled upon power-on-reset (VCC_12V power cycle) or external system reset (when SYS_RST# pin is toggled low by external hardware). The watchdog may be enabled by BIOS or system software. If the watchdog is enabled and times out, the module WDT pin shall be driven to a logic high level and shall remain high for at least one microsecond.

Typically, the watchdog parameters (output options, enabling, enable delay, timeout delay) are managed by the module BIOS, often via a BIOS setup screen. The regular watchdog strobes to prevent a watchdog timeout are typically handled by the module’s application software. There may be BIOS abstractions to isolate the application software from the watchdog hardware.

The software programmable Watchdog Enable Delay is the time between when the watchdog is enabled by firmware and when the first watchdog strobe is needed to prevent a watchdog time out. The enable delay allows time for the operating system to boot and the application to load and initialize.

After the initial Enable Delay, the enabled watchdog must be periodically strobed by software to prevent a watchdog timeout. The Strobe Interval shall be software programmable.

Recommended ranges in enable delay and max strobe periods are given in the following table.

Min Value Max Value


Enable Delay 1 second 10 minutes Strobe Interval 0.1 second 10 minutes

6/8/8 6/8/8 N/A ASAP

6/8/8 6/8/8 N/A ASAP

6/8/8 6/8/8 ASAP N/A

6/8/8 6/8/8 ASAP N/A

6/8/8 6/8/8 ASAP

6/8/8 6/8/8 ASAP N/A

6/8/8 6/8/8 ASAP N/A

6/8/8 6/8/8 N/A ASAP

6/8/8 6/8/8 N/A ASAP

6/8/8 6/8/8 N/A ASAP







Length[mils]


Length[mils]



6/8/8 6/8/8 ASAP N/A

SOM-5894 A101-4Total Length[mils]

Pin No. Description

C54

D57

A97 PDS

ASAP - As short as possible

Module Type Definition Pin Type Pwr Rail /

Tolerance

TYPE0#

PDS

The TYPE pins indicate to the Carrier Board the Pin-out Type that is implemented on the module. The pins are tied on the module to either ground (GND) or are no-connects (NC). For Pin-out Type 1 and Type 10, these pins are don’t care (X). TYPE2# TYPE1# TYPE0# X X X Pin-out Type 1 NC NC NC Pin-out Type 2 NC NC GND Pin-out Type 3 (no IDE) NC GND NC Pin-out Type 4 (no PCI) NC GND GND Pin-out Type 5 (no IDE, no PCI) GND NC NC Pin-out Type 6 (no IDE, no PCI)

The Carrier Board should implement combinatorial logic that monitors the module TYPE pins and keeps power off (e.g deactivates the ATX_ON signal for an ATX power supply) if an incompatible Module pin-out type is detected. The Carrier Board logic may also implement a fault indicator such as an LED.

C57 TYPE1#

TYPE2#

TYPE10#

Dual use pin. Indicates to the Carrier Board that a Type 10 Module is installed. Indicates to the Carrier that a Rev 1.0/2.0 Module is installed

TYPE10#NC Pin-out R2.0PD Pin-out Type 10 pull down to ground with 4.7K resistor12V Pin-out R1.0

This pin is reclaimed from the VCC_12V pool. In R1.0 Modules this pin will connect to other VCC_12V pins. In R2.0 this pin is defined as a no connect for types 1-6. A Carrier can detect a R1.0 Module by the presence of 12V on this pin. R2.0 Module types 1-6 will no connect this pin. Type 10 Modules shall pull this pin to ground through a 4.7K resistor.

DP - Differential PairSE - Single End

N/A N/A

N/A N/A

ASAP

N/A N/A

ASAP - As short as possible

PICMG DG 1.0Module

Length[mils]


Length[mils]


Length[mils]


Length[mils]

DP - Differential PairSE - Single End

Pin No. General Purpose I/O Pin Type Description

A93

B54B57B63

A54

A63A67A85



PICMG DG 1.0Module

Length[mils]


Length[mils]

GPO0

O CMOS 3.3V / 3.3V

General purpose output pins. Upon a hardware reset, these outputs should be low.From COM-Express Extension Spec V0.7, this pin is also recommended to be used as LID function and announce PME to system.

GPO1General purpose output pins. Upon a hardware reset, these outputs should be low. GPO2

GPO3

GPI0

I CMOS 3.3V / 3.3V

General purpose input pins. Pulled high internally on the module.From COM-Express Extension Spec V0.7, this pin is also recommended to be used as external fan control.

GPI1General purpose input pins. Pulled high internally on the module. GPI2

GPI3

6/8/8 6/8/8 ASAP

6/8/8 6/8/8 ASAP6/8/8 6/8/8 ASAP6/8/8 6/8/8 ASAP

6/8/8 6/8/8 ASAP

6/8/8 6/8/8 ASAP6/8/8 6/8/8 ASAP6/8/8 6/8/8 ASAP




Length[mils]


Length[mils]



Pin No. SDIO Pin Type

B63 SDIO_CD#

A93 SDIO_CLK

B54 SDIO_CMD

B57 SDIO_WP A54 SDIO_DAT0 A63 SDIO_DAT1A67 SDIO_DAT2A85 SDIO_DAT3

SD card interface signals

GPI0 SD_DATA0 Bidirectional signal GPI1 SD_DATA1 Bidirectional signal GPI2 SD_DATA2 Bidirectional signal GPI3 SD_DATA3 Bidirectional signal GPO0 SD_CLK Output from COM Ex, input to SD GPO1 SD_CMD Output from COM Ex, input to SD GPO2 SD_WP Output from COM Ex, input to SD GPO3 SD_CD# Output from SD, input to COM Ex



I CMOS

3.3V / 3.3V

O CMOS

3.3V / 3.3V

O CMOS

3.3V / 3.3V

O CMOS

3.3V / 3.3V

IO CMOS

3.3V / 3.3V

outputs connect to GPO. With this mapping, any combination of Module and Carrier Board SDIO interface support will not result in damage. An EEPROM bit is added so that the Carrier Board can define if the GPIO are used as GPIO or SDIO. The

COM Express Signal SD card interface signals Comments



SD card interface signals

Bidirectional signal Bidirectional signal Bidirectional signal Bidirectional signal

Output from COM Ex, input to SD Output from COM Ex, input to SD Output from COM Ex, input to SD Output from SD, input to COM Ex


SDIO Card Detect. This signal indicates when a SDIO/MMC card is present. Maps to GPO3. SDIO Clock. With each cycle of this signal a one-bit transfer on the command and each data line occurs. This signal has maximum frequency of 48 MHz. Maps to GPO0.

SDIO Command/Response. This signal is used for card initialization and for command transfers. During initialization mode this signal is open drain. During command transfer this signal is in push-pull mode. Maps to GPO1 SDIO Write Protect. This signal denotes the state of the write-protect tab on SD cards. Maps to GPO2. SDIO Data lines. These signals operate in push-pull mode. Maps to GPI[0:3]

outputs connect to GPO. With this mapping, any combination of Module and Carrier Board SDIO interface support will not result in damage. An EEPROM bit is added so that the Carrier Board can define if the GPIO are used as GPIO or SDIO. The

Comments

VSB in S3,S4,S5


B12

B49

B50

B24

B18

A15

A24

B66 PCI Express wake up signal.

B67

A27 Indicates that external battery is low.

Power and System Management


PICMG DG 1.0Module

Length[mils]

PWRBTN# I CMOS

3.3V / 3.3V Suspend

Power button to bring system out of S5 (soft off), active on rising edge.

SYS_RESET# I CMOS

3.3V / 3.3V Suspend

Reset button input. Active low input. System is held in hardware reset while this input is low, and comes out of reset upon release.

CB_RESET# O CMOS

3.3V / 3.3V Suspend

Reset output from module to Carrier Board. Active low. Issued by module chipset and may result from a low SYS_RESET# input, a low PWR_OK input, a VCC_12V power input that falls below the minimum specification, a watchdog timeout, or may be initiated by the module software.Carrier Board LPC devices should be reset with signal CB_RESET#.

PWR_OK I CMOS

3.3V / 3.3V

Power OK from main power supply. A high value indicates that the power is good.

SUS_STAT# O CMOS

3.3V / 3.3V Suspend

Indicates imminent suspend operation; used to notify LPC devices.

SUS_S3# O CMOS

3.3V / 3.3V Suspend

Indicates system is in Suspend to RAM state. Active low output.

A18 SUS_S4# O CMOS

3.3V / 3.3V Suspend

Indicates system is in Suspend to Disk state. Active low output.

SUS_S5# O CMOS

3.3V / 3.3V Suspend

Indicates system is in Soft Off state. Also known as "PS_ON" and can be used to control an ATX power supply.

WAKE0# I CMOS

3.3V / 3.3V Suspend

WAKE1# I CMOS

3.3V / 3.3V Suspend

General purpose wake up signal. May be used to implement wake-up on PS2 keyboard or mouse activity.

BATLOW# I CMOS

3.3V / 3.3V Suspend

B35

A35

B13

B14

B15

B88

A103

B103


THRM# I CMOS

3.3V / 3.3V

Input from off-module temp sensor indicating an over-temp situation.

THERMTRIP# O CMOS

3.3V / 3.3V

Active low output indicating that the CPU has entered thermal shutdown.

SMB_CLK I/O OD CMOS

3.3V / 3.3V Suspend

System Management Bus bidirectional clock line. Power sourced through 5V standby rail and main power rails.

SMB_DAT I/O OD CMOS

3.3V / 3.3V Suspend

System Management Bus bidirectional data line. Power sourced through 5V standby rail and main power rails.

SMB_ALERT# I CMOS

3.3V / 3.3V Suspend

System Management Bus Alert – active low input can be used to generate an SMI# (System Management Interrupt) or to wake the system. Power sourced through 5V standby rail and main power rails

RI# ICMOS

3.3V / 3.3V Suspend

This may be driven low by external circuitry to signal an external power-management event.

LID#* I OD CMOS

3.3V Suspend / 12V

LID button. Low active signal used by the ACPI operating system for a LID switch.

SLEEP#* I OD CMOS

3.3V Suspend / 12V

Sleep button. Low active signal used by the ACPI operating system to bring the system to sleep state or to wake it up again.

6/8/8 6/8/8 N/A ASAP

6/8/8 6/8/8 ASAP N/A

6/8/8 6/8/8 ASAP N/A

6/8/8 6/8/8 N/A ASAP

6/8/8 6/8/8 ASAP N/A

6/8/8 6/8/8 N/A ASAP

6/8/8 6/8/8 N/A ASAP

6/8/8 6/8/8 N/A ASAP

6/8/8 6/8/8 ASAP N/A

6/8/8 6/8/8 N/A ASAP

6/8/8 6/8/8 N/A ASAP







Length[mils]


Length[mils]



6/8/8 6/8/8 N/A ASAP

6/8/8 6/8/8 N/A ASAP

6/8/8 6/8/8 ASAP N/A

6/8/8 6/8/8 ASAP N/A

6/8/8 6/8/8 ASAP N/A

N/A N/A N/A N/A N/A

6/8/8 6/8/8 N/A ASAP

6/8/8 6/8/8 N/A ASAP


Pin No. Power and GND Pin Type Description

A47


Trace Width / Copper Area Calculator

RequirementI - current (amps) 11.895

10Copper thicknesst - trace oz 1


A97~A99,A101~A109B101~B109C104~C109D104~D109

VCC_12V Power

Primary power input: +12V nominal. See Electrical Specifications section for allowable input range. All available VCC_12V pins on the connector(s) shall be used.

B84~B87 VCC_5V_SBY Power

Standby power input: +5.0V nominal. See Electrical Specifications section for allowable input range. If VCC5_SBY is used, all available VCC_5V_SBY pins on the connector(s) shall be used. Only used for standby and suspend functions. May be left unconnected if these functions are not used in the system design.

VCC_RTC Power Real-time clock circuit-power input. Nominally +3.0V. See Electrical Specifications section for details.

A110B1,B11,B21,B31,B41,B51,B60,B70,B80,B90,B100,B110C1,C11,C21,C31,C41,C51,C60,C70,C76,C80,C84,C87,C90,C93,C96,C100,C103,C110D1,D11,D21,D31,D41,D51,D60,

GND Power

Ground - DC power and signal and AC signal return path. All available GND connector pins shall be used and tied to Carrier Board GND plane.

Based on http://frontdoor.biz/PCBportal/HowTo2152.xls with IPC2152 Standard.

Assume Imax * 1.5Tr - temp rise (oC)

http://frontdoor.biz/PCBportal/HowTo2152.xls

Nearest planetplane - plane oz 1s - distance (mils) 48.4

< 20"Board tpcb - thickness (mils) 63m - material FR4Safety marginD - percent derate (%) 20Result

W - Trace Width (mils) 663

713

1391.69113624780.8340.5551.0001.0001.0201.0841.200

A - plane area (inch2)

IF(t=3,(CV*tADJ*sADJ*tplaneADJ*AADJ*mADJ*tpcbADJ*DADJ)*(0.000258)*1000, IF(t=2,(CV*tADJ*sADJ*tplaneADJ*AADJ*mADJ*tpcbADJ*DADJ)*(0.000388)*1000, IF(t=1,(CV*tADJ*sADJ*tplaneADJ*AADJ*mADJ*tpcbADJ*DADJ)*(0.000775)*1000,(CV*tADJ*sADJ*tplaneADJ*AADJ*mADJ*tpcbADJ*DADJ)*(0.00155)*1000)))

CVADJ - Copper Area (mils2) CV*tADJ*sADJ*tplaneADJ*AADJ*mADJ*tpcbADJ

1. CV - Chart Value (mils2)

IF(Tr=2,63.637*I^(1.9386),IF(Tr=5,27.987*I^(1.8658),IF(Tr=10,15.663*I^(1.8121),IF(Tr=20,8.868*I^(1.7655),IF(Tr=30,6.5379*I^(1.7433),IF(Tr=45,4.8512*I^(1.7175),IF(Tr=60,3.9366*I^(1.6997),IF(Tr=75,3.3749*I^(1.686)))))))))

2. tADJ - trace adjust IF(t=2,-0.0185*LN(I)+0.9861, IF(t=3,1,-0.0318*LN(I)+0.9128))3. sADJ - distance adjust IF(s=0,1, IF(s>125,1,0.0031*s+0.4054))4. tplaneADJ - plane adjust IF(tplane>1,0.96,1)5. AADJ - area adjust IF(A="> 40""",0.94,IF(A="> 20""",0.96,1))6. mADJ - material adj IF(m="FR4",1.02, IF(m="Poly",1,1))7. tpcbADJ - thick adjust 25.959*tpcb^(-0.7666)8. DADJ - derate adjust (D+100)/100

B25

enter "0" if no plane is adjacent to trace

B36

IPC-2152 data is only verified for traces with cross-sectional area between 5-700 square mils

ASAP7.54 A

ASAP610 660

ASAP

0.39 A

ASAP10

ASAP6 μ A

ASAP10

ASAP

7.93 A

ASAP670 720


PICMG DG 1.0Module

Length[mils]


Length[mils]

SOM-5894 BaseboardPower Consumption [A]Trace Width min [mils] Copper Area min [mils2]


Length[mils]


Length[mils]

Trace Width (mils)

Copper Area (mils2)

Module OverviewModule Configuration

Feature Overview — SizeCompact Module

Basic Module

Extended Module

Feature Overview - Pin-out TypesPin-out Type 1

Two Three module sizes are defined: the Compact Module, Basic Module and the Extended Module. The primary difference between the Basic Module and the Extended different size Module is the over-all physical size and the performance envelope supported by each. The Extended Module is larger and can support larger processor and memory solutions. The Compact Module, Basic Module and Extended Module use the same connectors and pin-outs and utilize several common mounting hole positions. This level of compatibility allows that a carrier board can be designed to accommodate an Extended Module can also support a Basic Module Multiple Module sizes.Up to 440 pins of connectivity are available between COM ExpressTM modules and the Carrier Board. Legacy buses such as PCI, parallel ATA, LPC, AC'97 can be supported as well as new high speed serial interconnects such as PCI Express, Serial ATA or SAS, USB 2.0/ 3.0 and Gigabit Ethernet. To enhance interoperability between COM ExpressTM modules and Carrier Boards, five seven common signaling configurations (Pin-out Types) have been defined to ease system integration. Some Pin-out Types definitions require only a single 220-pin connector and others require both 220-pin connectors to supply all the defined signaling. All Pin-out Type definitions apply to either Compact Module, Basic Module or Extended Module sizes.

The Compact Module is intended for mobile systems and space-constrained stationary systems. Key features of the Compact Module include:• Module size: 95mm x 95mm• 5mm and 8mm stack height options (Module bottom to Carrier Board top)• 18mm ‘z’ height with heat-spreader (using the 5mm stack option)• Accommodates a single (or two stacked) horizontal mount SO-DIMM• Single 220 pin or dual 220 pin connectors for up to 440 pins

The Basic Module is intended for mobile systems and space-constrained stationary systems. Key features of the Basic Module include:

• Module size: 125 mm x 95 mm • 5mm and 8 mm stack height options (Module bottom to Carrier Board top) • 18 mm ‘z’ height with heat-spreader (with 5 mm stack option) • Accommodates a single (or two stacked) horizontal mount SO-DIMM • Single 220 pin or dual 220 pin connectors for up to 440 pins

The Extended Module, which targets OEM applications that require larger amounts of system memory, features a larger module size to accommodate full size DIMMs and larger chipsets and CPUs packages.

The key features of the Extended Module include:

• Module size: 155 mm x 110 mm • 5mm and 8 mm stack height options (Module bottom to Carrier Board top) • 18 mm ‘z’ height with heat-spreader (using 5 mm stack option) • Accommodates 2 full-size DIMM or mini DIMM memories or 2 right-angle mount or vertical mount SO-DIMMs• Single 220 pin or dual 220 pin connectors for up to 440 pins • Allows for the use of higher performance CPUs that can not be supported on the Compact Module or Basic Module

Pin-out Type 10

Pin-out Type 2

Pin-out Type 3

Pin-out Type 4

• Single 220 pin connector (A-B connector) • Up to 8 USB 2.0 ports; 4 shared over-current lines • Up to 4 Serial ATA or SAS ports • Up to 6 PCI Express Gen1/Gen2 signaling lanes • Support pins for up to 2 ExpressCards • Dual 24-bit LVDS channels • Analog VGA • TV Out: Composite Video, S-Video, Component Video (YPbPr) • AC '97 / HDA digital audio interface (external CODEC(s) required) • Single Ethernet interface with integrated PHY – pinned for Gigabit Ethernet • LPC interface • SPI (SPI support starts with COM.0 R2.0)• 8 GPIO pins • 120W 68W maximum input power over module connector pins • +12V primary power supply input • +5V standby and 3.3V RTC power supply inputs

The type 10 Pin-out was introduced with COM Express Rev. 2.0. (Pin-out Type 10 is not compatible to Type 1-6)• Single 220 pin connector (A-B connector)• Up to 8 USB 2.0 ports; 4 shared over-current lines• Up to 2 Serial ATA or SAS ports• Up to 4 PCI Express Gen1/Gen2 signaling lanes• Support pins for up to 2 ExpressCards• Single 24-bit LVDS channel• One Digital Display Interface configurable asSDVO, DP, or TMDS• AC '97 / HDA digital audio interface (external CODEC(s) required)• Single Ethernet interface with integrated PHY – pinned for Gigabit Ethernet• LPC interface• Two TX/RX serial pairsts• SPI• Fan control• TPM support• 8 GPIO pins• 68W maximum input power over Module connector pins• +12V primary power supply input• +5V standby and 3.3V RTC power supply inputs

All Pin-out Type 1 features plus the following: • Dual 220 pin connectors (A-B and C-D, 440 pins total) • 32 bit PCI interface • IDE port (to support legacy ATA devices such as CD-ROM drives and Compact Flash storage cards) • Up to 22 PCI Express lanes (up to 6 on A-B and up to 16 on C-D) • 16 of 22 PCI Express lanes commonly used for PCI Express Graphics • SDVO option (pins shared with PCI Express Graphics) • Maximum module input power capability extended to 188W 137W

All Pin-out Type 2 features with the exception of the following: • IDE pins are reallocated to provide additional Gigabit Ethernet capability: no IDE • Up to 3 Gigabit Ethernet channels • Option to implement 10 Gigabit Ethernet channel instead of additional 2 Gigabit Ethernet ports

Pin-out Type 5

Pin-out Type 6

All Pin-out Type 2 features with the exception of the following: • PCI pins are reallocated to provide additional PCI Express lanes: no PCI • Up to 32 PCI Express lanes

All Pin-out Type 2 features with the exception of the following: • Both IDE and PCI pins are reallocated: no IDE and no PCI • Up to 32 PCI Express lanes • Up to 3 Gigabit Ethernet channels • Option to implement 10 Gigabit Ethernet channel instead of two additional Gigabit Ethernet ports

All Pin-out Type 2 features with the exception of the following:• Both IDE and PCI pins are reallocated: no IDE and no PCI• Up to 24 PCI Express lanes (16 on the PEG port)• Reserved 16 pins to support the two extra differential pairs required for SuperSpeed 3.0. The 16 pins will allow SuperSpeed USB 3.0 support on up to four of the eight USB 2.0 ports. At this point in time, there is not enough information and silicon available for this subcommittee to determine the appropriate trace length and routing rules for SuperSpeed USB 3.0. The routing rules will be handled in a future version of this document• Up to 3 Digital Display Interfaces

Signal DescriptionsSignal Naming ConventionREQ#TX+, TX-A[0:31]CBE[0:3]#Pin and Signal Buffer TypesPin and Buffer type definitions apply to the signals in the Signal List section below.Pin TypesI O I/O OD Buffer TypesCMOS

PCIE

PCI SATA LVDS USB REF PDS Analog Power Power Rails and Tolerances

Signal List

Signals Requiring Carrier Board Termination

Signals Requiring Module TerminationThe signals below might require Module termination. They are mentioned to provide guidance to both the Module and Carrier designer.AC coupled on the Module

Pins are marked in the following table 'Signal List' with the power rail associated with the pin, and, for input and I/O pins, with the input voltage tolerance. The pin power rail and the pin input voltage tolerance may be different. For example, the PCI group is defined as having a 3.3V power rail, meaning that the output signals will only be driven to 3.3V, but the pins are tolerant of 5V signals.

An additional label, “Suspend” indicates that the pin is active during suspend states (S3,S4,S5). If suspend modes are used, then care must be taken to avoid loading signals that are active during suspend to avoid excessive suspend mode current draw.

COM ExpressTM signal descriptions are described in the following table. The Pin Availability column in the table indicates in which Pin-out Types the signal is available. Module Pin-out Types 1 through 5 6 and 10 are designated T1,T2,T3,T4,T5,T6,T10 in the Pin Availability column. A notation of “All” indicates that the signal is available to all module Pin-out Types.

Some signals, detailed below, require Carrier Board termination for proper operation. If the signals and the feature are not used, no Carrier Board termination is required, and the pins may be left open.

Misc

The following signals shall be AC coupled on the Module.• SDVO[B:C]_RED+/-• SDVO[B:C]_GRN+/-• SDVO[B:C]_BLU+/-• SDVO[B:C]_CK+/-• SATA[0:3]TX+/-• SATA[0:3]RX+/-• PCIE_TX[0:31]+/-• PEG_TX[0:15]+/-

The Module shall provide the termination for the signals below. The following signals should be pulled-up to 3.3V with a 2.2kΩ resistor• LVDS_I2C_CK• LVDS_I2C_DAT• I2C_CK• I2C_DAT• VGA_I2C_CK• VGA_I2C_DAT

The Module shall provide the termination for the signals below. The following signals should be pulled-up to 3.3V with a 4.7kΩ resistor• IDE_IORDY

The Module shall provide the termination for the signals below. The following signals should be pulled-up to 3.3V with a 8.2kΩ resistor• PCI_IRQ[A:D]#• PCI_IRDY#• PCI_LOCK#• PCI_PERR#• PCI_REQ[0:3]#• PCI_SERR#• PCI_STOP#• PCI_TRDY#• PCI_FRAME#• PCI_CLKRUN#• LPC_SERIRQ

The Module shall provide the termination for the signals below. The following signals should be pulled-up to 3.3V with a 10kΩ resistor• KBD_A20GATE• KBD_RST#• BIOS_DISABLE#• EXCD[0:1]_CPPE#• PP_TPM• FAN_TACHIN

The Module shall provide the termination for the signals below. The following signal should be pulled-up to 3.3V Standby with a 1.2kΩ resistor• WAKE0#The Module shall provide the termination for the signals below. The following signals should be pulled-up to 3.3V Standby with a 2.2kΩ resistor• SMB_CK

The Module shall provide the termination for the signals below. The following signalsn should be pulled-up to 3.3V Standby with a 10kΩ resistor• USB_[0,2,4,6]_[1,3,5,7]_OC#• SYS_RESET#• BATLOW#• PWRBTN• WAKE1#• PCI_PME#• PWRBTN#• SLEEP#• LID#

Module termination of IDE_IRQ is dependent on the controller used. The ModuleWhen supporting Carrier Board based SPI devices, the SPI_MISO line

Pin-out Tables

Modules implementing a TPM shall pull down TPM_PP. The value of the pull down resistor will be module specific. Carries that support TPM should tie this signal to 3.3V when TPM features that require physical presence should be activated.

Pin-out information for Module pin-out Types 1–

Signal DescriptionsSignal Naming Convention

Active-low signals are indicated by a trailing ‘#’ sign: Differential pairs are indicated by trailing ‘+’ and ‘-‘ signs: Bused signals are indicated by brackets, with LS bit first, MS bit last:

Pin and Signal Buffer TypesPin and Buffer type definitions apply to the signals in the Signal List section below.Pin Types

Input to the module Output from the module Bi-directional input / output signal Open drain output

Buffer Types

PCI 2.3 compatible signal. Please refer to the PCI Rev. 2.3 Specification for details.

Low Voltage Differential Signal – 330mV nominal; 450mV maximum differential signal.USB 2.0 compatible differential signal. Please refer to the USB 2.0 Specification for details.

Pull-down strap. A module output pin that is either tied to GND or is not connected. Used to signal module capabilities to the Carrier Board.

Inputs used for power delivery to the module electronics.Power Rails and Tolerances

Signal List

Signals Requiring Carrier Board Termination

Signals Requiring Module TerminationThe signals below might require Module termination. They are mentioned to provide guidance to both the Module and Carrier designer.AC coupled on the Module

Bus brackets may appear anywhere in the signal name:

Logic input or output. Input thresholds and output levels shall be 80% of supply rail for high side and 20% of the relevant supply rail for low side.

PCI Express compatible differential signal. Please refer to the PCI Express Specification for details. PCIE transmit pins (module outputs) shall be AC coupled on the module. PCIE receive pins (module inputs) shall be DC coupled on the COM ExpressTM module and shall be assumed to be AC coupled off-module, close to the signal source. If the target PCI Express device resides on the Carrier Board, the module PCIE receive lanes (target PCIE device transmit lanes) shall be AC coupled near the device on the Carrier Board. If the Carrier Board implements a PCIE slot, then these signals shall be AC coupled on the add-in card, not on the Carrier Board.

SATA compatible differential signal. Please refer to the SATA Specification for details. All COM ExpressTM SATA signals shall be AC coupled on the module.

Reference voltage output. May be sourced from a module power plane.

Inputs and Outputs used for LAN, VGA and TV OUT are analog signals.

Pins are marked in the following table 'Signal List' with the power rail associated with the pin, and, for input and I/O pins, with the input voltage tolerance. The pin power rail and the pin input voltage tolerance may be different. For example, the PCI group is defined as having a 3.3V power rail, meaning that the output signals will only be driven to 3.3V, but the pins are tolerant of 5V signals.

An additional label, “Suspend” indicates that the pin is active during suspend states (S3,S4,S5). If suspend modes are used, then care must be taken to avoid loading signals that are active during suspend to avoid excessive suspend mode current draw.

COM ExpressTM signal descriptions are described in the following table. The Pin Availability column in the table indicates in which Pin-out Types the signal is available. Module Pin-out Types 1 through are designated T1,T2,T3,T4,T5,T6,T10 in the Pin Availability column. A notation of “All” indicates that the signal is available to all module Pin-out Types.

Some signals, detailed below, require Carrier Board termination for proper operation. If the signals and the feature are not used, no Carrier Board termination is required, and the pins may be left open.

Misc

The following signals shall be AC coupled on the Module.SDVO[B:C]_RED+/-SDVO[B:C]_GRN+/-SDVO[B:C]_BLU+/-SDVO[B:C]_CK+/-SATA[0:3]TX+/-SATA[0:3]RX+/-PCIE_TX[0:31]+/-PEG_TX[0:15]+/-

shall provide the termination for the signals below. The following signals should be pulled-up to 3.3V with a 2.2kΩ resistorLVDS_I2C_CKLVDS_I2C_DAT

VGA_I2C_CKVGA_I2C_DAT

shall provide the termination for the signals below. The following signals should be pulled-up to 3.3V with a 4.7kΩ resistorIDE_IORDY

shall provide the termination for the signals below. The following signals should be pulled-up to 3.3V with a 8.2kΩ resistorPCI_IRQ[A:D]#

PCI_LOCK#PCI_PERR#PCI_REQ[0:3]#PCI_SERR#PCI_STOP#PCI_TRDY#PCI_FRAME#PCI_CLKRUN#LPC_SERIRQ

shall provide the termination for the signals below. The following signals should be pulled-up to 3.3V with a 10kΩ resistorKBD_A20GATE

BIOS_DISABLE#EXCD[0:1]_CPPE#

FAN_TACHIN

shall provide the termination for the signals below. The following signal should be pulled-up to 3.3V Standby with a 1.2kΩ resistor

shall provide the termination for the signals below. The following signals should be pulled-up to 3.3V Standby with a 2.2kΩ resistor

shall provide the termination for the signals below. The following signalsn should be pulled-up to 3.3V Standby with a 10kΩ resistorUSB_[0,2,4,6]_[1,3,5,7]_OC#SYS_RESET#

Module termination of IDE_IRQ is dependent on the controller used. The Module shall provide the necessary termination.When supporting Carrier Board based SPI devices, the SPI_MISO line shall have a series resistor of 33Ω.

Pin-out Tables

Modules implementing a TPM shall pull down TPM_PP. The value of the pull down resistor will be module specific. Carries that support TPM should tie this signal to 3.3V when TPM features that require physical presence should be activated.

Pin-out information for Module pin-out Types 1–5 6 and 10 are provided in the five seven tables on the following pages.

A1 GND (FIXED) B1 GND (FIXED) A2 GBE0_MDI3- B2 GBE0_ACT# A3 GBE0_MDI3+ B3 LPC_FRAME# A4 GBE0_LINK100# B4 LPC_AD0 A5 GBE0_LINK1000# B5 LPC_AD1 A6 GBE0_MDI2- B6 LPC_AD2 A7 GBE0_MDI2+ B7 LPC_AD3 A8 GBE0_LINK# B8 LPC_DRQ0# A9 GBE0_MDI1- B9 LPC_DRQ1# A10 GBE0_MDI1+ B10 LPC_CLK A11 GND (FIXED) B11 GND (FIXED) A12 GBE0_MDI0- B12 PWRBTN# A13 GBE0_MDI0+ B13 SMB_CK A14 GBE0_CTREF B14 SMB_DAT A15 SUS_S3# B15 SMB_ALERT# A16 SATA0_TX+ B16 SATA1_TX+ A17 SATA0_TX- B17 SATA1_TX- A18 SUS_S4# B18 SUS_STAT# A19 SATA0_RX+ B19 SATA1_RX+ A20 SATA0_RX- B20 SATA1_RX- A21 GND (FIXED) B21 GND (FIXED) A22 SATA2_TX+ B22 SATA3_TX+ A23 SATA2_TX- B23 SATA3_TX- A24 SUS_S5# B24 PWR_OK A25 SATA2_RX+ B25 SATA3_RX+ A26 SATA2_RX- B26 SATA3_RX- A27 BATLOW# B27 WDT A28 ATA_ACT# B28 AC_SDIN2 A29 AC_SYNC B29 AC_SDIN1 A30 AC_RST# B30 AC_SDIN0 A31 GND (FIXED) B31 GND (FIXED) A32 AC_BITCLK B32 SPKR A33 AC_SDOUT B33 I2C_CK A34 BIOS_DISABLE# B34 I2C_DAT A35 THRMTRIP# B35 THRM# A36 USB6- B36 USB7- A37 USB6+ B37 USB7+ A38 USB_6_7_OC# B38 USB_4_5_OC# A39 USB4- B39 USB5- A40 USB4+ B40 USB5+ A41 GND (FIXED) B41 GND (FIXED) A42 USB2- B42 USB3- A43 USB2+ B43 USB3+ A44 USB_2_3_OC# B44 USB_0_1_OC# A45 USB0- B45 USB1- A46 USB0+ B46 USB1+ A47 VCC_RTC B47 EXCD1_PERST# A48 EXCD0_PERST# B48 EXCD1_CPPE# A49 EXCD0_CPPE# B49 SYS_RESET# A50 LPC_SERIRQ B50 CB_RESET# A51 GND (FIXED) B51 GND (FIXED) A52 PCIE_TX5+ B52 PCIE_RX5+ A53 PCIE_TX5- B53 PCIE_RX5-

Row A Row B

A54 GPI0 B54 GPO1 A55 PCIE_TX4+ B55 PCIE_RX4+ A56 PCIE_TX4- B56 PCIE_RX4- A57 GND B57 GPO2 A58 PCIE_TX3+ B58 PCIE_RX3+ A59 PCIE_TX3- B59 PCIE_RX3- A60 GND (FIXED) B60 GND (FIXED) A61 PCIE_TX2+ B61 PCIE_RX2+ A62 PCIE_TX2- B62 PCIE_RX2- A63 GPI1 B63 GPO3

PCIE_TX1+ PCIE_RX1+ PCIE_TX1- PCIE_RX1- GND WAKE0# GPI2 WAKE1# PCIE_TX0+ PCIE_RX0+ PCIE_TX0- PCIE_RX0- GND (FIXED) GND (FIXED) LVDS_A0+ LVDS_B0+ LVDS_A0- LVDS_B0- LVDS_A1+ LVDS_B1+ LVDS_A1- LVDS_B1- LVDS_A2+ LVDS_B2+ LVDS_A2- LVDS_B2- LVDS_VDD_EN LVDS_B3+ LVDS_A3+ LVDS_B3- LVDS_A3- LVDS_BKLT_EN GND (FIXED) GND (FIXED) LVDS_A_CK+ LVDS_B_CK+

A82 LVDS_A_CK- B82 LVDS_B_CK- A83 LVDS_I2C_CK B83 LVDS_BKLT_CTRL A84 LVDS_I2C_DAT B84 VCC_5V_SBY A85 GPI3 B85 VCC_5V_SBY A86 KBD_RST# B86 VCC_5V_SBY A87 KBD_A20GATE B87 VCC_5V_SBY A88 PCIE0_CK_REF+ B88 RSVD A89 PCIE0_CK_REF- B89 VGA_RED A90 GND (FIXED) B90 GND (FIXED) A91 RSVD B91 VGA_GRN A92 RSVD B92 VGA_BLU A93 GPO0 B93 VGA_HSYNC A94 RSVD B94 VGA_VSYNC A95 RSVD B95 VGA_I2C_CK A96 GND B96 VGA_I2C_DAT A97 VCC_12V B97 TV_DAC_A A98 VCC_12V B98 TV_DAC_B A99 VCC_12V B99 TV_DAC_C A100 GND (FIXED) B100 GND (FIXED) A101 VCC_12V B101 VCC_12V A102 VCC_12V B102 VCC_12V A103 VCC_12V B103 VCC_12V A104 VCC_12V B104 VCC_12V A105 VCC_12V B105 VCC_12V A106 VCC_12V B106 VCC_12V A107 VCC_12V B107 VCC_12V

A64 B64 A65 B65 A66 B66 A67 B67 A68 B68 A69 B69 A70 B70 A71 B71 A72 B72 A73 B73 A74 B74 A75 B75 A76 B76 A77 B77 A78 B78 A79 B79 A80 B80 A81 B81

A108 VCC_12V B108 VCC_12V A109 VCC_12V B109 VCC_12V A110 GND (FIXED) B110 GND (FIXED)

A1 GND (FIXED) B1 GND (FIXED) C1 GND (FIXED) D1 A2 GBE0_MDI3- B2 GBE0_ACT# C2 IDE_D7 D2 A3 GBE0_MDI3+ B3 LPC_FRAME# C3 IDE_D6 D3 A4 GBE0_LINK100# B4 LPC_AD0 C4 IDE_D3 D4 A5 GBE0_LINK1000# B5 LPC_AD1 C5 IDE_D15 D5 A6 GBE0_MDI2- B6 LPC_AD2 C6 IDE_D8 D6 A7 GBE0_MDI2+ B7 LPC_AD3 C7 IDE_D9 D7 A8 GBE0_LINK# B8 LPC_DRQ0# C8 IDE_D2 D8 A9 GBE0_MDI1- B9 LPC_DRQ1# C9 IDE_D13 D9 A10 GBE0_MDI1+ B10 LPC_CLK C10 IDE_D1 D10 A11 GND (FIXED) B11 GND (FIXED) C11 GND (FIXED) D11 A12 GBE0_MDI0- B12 PWRBTN# C12 IDE_D14 D12 A13 GBE0_MDI0+ B13 SMB_CK C13 IDE_IORDY D13 A14 GBE0_CTREF B14 SMB_DAT C14 IDE_IOR# D14 A15 SUS_S3# B15 SMB_ALERT# C15 PCI_PME# D15 A16 SATA0_TX+ B16 SATA1_TX+ C16 PCI_GNT2# D16 A17 SATA0_TX- B17 SATA1_TX- C17 PCI_REQ2# D17 A18 SUS_S4# B18 SUS_STAT# C18 PCI_GNT1# D18 A19 SATA0_RX+ B19 SATA1_RX+ C19 PCI_REQ1# D19 A20 SATA0_RX- B20 SATA1_RX- C20 PCI_GNT0# D20 A21 GND (FIXED) B21 GND (FIXED) C21 GND (FIXED) D21 A22 SATA2_TX+ B22 SATA3_TX+ C22 PCI_REQ0# D22 A23 SATA2_TX- B23 SATA3_TX- C23 PCI_RESET# D23 A24 SUS_S5# B24 PWR_OK C24 PCI_AD0 D24 A25 SATA2_RX+ B25 SATA3_RX+ C25 PCI_AD2 D25 A26 SATA2_RX- B26 SATA3_RX- C26 PCI_AD4 D26 A27 BATLOW# B27 WDT C27 PCI_AD6 D27 A28 ATA_ACT# B28 AC_SDIN2 C28 PCI_AD8 D28 A29 AC_SYNC B29 AC_SDIN1 C29 PCI_AD10 D29 A30 AC_RST# B30 AC_SDIN0 C30 PCI_AD12 D30 A31 GND (FIXED) B31 GND (FIXED) C31 GND (FIXED) D31 A32 AC_BITCLK B32 SPKR C32 PCI_AD14 D32 A33 AC_SDOUT B33 I2C_CK C33 PCI_C/BE1# D33 A34 BIOS_DISABLE# B34 I2C_DAT C34 PCI_PERR# D34 A35 THRMTRIP# B35 THRM# C35 PCI_LOCK# D35 A36 USB6- B36 USB7- C36 PCI_DEVSEL# D36 A37 USB6+ B37 USB7+ C37 PCI_IRDY# D37 A38 USB_6_7_OC# B38 USB_4_5_OC# C38 PCI_C/BE2# D38 A39 USB4- B39 USB5- C39 PCI_AD17 D39 A40 USB4+ B40 USB5+ C40 PCI_AD19 D40 A41 GND (FIXED) B41 GND (FIXED) C41 GND (FIXED) D41 A42 USB2- B42 USB3- C42 PCI_AD21 D42 A43 USB2+ B43 USB3+ C43 PCI_AD23 D43 A44 USB_2_3_OC# B44 USB_0_1_OC# C44 PCI_C/BE3# D44 A45 USB0- B45 USB1- C45 PCI_AD25 D45 A46 USB0+ B46 USB1+ C46 PCI_AD27 D46 A47 VCC_RTC B47 EXCD1_PERST# C47 PCI_AD29 D47 A48 EXCD0_PERST# B48 EXCD1_CPPE# C48 PCI_AD31 D48 A49 EXCD0_CPPE# B49 SYS_RESET# C49 PCI_IRQA# D49 A50 LPC_SERIRQ B50 CB_RESET# C50 PCI_IRQB# D50 A51 GND (FIXED) B51 GND (FIXED) C51 GND (FIXED) D51 A52 PCIE_TX5+ B52 PCIE_RX5+ C52 PEG_RX0+ D52 A53 PCIE_TX5- B53 PCIE_RX5- C53 PEG_RX0- D53

Row A Row B Row C

A54 GPI0 B54 GPO1 C54 TYPE0# D54 A55 PCIE_TX4+ B55 PCIE_RX4+ C55 PEG_RX1+ D55 A56 PCIE_TX4- B56 PCIE_RX4- C56 PEG_RX1- D56 A57 GND B57 GPO2 C57 TYPE1# D57 A58 PCIE_TX3+ B58 PCIE_RX3+ C58 PEG_RX2+ D58 A59 PCIE_TX3- B59 PCIE_RX3- C59 PEG_RX2- D59 A60 GND (FIXED) B60 GND (FIXED) C60 GND (FIXED) D60 A61 PCIE_TX2+ B61 PCIE_RX2+ C61 PEG_RX3+ D61 A62 PCIE_TX2- B62 PCIE_RX2- C62 PEG_RX3- D62 A63 GPI1 B63 GPO3 C63 RSVD

PCIE_TX1+ PCIE_RX1+ RSVD PCIE_TX1- PCIE_RX1- PEG_RX4+ GND WAKE0# PEG_RX4- GPI2 WAKE1# RSVD PCIE_TX0+ PCIE_RX0+ PEG_RX5+ PCIE_TX0- PCIE_RX0- PEG_RX5- GND (FIXED) GND (FIXED) GND (FIXED) LVDS_A0+ LVDS_B0+ PEG_RX6+ LVDS_A0- LVDS_B0- PEG_RX6- LVDS_A1+ LVDS_B1+ SDVO_DATA LVDS_A1- LVDS_B1- PEG_RX7+ LVDS_A2+ LVDS_B2+ PEG_RX7- LVDS_A2- LVDS_B2- GND LVDS_VDD_EN LVDS_B3+ RSVD LVDS_A3+ LVDS_B3- PEG_RX8+ LVDS_A3- LVDS_BKLT_EN PEG_RX8- GND (FIXED) GND (FIXED) GND (FIXED) LVDS_A_CK+ LVDS_B_CK+ PEG_RX9+

A82 LVDS_A_CK- B82 LVDS_B_CK- C82 PEG_RX9- D82 A83 LVDS_I2C_CK B83 LVDS_BKLT_CTRL C83 RSVD D83 A84 LVDS_I2C_DAT B84 VCC_5V_SBY C84 GND D84 A85 GPI3 B85 VCC_5V_SBY C85 PEG_RX10+ D85 A86 KBD_RST# B86 VCC_5V_SBY C86 PEG_RX10- D86 A87 KBD_A20GATE B87 VCC_5V_SBY C87 GND D87 A88 PCIE0_CK_REF+ B88 RSVD C88 PEG_RX11+ D88 A89 PCIE0_CK_REF- B89 VGA_RED C89 PEG_RX11- D89 A90 GND (FIXED) B90 GND (FIXED) C90 GND (FIXED) D90 A91 RSVD B91 VGA_GRN C91 PEG_RX12+ D91 A92 RSVD B92 VGA_BLU C92 PEG_RX12- D92 A93 GPO0 B93 VGA_HSYNC C93 GND D93 A94 RSVD B94 VGA_VSYNC C94 PEG_RX13+ D94 A95 RSVD B95 VGA_I2C_CK C95 PEG_RX13- D95 A96 GND B96 VGA_I2C_DAT C96 GND D96 A97 VCC_12V B97 TV_DAC_A C97 RSVD D97 A98 VCC_12V B98 TV_DAC_B C98 PEG_RX14+ D98 A99 VCC_12V B99 TV_DAC_C C99 PEG_RX14- D99 A100 GND (FIXED) B100 GND (FIXED) C100 GND (FIXED) D100 A101 VCC_12V B101 VCC_12V C101 PEG_RX15+ D101 A102 VCC_12V B102 VCC_12V C102 PEG_RX15- D102 A103 VCC_12V B103 VCC_12V C103 GND D103 A104 VCC_12V B104 VCC_12V C104 VCC_12V D104 A105 VCC_12V B105 VCC_12V C105 VCC_12V D105 A106 VCC_12V B106 VCC_12V C106 VCC_12V D106 A107 VCC_12V B107 VCC_12V C107 VCC_12V D107

D63 A64 B64 C64 D64 A65 B65 C65 D65 A66 B66 C66 D66 A67 B67 C67 D67 A68 B68 C68 D68 A69 B69 C69 D69 A70 B70 C70 D70 A71 B71 C71 D71 A72 B72 C72 D72 A73 B73 C73 D73 A74 B74 C74 D74 A75 B75 C75 D75 A76 B76 C76 D76 A77 B77 C77 D77 A78 B78 C78 D78 A79 B79 C79 D79 A80 B80 C80 D80 A81 B81 C81 D81

A108 VCC_12V B108 VCC_12V C108 VCC_12V D108 A109 VCC_12V B109 VCC_12V C109 VCC_12V D109 A110 GND (FIXED) B110 GND (FIXED) C110 GND (FIXED) D110

GND (FIXED) IDE_D5 IDE_D10 IDE_D11 IDE_D12 IDE_D4 IDE_D0 IDE_REQ IDE_IOW# IDE_ACK# GND (FIXED) IDE_IRQ IDE_A0 IDE_A1 IDE_A2 IDE_CS1# IDE_CS3# IDE_RESET# PCI_GNT3# PCI_REQ3# GND (FIXED) PCI_AD1 PCI_AD3 PCI_AD5 PCI_AD7 PCI_C/BE0# PCI_AD9 PCI_AD11 PCI_AD13 PCI_AD15 GND (FIXED) PCI_PAR PCI_SERR# PCI_STOP# PCI_TRDY# PCI_FRAME# PCI_AD16 PCI_AD18 PCI_AD20 PCI_AD22 GND (FIXED) PCI_AD24 PCI_AD26 PCI_AD28 PCI_AD30 PCI_IRQC# PCI_IRQD# PCI_CLKRUN# PCI_M66EN PCI_CLK GND (FIXED) PEG_TX0+ PEG_TX0-

Row D

PEG_LANE_RV# PEG_TX1+ PEG_TX1- TYPE2# PEG_TX2+ PEG_TX2- GND (FIXED) PEG_TX3+ PEG_TX3- RSVD RSVD PEG_TX4+ PEG_TX4- GND PEG_TX5+ PEG_TX5- GND (FIXED) PEG_TX6+ PEG_TX6- SDVO_CLK PEG_TX7+ PEG_TX7- GND IDE_CBLID# PEG_TX8+ PEG_TX8- GND (FIXED) PEG_TX9+ PEG_TX9- RSVD GND PEG_TX10+ PEG_TX10- GND PEG_TX11+ PEG_TX11- GND (FIXED) PEG_TX12+ PEG_TX12- GND PEG_TX13+ PEG_TX13- GND PEG_ENABLE# PEG_TX14+ PEG_TX14- GND (FIXED) PEG_TX15+ PEG_TX15- GND VCC_12V VCC_12V VCC_12V VCC_12V

VCC_12V VCC_12V GND (FIXED)

A1 GND (FIXED) B1 GND (FIXED) A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 B7 A8 B8 A9 B9 A10 B10 A11 GND (FIXED) B11 GND (FIXED) A12 B12 A13 B13 A14 B14 A15 B15 A16 B16 A17 B17 A18 B18 A19 B19 A20 B20 A21 GND (FIXED) B21 GND (FIXED) A22 B22 A23 B23 A24 B24 A25 B25 A26 B26 A27 B27 A28 B28 A29 B29 A30 B30 A31 GND (FIXED) B31 GND (FIXED) A32 B32 A33 B33 A34 B34 A35 B35 A36 B36 A37 B37 A38 B38 A39 B39 A40 B40 A41 GND (FIXED) B41 GND (FIXED) A42 B42 A43 B43 A44 B44 A45 B45 A46 B46 A47 B47 A48 B48 A49 B49 A50 B50 A51 GND (FIXED) B51 GND (FIXED) A52 B52 A53 B53

Row A Row B

GBE0_MDI3- GBE0_ACT# GBE0_MDI3+ LPC_FRAME# GBE0_LINK100# LPC_AD0 GBE0_LINK1000# LPC_AD1 GBE0_MDI2- LPC_AD2 GBE0_MDI2+ LPC_AD3 GBE0_LINK# LPC_DRQ0# GBE0_MDI1- LPC_DRQ1# GBE0_MDI1+ LPC_CLK

GBE0_MDI0- PWRBTN# GBE0_MDI0+ SMB_CK GBE0_CTREF SMB_DAT SUS_S3# SMB_ALERT# SATA0_TX+ SATA1_TX+ SATA0_TX- SATA1_TX- SUS_S4# SUS_STAT# SATA0_RX+ SATA1_RX+ SATA0_RX- SATA1_RX-

RSVD14 RSVD14

RSVD14 RSVD14

SUS_S5# PWR_OK RSVD14 RSVD14

RSVD14 RSVD14

BATLOW# WDT (S)ATA_ACT# AC/HDA_SDIN2 AC/HDA_SYNC AC/HDA_SDIN1 AC/HDA_RST# AC/HDA_SDIN0

AC/HDA_BITCLK SPKR AC/HDA_SDOUT I2C_CK BIOS_DIS0# I2C_DAT THRMTRIP# THRM# USB6- USB7- USB6+ USB7+ USB_6_7_OC# USB_4_5_OC# USB4- USB5- USB4+ USB5+

USB2- USB3- USB2+ USB3+ USB_2_3_OC# USB_0_1_OC# USB0- USB1- USB0+ USB1+ VCC_RTC EXCD1_PERST# EXCD0_PERST# EXCD1_CPPE# EXCD0_CPPE# SYS_RESET# LPC_SERIRQ CB_RESET#

RSVD14 RSVD14

RSVD14 RSVD14

A54 B54 A55 B55 A56 B56 A57 GND B57 A58 B58 A59 B59 A60 GND (FIXED) B60 GND (FIXED) A61 B61 A62 B62 A63 B63 A64 B64 A65 B65 A66 GND B66 A67 B67 A68 B68 A69 B69 A70 GND (FIXED) B70 GND (FIXED) A71 B71 DDI0_PAIR0+ A72 B72 DDI0_PAIR0- A73 B73 DDI0_PAIR1+ A74 B74 DDI0_PAIR1- A75 B75 DDI0_PAIR2+ A76 B76 DDI0_PAIR2- A77 B77 DDI0_PAIR4+ A78 B78 DDI0_PAIR4- A79 B79 A80 GND (FIXED) B80 GND (FIXED) A81 B81 DDI0_PAIR3+ A82 B82 DDI0_PAIR3- A83 B83 A84 B84 A85 B85 A86 B86 A87 B87 A88 B88 BIOS_DIS1# A89 B89 DD0_HPD A90 GND (FIXED) B90 GND (FIXED) A91 SPI_POWER B91 DDI0_PAIR5+ A92 SPI_MISO B92 DDI0_PAIR5- A93 B93 DDI0_PAIR6+ A94 SPI_CLK B94 DDI0_PAIR6- A95 SPI_MOSI B95 DDI0_DDC_AUX_SEL A96 TPM_PP B96 A97 TYPE10# B97 SPI_CS# A98 SER0_TX B98 DDI0_CTRLCLK_AUX+ A99 SER0_RX B99 DDI0_CTRLDATA_AUX- A100 GND (FIXED) B100 GND (FIXED) A101 B101 A102 B102 A103 B103 A104 B104 A105 B105 A106 B106 A107 B107

GPI0 GPO1 RSVD14 RSVD14

RSVD14 RSVD14

GPO2 PCIE_TX3+ PCIE_RX3+ PCIE_TX3- PCIE_RX3-

PCIE_TX2+ PCIE_RX2+ PCIE_TX2- PCIE_RX2- GPI1 GPO3 PCIE_TX1+ PCIE_RX1+ PCIE_TX1- PCIE_RX1-

WAKE0# GPI2 WAKE1# PCIE_TX0+ PCIE_RX0+ PCIE_TX0- PCIE_RX0-

LVDS_A0+ LVDS_A0- LVDS_A1+ LVDS_A1- LVDS_A2+ LVDS_A2- LVDS_VDD_EN LVDS_A3+ LVDS_A3- LVDS_BKLT_EN

LVDS_A_CK+ LVDS_A_CK- LVDS_I2C_CK LVDS_BKLT_CTRL LVDS_I2C_DAT VCC_5V_SBY GPI3 VCC_5V_SBY RSVD14 VCC_5V_SBY RSVD14 VCC_5V_SBY PCIE_CLK_REF+ PCIE_CLK_REF-

GPO0

RSVD14

SER1_TX FAN_PWMOUT SER1_RX FAN_TACHIN LID# SLEEP# VCC_12V VCC_12V VCC_12V VCC_12V VCC_12V VCC_12V VCC_12V VCC_12V

A108 B108 A109 B109 A110 GND (FIXED) B110 GND (FIXED)

VCC_12V VCC_12V VCC_12V VCC_12V

14RSVD pins are reserved for future use and should be no connect. Do not tie the RSVD pins together.

GND (FIXED)

Row A Row B A1 GND (FIXED) B1 GND (FIXED) A2 GBE0_MDI3- B2 GBE0_ACT# A3 GBE0_MDI3+ B3 LPC_FRAME# A4 GBE0_LINK100# B4 LPC_AD0 A5 GBE0_LINK1000# B5 LPC_AD1 A6 GBE0_MDI2- B6 LPC_AD2 A7 GBE0_MDI2+ B7 LPC_AD3 A8 GBE0_LINK# B8 LPC_DRQ0# A9 GBE0_MDI1- B9 LPC_DRQ1# A10 GBE0_MDI1+ B10 LPC_CLK A11 B11 GND (FIXED) A12 GBE0_MDI0- B12 PWRBTN# A13 GBE0_MDI0+ B13 SMB_CK A14 GBE0_CTREF B14 SMB_DAT A15 SUS_S3# B15 SMB_ALERT# A16 SATA0_TX+ B16 SATA1_TX+ A17 SATA0_TX- B17 SATA1_TX- A18 SUS_S4# B18 SUS_STAT# A19 SATA0_RX+ B19 SATA1_RX+ A20 SATA0_RX- B20 SATA1_RX- A21 GND (FIXED) B21 GND (FIXED) A22 SATA2_TX+ B22 SATA3_TX+ A23 SATA2_TX- B23 SATA3_TX- A24 SUS_S5# B24 PWR_OK A25 SATA2_RX+ B25 SATA3_RX+ A26 SATA2_RX- B26 SATA3_RX- A27 BATLOW# B27 WDT A28 (S)ATA_ACT# B28 AC/HDA_SDIN2 A29 AC/HDA_SYNC B29 AC/HDA_SDIN1 A30 AC/HDA_RST# B30 AC/HDA_SDIN0 A31 GND (FIXED) B31 GND (FIXED) A32 AC/HDA_BITCLK B32 SPKR A33 AC/HDA_SDOUT B33 I2C_CK A34 BIOS_DIS0# B34 I2C_DAT A35 THRMTRIP# B35 THRM# A36 USB6- B36 USB7- A37 USB6+ B37 USB7+ A38 USB_6_7_OC# B38 USB_4_5_OC# A39 USB4- B39 USB5- A40 USB4+ B40 USB5+ A41 GND (FIXED) B41 GND (FIXED) A42 USB2- B42 USB3- A43 USB2+ B43 USB3+ A44 USB_2_3_OC# B44 USB_0_1_OC# A45 USB0- B45 USB1- A46 USB0+ B46 USB1+ A47 VCC_RTC B47 EXCD1_PERST# A48 EXCD0_PERST# B48 EXCD1_CPPE# A49 EXCD0_CPPE# B49 SYS_RESET# A50 LPC_SERIRQ B50 CB_RESET# A51 GND (FIXED) B51 GND (FIXED) A52 PCIE_TX5+ B52 PCIE_RX5+ A53 PCIE_TX5- B53 PCIE_RX5-

A54 GPI0 B54 GPO1 A55 PCIE_TX4+ B55 PCIE_RX4+ A56 PCIE_TX4- B56 PCIE_RX4- A57 GND B57 GPO2 A58 PCIE_TX3+ B58 PCIE_RX3+ A59 PCIE_TX3- B59 PCIE_RX3- A60 GND (FIXED) B60 GND (FIXED) A61 PCIE_TX2+ B61 PCIE_RX2+ A62 PCIE_TX2- B62 PCIE_RX2- A63 GPI1 B63 GPO3 A64 PCIE_TX1+ B64 PCIE_RX1+ A65 PCIE_TX1- B65 PCIE_RX1- A66 GND B66 WAKE0# A67 GPI2 B67 WAKE1# A68 PCIE_TX0+ B68 PCIE_RX0+ A69 PCIE_TX0- B69 PCIE_RX0- A70 GND (FIXED) B70 GND (FIXED) A71 LVDS_A0+ B71 LVDS_B0+ A72 LVDS_A0- B72 LVDS_B0- A73 LVDS_A1+ B73 LVDS_B1+ A74 LVDS_A1- B74 LVDS_B1- A75 LVDS_A2+ B75 LVDS_B2+ A76 LVDS_A2- B76 LVDS_B2- A77 LVDS_VDD_EN B77 LVDS_B3+ A78 LVDS_A3+ B78 LVDS_B3- A79 LVDS_A3- B79 LVDS_BKLT_EN A80 GND (FIXED) B80 GND (FIXED) A81 LVDS_A_CK+ B81 LVDS_B_CK+ A82 LVDS_A_CK- B82 LVDS_B_CK- A83 LVDS_I2C_CK B83 LVDS_BKLT_CTRL A84 LVDS_I2C_DAT B84 VCC_5V_SBY A85 GPI3 B85 VCC_5V_SBY A86 KBD_RST# B86 VCC_5V_SBY A87 KBD_A20GATE B87 VCC_5V_SBY A88 PCIE_CLK_REF+ B88 BIOS_DIS1# A89 PCIE_CLK_REF- B89 VGA_RED A90 GND (FIXED) B90 GND (FIXED) A91 SPI_POWER B91 VGA_GRN A92 SPI_MISO B92 VGA_BLU A93 GPO0 B93 VGA_HSYNC A94 SPI_CLK B94 VGA_VSYNC A95 SPI_MOSI B95 VGA_I2C_CK A96 GND B96 VGA_I2C_DAT A97 TYPE10# B97 SPI_CS# A98 RSVD13 B98 RSVD13 A99 RSVD13 B99 RSVD13 A100 GND (FIXED) B100 GND (FIXED) A101 RSVD13 B101 RSVD13 A102 RSVD13 B102 RSVD13 A103 RSVD13 B103 RSVD13 A104 VCC_12V B104 VCC_12V A105 VCC_12V B105 VCC_12V A106 VCC_12V B106 VCC_12V A107 VCC_12V B107 VCC_12V

A108 VCC_12V B108 VCC_12V A109 VCC_12V B109 VCC_12V A110 GND (FIXED) B110 GND (FIXED) 13RSVD pins are reserved for future use and should be no connect. Do not tie the RSVD pins together.

A1 GND (FIXED) B1 GND (FIXED) C1 A2 GBE0_MDI3- B2 GBE0_ACT# C2 A3 GBE0_MDI3+ B3 LPC_FRAME# C3 A4 GBE0_LINK100# B4 LPC_AD0 C4 A5 GBE0_LINK1000# B5 LPC_AD1 C5 A6 GBE0_MDI2- B6 LPC_AD2 C6 A7 GBE0_MDI2+ B7 LPC_AD3 C7 A8 GBE0_LINK# B8 LPC_DRQ0# C8 A9 GBE0_MDI1- B9 LPC_DRQ1# C9 A10 GBE0_MDI1+ B10 LPC_CLK C10 A11 GND (FIXED) B11 GND (FIXED) C11 A12 GBE0_MDI0- B12 PWRBTN# C12 A13 GBE0_MDI0+ B13 SMB_CK C13 A14 GBE0_CTREF B14 SMB_DAT C14 A15 SUS_S3# B15 SMB_ALERT# C15 A16 SATA0_TX+ B16 SATA1_TX+ C16 A17 SATA0_TX- B17 SATA1_TX- C17 A18 SUS_S4# B18 SUS_STAT# C18 A19 SATA0_RX+ B19 SATA1_RX+ C19 A20 SATA0_RX- B20 SATA1_RX- C20 A21 GND (FIXED) B21 GND (FIXED) C21 A22 SATA2_TX+ B22 SATA3_TX+ C22 A23 SATA2_TX- B23 SATA3_TX- C23 A24 SUS_S5# B24 PWR_OK C24 A25 SATA2_RX+ B25 SATA3_RX+ C25 A26 SATA2_RX- B26 SATA3_RX- C26 A27 BATLOW# B27 WDT C27 A28 B28 C28 A29 B29 C29 A30 B30 C30 A31 GND (FIXED) B31 GND (FIXED) C31 A32 B32 SPKR C32 A33 B33 I2C_CK C33 A34 B34 I2C_DAT C34 A35 THRMTRIP# B35 THRM# C35 A36 USB6- B36 USB7- C36 A37 USB6+ B37 USB7+ C37 A38 USB_6_7_OC# B38 USB_4_5_OC# C38 A39 USB4- B39 USB5- C39 A40 USB4+ B40 USB5+ C40 A41 GND (FIXED) B41 GND (FIXED) C41 A42 USB2- B42 USB3- C42 A43 USB2+ B43 USB3+ C43 A44 USB_2_3_OC# B44 USB_0_1_OC# C44 A45 USB0- B45 USB1- C45 A46 USB0+ B46 USB1+ C46 A47 VCC_RTC B47 EXCD1_PERST# C47 A48 EXCD0_PERST# B48 EXCD1_CPPE# C48 A49 EXCD0_CPPE# B49 SYS_RESET# C49 A50 LPC_SERIRQ B50 CB_RESET# C50 A51 GND (FIXED) B51 GND (FIXED) C51 A52 PCIE_TX5+ B52 PCIE_RX5+ C52 A53 PCIE_TX5- B53 PCIE_RX5- C53

Row A Row B

(S)ATA_ACT# AC/HDA_SDIN2 AC/HDA_SYNC AC/HDA_SDIN1 AC/HDA_RST# AC/HDA_SDIN0

AC/HDA_BITCLK AC/HDA_SDOUT BIOS_DIS0#

A54 GPI0 B54 GPO1 C54 A55 PCIE_TX4+ B55 PCIE_RX4+ C55 A56 PCIE_TX4- B56 PCIE_RX4- C56 A57 GND B57 GPO2 C57 A58 PCIE_TX3+ B58 PCIE_RX3+ C58 A59 PCIE_TX3- B59 PCIE_RX3- C59 A60 GND (FIXED) B60 GND (FIXED) C60 A61 PCIE_TX2+ B61 PCIE_RX2+ C61 A62 PCIE_TX2- B62 PCIE_RX2- C62 A63 GPI1 B63 GPO3 C63


A82 LVDS_A_CK- B82 LVDS_B_CK- C82 A83 LVDS_I2C_CK B83 LVDS_BKLT_CTRL C83 A84 LVDS_I2C_DAT B84 VCC_5V_SBY C84 A85 GPI3 B85 VCC_5V_SBY C85 A86 KBD_RST# B86 VCC_5V_SBY C86 A87 KBD_A20GATE B87 VCC_5V_SBY C87 A88 B88 BIOS_DIS1# C88 A89 B89 VGA_RED C89 A90 GND (FIXED) B90 GND (FIXED) C90 A91 B91 VGA_GRN C91 A92 B92 VGA_BLU C92 A93 B93 VGA_HSYNC C93 A94 B94 VGA_VSYNC C94 A95 B95 VGA_I2C_CK C95 A96 B96 VGA_I2C_DAT C96 A97 B97 C97 A98 B98 C98 A99 B99 C99 A100 B100 GND (FIXED) C100 A101 B101 C101 A102 B102 C102 A103 B103 C103 A104 VCC_12V B104 VCC_12V C104 A105 VCC_12V B105 VCC_12V C105 A106 VCC_12V B106 VCC_12V C106

A64 B64 C64 A65 B65 C65 A66 B66 C66 A67 B67 C67 A68 B68 C68 A69 B69 C69 A70 B70 C70 A71 B71 C71 A72 B72 C72 A73 B73 C73 A74 B74 C74 A75 B75 C75 A76 B76 C76 A77 B77 C77 A78 B78 C78 A79 B79 C79 A80 B80 C80 A81 B81 C81

PCIE_CLK_REF+ PCIE_CLK_REF-

SPI_POWER SPI_MISO GPO0 SPI_CLK SPI_MOSI GND TYPE10# SPI_CS# RSVD15 RSVD15 RSVD15 RSVD15 GND (FIXED) RSVD15 RSVD15 RSVD15 RSVD15 RSVD15 RSVD15

A107 VCC_12V B107 VCC_12V C107 A108 VCC_12V B108 VCC_12V C108 A109 VCC_12V B109 VCC_12V C109 A110 GND (FIXED) B110 GND (FIXED) C110 15 RSVD pins are reserved for future use and should be no connect. Do not tie the RSVD pins together.

GND (FIXED) D1 GND (FIXED) IDE_D7 D2 IDE_D5 IDE_D6 D3 IDE_D10 IDE_D3 D4 IDE_D11 IDE_D15 D5 IDE_D12 IDE_D8 D6 IDE_D4 IDE_D9 D7 IDE_D0 IDE_D2 D8 IDE_REQ IDE_D13 D9 IDE_IOW# IDE_D1 D10 IDE_ACK# GND (FIXED) D11 GND (FIXED) IDE_D14 D12 IDE_IRQ IDE_IORDY D13 IDE_A0 IDE_IOR# D14 IDE_A1 PCI_PME# D15 IDE_A2 PCI_GNT2# D16 IDE_CS1# PCI_REQ2# D17 IDE_CS3# PCI_GNT1# D18 IDE_RESET# PCI_REQ1# D19 PCI_GNT3# PCI_GNT0# D20 PCI_REQ3# GND (FIXED) D21 GND (FIXED) PCI_REQ0# D22 PCI_AD1 PCI_RESET# D23 PCI_AD3 PCI_AD0 D24 PCI_AD5 PCI_AD2 D25 PCI_AD7 PCI_AD4 D26 PCI_C/BE0# PCI_AD6 D27 PCI_AD9 PCI_AD8 D28 PCI_AD11 PCI_AD10 D29 PCI_AD13 PCI_AD12 D30 PCI_AD15 GND (FIXED) D31 GND (FIXED) PCI_AD14 D32 PCI_PAR PCI_C/BE1# D33 PCI_SERR# PCI_PERR# D34 PCI_STOP# PCI_LOCK# D35 PCI_TRDY# PCI_DEVSEL# D36 PCI_FRAME# PCI_IRDY# D37 PCI_AD16 PCI_C/BE2# D38 PCI_AD18 PCI_AD17 D39 PCI_AD20 PCI_AD19 D40 PCI_AD22 GND (FIXED) D41 GND (FIXED) PCI_AD21 D42 PCI_AD24 PCI_AD23 D43 PCI_AD26 PCI_C/BE3# D44 PCI_AD28 PCI_AD25 D45 PCI_AD30 PCI_AD27 D46 PCI_IRQC# PCI_AD29 D47 PCI_IRQD# PCI_AD31 D48 PCI_CLKRUN# PCI_IRQA# D49 PCI_M66EN PCI_IRQB# D50 PCI_CLK GND (FIXED) D51 GND (FIXED) PEG_RX0+ D52 PEG_TX0+ PEG_RX0- D53 PEG_TX0-

Row C Row D

TYPE0# D54 PEG_LANE_RV# PEG_RX1+ D55 PEG_TX1+ PEG_RX1- D56 PEG_TX1- TYPE1# D57 TYPE2# PEG_RX2+ D58 PEG_TX2+ PEG_RX2- D59 PEG_TX2- GND (FIXED) D60 GND (FIXED) PEG_RX3+ D61 PEG_TX3+ PEG_RX3- D62 PEG_TX3-

PEG_RX4+ PEG_TX4+ PEG_RX4- PEG_TX4-

GND PEG_RX5+ PEG_TX5+ PEG_RX5- PEG_TX5- GND (FIXED) GND (FIXED) PEG_RX6+ PEG_TX6+ PEG_RX6- PEG_TX6- SDVO_DATA SDVO_CLK PEG_RX7+ PEG_TX7+ PEG_RX7- PEG_TX7- GND GND

IDE_CBLID# PEG_RX8+ PEG_TX8+ PEG_RX8- PEG_TX8- GND (FIXED) GND (FIXED) PEG_RX9+ PEG_TX9+ PEG_RX9- D82 PEG_TX9-

D83 GND D84 GND PEG_RX10+ D85 PEG_TX10+ PEG_RX10- D86 PEG_TX10- GND D87 GND PEG_RX11+ D88 PEG_TX11+ PEG_RX11- D89 PEG_TX11- GND (FIXED) D90 GND (FIXED) PEG_RX12+ D91 PEG_TX12+ PEG_RX12- D92 PEG_TX12- GND D93 GND PEG_RX13+ D94 PEG_TX13+ PEG_RX13- D95 PEG_TX13- GND D96 GND

D97 PEG_ENABLE# PEG_RX14+ D98 PEG_TX14+ PEG_RX14- D99 PEG_TX14- GND (FIXED) D100 GND (FIXED) PEG_RX15+ D101 PEG_TX15+ PEG_RX15- D102 PEG_TX15- GND D103 GND VCC_12V D104 VCC_12V VCC_12V D105 VCC_12V VCC_12V D106 VCC_12V

RSVD15 D63 RSVD15

RSVD15 D64 RSVD15

D65 D66

RSVD15 D67 D68 D69 D70 D71 D72 D73 D74 D75 D76

RSVD15 D77 D78 D79 D80 D81

RSVD15 RSVD15

RSVD15

VCC_12V D107 VCC_12V VCC_12V D108 VCC_12V VCC_12V D109 VCC_12V GND (FIXED) D110 GND (FIXED)


A1 GND (FIXED) B1 GND (FIXED) C1 A2 GBE0_MDI3- B2 GBE0_ACT# C2 A3 GBE0_MDI3+ B3 LPC_FRAME# C3 A4 GBE0_LINK100# B4 LPC_AD0 C4 A5 GBE0_LINK1000# B5 LPC_AD1 C5 A6 GBE0_MDI2- B6 LPC_AD2 C6 A7 GBE0_MDI2+ B7 LPC_AD3 C7 A8 GBE0_LINK# B8 LPC_DRQ0# C8 A9 GBE0_MDI1- B9 LPC_DRQ1# C9 A10 GBE0_MDI1+ B10 LPC_CLK C10 A11 GND (FIXED) B11 GND (FIXED) C11 A12 GBE0_MDI0- B12 PWRBTN# C12 A13 GBE0_MDI0+ B13 SMB_CK C13 A14 GBE0_CTREF B14 SMB_DAT C14 A15 SUS_S3# B15 SMB_ALERT# C15 A16 SATA0_TX+ B16 SATA1_TX+ C16 A17 SATA0_TX- B17 SATA1_TX- C17 A18 SUS_S4# B18 SUS_STAT# C18 A19 SATA0_RX+ B19 SATA1_RX+ C19 A20 SATA0_RX- B20 SATA1_RX- C20 A21 GND (FIXED) B21 GND (FIXED) C21 A22 SATA2_TX+ B22 SATA3_TX+ C22 A23 SATA2_TX- B23 SATA3_TX- C23 A24 SUS_S5# B24 PWR_OK C24 A25 SATA2_RX+ B25 SATA3_RX+ C25 A26 SATA2_RX- B26 SATA3_RX- C26 A27 BATLOW# B27 WDT C27 A28 (S)ATA_ACT# B28 AC/HDA_SDIN2 C28 A29 AC/HDA_SYNC B29 AC/HDA_SDIN1 C29 A30 AC/HDA_RST# B30 AC/HDA_SDIN0 C30 A31 GND (FIXED) B31 GND (FIXED) C31 A32 AC/HDA_BITCLK B32 SPKR C32 A33 AC/HDA_SDOUT B33 I2C_CK C33 A34 BIOS_DIS0# B34 I2C_DAT C34 A35 THRMTRIP# B35 THRM# C35 A36 USB6- B36 USB7- C36 A37 USB6+ B37 USB7+ C37 A38 USB_6_7_OC# B38 USB_4_5_OC# C38 A39 USB4- B39 USB5- C39 A40 USB4+ B40 USB5+ C40 A41 GND (FIXED) B41 GND (FIXED) C41 A42 USB2- B42 USB3- C42 A43 USB2+ B43 USB3+ C43 A44 USB_2_3_OC# B44 USB_0_1_OC# C44 A45 USB0- B45 USB1- C45 A46 USB0+ B46 USB1+ C46 A47 VCC_RTC B47 EXCD1_PERST# C47 A48 EXCD0_PERST# B48 EXCD1_CPPE# C48 A49 EXCD0_CPPE# B49 SYS_RESET# C49 A50 LPC_SERIRQ B50 CB_RESET# C50 A51 GND (FIXED) B51 GND (FIXED) C51 A52 PCIE_TX5+ B52 PCIE_RX5+ C52

Row A Row B

A53 PCIE_TX5- B53 PCIE_RX5- C53 A54 GPI0 B54 GPO1 C54 A55 PCIE_TX4+ B55 PCIE_RX4+ C55 A56 PCIE_TX4- B56 PCIE_RX4- C56 A57 GND B57 GPO2 C57 A58 PCIE_TX3+ B58 PCIE_RX3+ C58 A59 PCIE_TX3- B59 PCIE_RX3- C59 A60 GND (FIXED) B60 GND (FIXED) C60 A61 PCIE_TX2+ B61 PCIE_RX2+ C61 A62 PCIE_TX2- B62 PCIE_RX2- C62 A63 GPI1 B63 GPO3 C63


A82 LVDS_A_CK- B82 LVDS_B_CK- C82 A83 LVDS_I2C_CK B83 LVDS_BKLT_CTRL C83 A84 LVDS_I2C_DAT B84 VCC_5V_SBY C84 A85 GPI3 B85 VCC_5V_SBY C85 A86 B86 VCC_5V_SBY C86 A87 B87 VCC_5V_SBY C87 A88 PCIE_CLK_REF+ B88 BIOS_DIS1# C88 A89 PCIE_CLK_REF- B89 VGA_RED C89 A90 GND (FIXED) B90 GND (FIXED) C90 A91 SPI_POWER B91 VGA_GRN C91 A92 SPI_MISO B92 VGA_BLU C92 A93 GPO0 B93 VGA_HSYNC C93 A94 SPI_CLK B94 VGA_VSYNC C94 A95 SPI_MOSI B95 VGA_I2C_CK C95 A96 TPM_PP B96 VGA_I2C_DAT C96 A97 TYPE10# B97 SPI_CS# C97 A98 SER0_TX B98 C98 A99 SER0_RX B99 C99 A100 GND (FIXED) B100 GND (FIXED) C100 A101 SER1_TX B101 FAN_PWMOUT C101 A102 SER1_RX B102 FAN_TACHIN C102 A103 LID# B103 SLEEP# C103 A104 VCC_12V B104 VCC_12V C104 A105 VCC_12V B105 VCC_12V C105

A64 B64 C64 A65 B65 C65 A66 B66 C66 A67 B67 C67 A68 B68 C68 A69 B69 C69 A70 B70 C70 A71 B71 C71 A72 B72 C72 A73 B73 C73 A74 B74 C74 A75 B75 C75 A76 B76 C76 A77 B77 C77 A78 B78 C78 A79 B79 C79 A80 B80 C80 A81 B81 C81

RSVD19 RSVD19

RSVD19 RSVD19

A106 VCC_12V B106 VCC_12V C106 A107 VCC_12V B107 VCC_12V C107 A108 VCC_12V B108 VCC_12V C108 A109 VCC_12V B109 VCC_12V C109 A110 GND (FIXED) B110 GND (FIXED) C110 19 RSVD pins are reserved for future use and should be no connect. Do not tie the RSVD pins together.

GND (FIXED) D1 GND (FIXED) GND D2 GND USB_SSRX0- D3 USB_SSTX0- USB_SSRX0+ D4 USB_SSTX0+ GND D5 GND USB_SSRX1- D6 USB_SSTX1- USB_SSRX1+ D7 USB_SSTX1+ GND D8 GND USB_SSRX2- D9 USB_SSTX2- USB_SSRX2+ D10 USB_SSTX2+ GND (FIXED) D11 GND (FIXED) USB_SSRX3- D12 USB_SSTX3- USB_SSRX3+ D13 USB_SSTX3+ GND D14 GND DDI1_PAIR6+ D15 DDI1_CTRLCLK_AUX+ DDI1_PAIR6- D16 DDI1_CTRLDATA_AUX-

D17 D18

PCIE_RX6+ D19 PCIE_TX6+ PCIE_RX6- D20 PCIE_TX6- GND (FIXED) D21 GND (FIXED) PCIE_RX7+ D22 PCIE_TX7+ PCIE_RX7- D23 PCIE_TX7- DDI1_HPD D24 DDI1_PAIR4 + D25 DDI1_PAIR4- D26 DDI1_PAIR0+

D27 DDI1_PAIR0- D28

DDI1_PAIR5+ D29 DDI1_PAIR1+ DDI1_PAIR5- D30 DDI1_PAIR1- GND (FIXED) D31 GND (FIXED) DDI2_CTRLCLK_AUX+ D32 DDI1_PAIR2+ DDI2_CTRLDATA_AUX- D33 DDI1_PAIR2- DDI2_DDC_AUX_SEL D34 DDI1_DDC_AUX_SEL

D35 DDI3_CTRLCLK_AUX+ D36 DDI1_PAIR3+ DDI3_CTRLDATA_AUX- D37 DDI1_PAIR3- DDI3_DDC_AUX_SEL D38 DDI3_PAIR0+ D39 DDI2_PAIR0+ DDI3_PAIR0- D40 DDI2_PAIR0- GND (FIXED) D41 GND (FIXED) DDI3_PAIR1+ D42 DDI2_PAIR1+ DDI3_PAIR1- D43 DDI2_PAIR1- DDI3_HPD D44 DDI2_HPD

D45 DDI3_PAIR2+ D46 DDI2_PAIR2+ DDI3_PAIR2- D47 DDI2_PAIR2-

D48 DDI3_PAIR3+ D49 DDI2_PAIR3+ DDI3_PAIR3- D50 DDI2_PAIR3- GND (FIXED) D51 GND (FIXED) PEG_RX0+ D52 PEG_TX0+

Row C Row D

RSVD19 RSVD19 RSVD19 RSVD19

RSVD19 RSVD19

RSVD19 RSVD19 RSVD19

RSVD19 RSVD19

RSVD19

RSVD19 RSVD19

RSVD19 RSVD19

PEG_RX0- D53 PEG_TX0- TYPE0# D54 PEG_LANE_RV# PEG_RX1+ D55 PEG_TX1+ PEG_RX1- D56 PEG_TX1- TYPE1# D57 TYPE2# PEG_RX2+ D58 PEG_TX2+ PEG_RX2- D59 PEG_TX2- GND (FIXED) D60 GND (FIXED) PEG_RX3+ D61 PEG_TX3+ PEG_RX3- D62 PEG_TX3-

PEG_RX4+ PEG_TX4+ PEG_RX4- PEG_TX4-

GND PEG_RX5+ PEG_TX5+ PEG_RX5- PEG_TX5- GND (FIXED) GND (FIXED) PEG_RX6+ PEG_TX6+ PEG_RX6- PEG_TX6- GND GND PEG_RX7+ PEG_TX7+ PEG_RX7- PEG_TX7- GND GND

PEG_RX8+ PEG_TX8+ PEG_RX8- PEG_TX8- GND (FIXED) GND (FIXED) PEG_RX9+ PEG_TX9+ PEG_RX9- D82 PEG_TX9-

D83 GND D84 GND PEG_RX10+ D85 PEG_TX10+ PEG_RX10- D86 PEG_TX10- GND D87 GND PEG_RX11+ D88 PEG_TX11+ PEG_RX11- D89 PEG_TX11- GND (FIXED) D90 GND (FIXED) PEG_RX12+ D91 PEG_TX12+ PEG_RX12- D92 PEG_TX12- GND D93 GND PEG_RX13+ D94 PEG_TX13+ PEG_RX13- D95 PEG_TX13- GND D96 GND

D97 PEG_RX14+ D98 PEG_TX14+ PEG_RX14- D99 PEG_TX14- GND (FIXED) D100 GND (FIXED) PEG_RX15+ D101 PEG_TX15+ PEG_RX15- D102 PEG_TX15- GND D103 GND VCC_12V D104 VCC_12V VCC_12V D105 VCC_12V

RSVD19 D63 RSVD19 RSVD19 D64 RSVD19

D65 D66

RSVD19 D67 D68 D69 D70 D71 D72 D73 D74 D75 D76

RSVD19 D77 RSVD19 D78 D79 D80 D81

RSVD19 RSVD19

RSVD19 RSVD19

VCC_12V D106 VCC_12V VCC_12V D107 VCC_12V VCC_12V D108 VCC_12V VCC_12V D109 VCC_12V GND (FIXED) D110 GND (FIXED)


Loss Budgets for High Speed Differential Interfaces

COM ExpressTM Module and Carrier Board insertion loss budgets for the PCI Express, SATA, USB and GBE interfaces are presented in the following sectionsThe COM ExpressTM Module and Carrier Board insertion loss budgets were formulated to be compatible with the relevant source specifications. The source specifications vary in their treatment of insertion loss parameters. For example, the PCI Express Card Electromechanical Specification factors cross talk losses into the insertion loss budgets, but the SATA, USB and GBE source specifications do not.For frequency dependent material losses, a rule-of-thumb insertion loss value of 0.28 dB per inch per GHz is used in all cases, representative of commonly used FR4 PCB laminates. This value is consistent with the PCI Express Card Electromechanical Specification usage (which calls out a 1.4 dB material loss for 4 inches of trace at 1.25 GHz). It is also consistent with other PICMG® specifications that use values slightly above and below this value.Module and Carrier Board vendors may elect to use PCB laminates with better characteristics than common FR4. If this is done, then the trace lengths referenced in the following sections may be extended as long as the net insertion loss budgets are met.Loss budgets for future generations of PCI Express (Gen 2), Ethernet (10 Gbps) and SATA (Gen 3) will be addressed in future revisions to this document.There is no explicit COM ExpressTM jitter budget for the high speed differential interfaces. Designers are referred to the relevant source specifications (PCIE, SATA, USB and GBE) for system jitter budgets.

To develop guidelines for PCI Express Gen 2 (5 GT/s) operation, a series of simulations that modeled PCIe Gen2 operations in the COM Express environment was conducted per the recommendations given in the PCI-SIG PCI Express ® Base Specification, Rev 2.1, Section 4.3.6, “Channel Specifications”. The following two paragraphs excerpted from the PCI-SIG document, Section 4.3.6.2, “Channel Characteristics at 5.0 GT/s” may serve as an overview of the PCI-SIG recommendations:

At 5.0 GT/s a more accurate method of comprehending the effects of channel loss is required in order to avoid excessive guardbanding. The method described here imports the channel’s s-parameters into a simulation environment that includes worst case models for Transmitters and data patterns.The resulting time domain simulation yields eye diagrams from which voltage and timing margins may be obtained and compared against those defined for the Receiver.Note: The methodology described in Sections 4.3.6.2 through 4.3.6.2.7 must be applied to 5.0 GT/s designs, and may be applied to 2.5 GT/s designs. A channel's characteristics are completely defined by its s-parameters, in particular: insertion loss, return loss, and aggressor-victim coupling. It can been demonstrated that these parameters are sufficient to completely quantize all channel-induced phenomena affecting eye margins including I/O-channel impedance mismatch, insertion loss, jitter amplification, impedance discontinuities, and crosstalk. Long channels tend to be dominated by insertion loss and crosstalk, while short channels tend to dominated by impedance discontinuities. Since both types of channels are possible in PCI Express implementations, it is necessary provide a means of characterizing the channel that comprehends all possible channel characteristics.

All relevant elements of the COM Express environment were included in the simulations: a PCIe Gen 2 source, package breakout, coupling capacitors, Module trace, COM Express connector, Carrier Board trace, and Carrier Board target device, for the “Device Down” case.

The “Device Up” case was also simulated, adding in the effects of a Slot Card connector and trace. Cross-talk, jitter and inter-symbol interference effects were included in the simulations, and both the common clocked and data clocked PCIe operations were considered. The simulations were carried out assuming that the Module, Carrier, and Slot PCBs care constructed with standard FR4 dielectrics. Full details of these simulations may be found in the document titled 'PCIe Gen2 COM Express Hardware Simulation Report', available from the PICMG.

The conclusions drawn from the simulations are that the eye margins are dominated by the trace length in the various sections and the jitter components, and that connector losses and crosstalk play minor roles. For Gen 2 operation, the maximum allowed PCIe trace lengths need to be shorter than those that were allowed for Gen 1 operation.

Mechanical SpecificationsModule Size - Compact Module

Compact Module Form Factor

Module Size — Basic Module

Basic Module Form Factor

The PCB size for the Compact Module shall be 95mm x 95mm. The PCB thickness should be 2mm to allow high layer count stack-ups and facilitate a standard ‘z’ dimension between the Carrier Board and the top of the heat-spreader (See “Heat-Spreader“). The holes shown in this drawing are intended for mounting the Module / heat-spreader combination to the Carrier Board. An independent, implementation specific set of holes and spacers shall be used to attach the heat-spreader to the Module.

All dimensions are shown in millimeters. Tolerances shall be ± 0.25mm [±0.010"], unless noted otherwise. The 440 pin connector pair shall be mounted on the backside of the PCB and is seen “through” the board in this view. The four mounting holes shown shall use 6 mm diameter pads and have 2.7 mm plated holes, for use with 2.5 mm hardware. The pads shall be tied to the PCB ground plane. Modules shall include the 4 mounting holes as shown in Figure 6-1 above. These holes are primarily used to attach the module to the carrier.

The PCB size for the Basic Module shall be 125mm x 95mm. The PCB thickness should be 2mm to allow high layer count stack-ups and facilitate a standard ‘z’ dimension between the Carrier Board and the top of the heat-spreader. (See “Heat-Spreader”). The holes shown in this drawing are intended for mounting the module / heat-spreader combination to the Carrier Board. An independent, implementation specific set of holes and spacers shall be used to attach the heat-spreader to the module.

Module Size — Extended Module

Extended Module Form Factor

All dimensions are shown in millimeters. Tolerances shall be ± 0.25mm [±0.010"], unless noted otherwise. The 440 pin connector pair shall be mounted on the backside of the PCB and is seen “through” the board in this view. The 5 mounting holes shown shall use 6mm diameter pads and shall have 2.7mm plated holes, for use with 2.5mm hardware. The pads shall be tied to the PCB ground plane. Modules shall include the 5 mounting holes as shown in Figure 6-2 above. These holes areprimarily used to attach the module to the carrier.

The PCB size for the Extended Module shall be 155mm x 110mm. The PCB thickness should be 2mm to allow high layer count stack-ups and facilitate a standard ‘z’ dimension between the Carrier Board and the top of the heat-spreader. (See “Heat-Spreader”). The holes shown in this drawing are intended for mounting the module / heat-spreader combination to the Carrier Board. An independent, implementation specific set of holes and spacers shall be used to attach the heat-spreader to the module.

Module Connector

Module Receptacle

All dimensions are shown in millimeters Tolerances shall be ± 0.25mm [±0.010"], unless noted otherwise. The 440 pin connector pair shall be mounted on the backside of the PCB and is seen “through” the board in this view. The seven mounting holes shown shall use 6 mm diameter pads and have 2.7 mm plated holes, for use with 2.5 mm hardware. The pads shall be tied to the PCB ground plane. Modules shall include the 7 mounting holes as shown in Figure 6-3 above. These holes are primarily used to attach the module to the carrier.

The module connector for Pin-out Types 2 through 56 shall be a 440-pin receptacle that is composed of 2 pieces of a 220-pin, 0.5 mm pitch receptacle. The pair of connectors may be held together by a plastic carrier during assembly to allow handling by automated assembly equipment. Module Pin-out Type 1 or 10 shall use a single 220-pin, 0.5 mm pitch receptacle. The connectors shall be qualified for LVDS operation up to 6.25GHz, to support PCI Express Generation 2 signaling speeds. Sources for the individual 220-pin receptacle are AMP / Tyco 3-1318490-6 0.5 mm pitch Free Height 220 pin 4H Receptacle, or equivalent AMP / Tyco 8-1318490-6 0.5 mm pitch Free Height 220 pin 4H Receptacle, or equivalent (same as previous part, but with anti-wicking solution applied) Tyco Electronics 3-6318490-6 Foxconn QT012206-1031-2H or equivalent 0.5 mm pitch Free Height 220 pin 4H Receptacle Source for the combined 440-pin receptacle (composed of 2 pieces of the 220 pin receptacle held by a carrier) are: AMP / Tyco 3-1827231-6 0.5mm pitch Free Height 440 pin 4H Receptacle or equivalent. Tyco Electronics 3-1827231-6 Foxconn QT012206-1041-3H or equivalent 0.5 mm pitch Free Height 440 pin 4H Receptacle Note: the part number above shown with a leading ‘8’ has an anti-wicking solution applied that may help in processing with an aggressive flux. The other versions of the parts may also be made available with this solution by the vendor. The module connector is a receptacle by virtue of the vendor’s technical definition of a receptacle, and to some users it looks like a plug.

Carrier Board Connector

Carrier Board Plug (8-mm Version)

The Carrier Board connector for module Pin-out Types 2 through 56 shall be a 440-pin plug that is composed of 2 pieces of a 220-pin, 0.5 mm pitch plug. The pair of connectors may be held together by a plastic carrier during assembly to allow handling by automated assembly equipment. Carrier Boards intended only for use with Pin-out Type 1 or 10 modules may use a single 220-pin, 0.5 mm pitch plug. The connectors shall be qualified for LVDS operation up to 6.25GHz, to support PCI Express Generation 2 signaling speeds. The Carrier Board plugs are available in a variety of heights. The Carrier Board shall use either the 5mm or 8mm heights. Source for the individual 5 mm stack height 220 pin plug are: AMP / Tyco 3-1827253-6 0.5 mm pitch Free Height 220 pin 5H Plug or equivalent Tyco Electronics 3-1827253-6 Foxconn QT002206-2131-3H or equivalent 0.5 mm pitch Free Height 220 pin 5H Plug Source for the combined 5mm stack height 440-pin plug (composed of 2 pieces of the 220 pin plug held by a carrier) is: AMP / Tyco 3-1827233-6 0.5 mm pitch Free Height 440 pin 5H Plug or equivalent. Tyco Electronics 3-1827233-6 Foxconn QT002206-2141-3H or equivalent 0.5 mm pitch Free Height 440 pin 5H Plug . Source for the individual 8 mm stack height 220 pin plug are: AMP / Tyco 3-1318491-6 0.5 mm pitch Free Height 220 pin 8H Plug or equivalent AMP / Tyco 8-1318491-6 0.5 mm pitch Free Height 220 pin 8H Plug or equivalent (same as previous part, but with anti-wicking solution applied) Tyco Electronics 3-6318491-6 Foxconn QT002206-4131-3H or equivalent 0.5 mm pitch Free Height 220 pin 8H Plug Source for the combined 8 mm stack height 440 pin plug (composed of 2 pieces of the 220 pin plug held by a carrier) is: AMP / Tyco 3-5353652-6 0.5 mm Free Height 440 pin 8H Plug or equivalent. Tyco Electronics 3-5353652-6 Foxconn QT002206-4141-3H or equivalent 0.5 mm Free Height 440 pin 8H Plug . Note: the part number above shown with a leading ‘8’ has an anti-wicking solution applied that may help in processing with an aggressive flux. The other versions of the parts may also be made available with this solution by the vendor. The Carrier Board connector is a plug by virtue of the vendor’s technical definition of a plug, and to some users it looks like a receptacle.

Connector PCB PatternConnector PCB Pattern

All dimensions in mm.Module Connector Pin NumberingPin numbering for 440-pin module receptacle. This is a top view of the receptacle, looking into the receptacle, as mounted on the backside of the module.

Module Connector Pin Numbering

All dimensions in mm.Carrier Board Connector Pin NumberingPin numbering for 440-pin carrier-board plug. This is a top view, looking into the plug as mounted on the Carrier Board.

Carrier Board Connector Pin Numbering

All dimensions in mm.

Electrical SpecificationsInput Power — General Considerations

Input Power — Sequencing

Power Sequencing

The Compact, Basic and Extended Module modules shall use a single main power rail with a nominal value of +12V. Two additional rails are specified: a +5V standby power rail and a +3V battery input to power the module Real-time Clock (RTC) circuit in the absence of other power sources. The +5V standby rail may be left unconnected on the Carrier Board if the standby functions are not required by the application. Likewise, the +3V battery input may be left open if the application does not require the RTC to keep time in the absence of the main and standby sources. There may be module specific concerns regarding storage of system setup parameters that may be affected by the absence of the +5V standby and / or the +3V battery. The rationale for this power-delivery scheme is:• Module pins are scarce. It is more pin-efficient to bring power in on a higher voltage rail. • Single supply operation is attractive to many users.• Lithium ion battery packs for mobile systems are most prevalent with a +14.4V output. This is well suited for the +12V main power rail. • Contemporary chipsets have no power requirements for +5V other than to provide a reference voltage for +5V tolerant inputs. No COM ExpressTM module pins are allocated to accept +5V except for the +5V standby pins. In the case of an ATX supply, the switched (non standby) +5V line would not be used for the COM ExpressTM module, but it might be used elsewhere on the Carrier Board.

Input Power — Basic and Extended ModulesCurrent LoadThe module connector pins limit the amount of power that can be brought into the COM ExpressTM modules. The limits are different for module Pin-out Types 1, and 10 vs. Pin-out Types 2 through 56, based on the number of 12V power pins as Pin-out Types 1 and 10 have fewer pins available.

Input Power — Pin-out Type 1,10 Modules (Single Connector, 220 pins)

Power Rail Module Pin Current Capability (Amps) Nominal Input (Volts) Input Range (Volts)

VCC_12V 10.5 6 12 11.4 - 12.6

VCC_5V_SBY 2 5 4.75 – 5.25 VCC_RTC 0.5 3 2.0 - 3.3

Input Power — Pin-out Type 2,3,4,5,6 Modules (Dual Connector, 440 pins)

Rail Module Pin Current Capability (Amps) Nominal Input (Volts) Input Range (Volts)

VCC_12V 16.512 12 11.4 - 12.6

VCC_5V_SBY 2 5 4.75 – 5.25 VCC_RTC 0.5 3 2.0 - 3.3

COM ExpressTM input power sequencing requirements are as follows:

VCC_RTC shall come up at the same time or before VCC_5V_SBY comes up. VCC_5V_SBY shall come up at the same time or before VCC_12V comes up. PWROK shall be active at the same time or after VCC_12V comes up.

PWROK shall be inactive at the same time or before VCC_12V goes down. VCC_12V shall go down at the same time or before VCC_5V_SBY goes down. VCC_5V_SBY shall go down at the same time or before VCC_RTC goes down.

Power Sequencing

Input Power - Rise Time

Input Power Rise Time

T1 VCC_RTC rise to VCC_5V_SBY rise T2 VCC_5V_SBY rise to VCC_12V rise T3 VCC_12V rise to PWROK rise T4 PWROK fall to VCC_12V fall T5 VCC_12V fall to VCC_5V_SBY fall T6 VCC_5V_SBY fall to VCC_RTC fall

The input voltages to the COM Express module VCC_12V and VCC_5V_SBY if used shall rise from ≤10% of nominal to within the regulation ranges within 0.1 ms to 20 ms (0.1 ms ≤ T2 ≤ 20 ms). There must be a smooth and continuous ramp of each DC output voltage from 10% to 90% of its final set point within the regulation band. The smooth turn-on requires that, during the 10% to 90% portion of the rise time, the slope of the turn-on waveform must be positive and have a value of between 0 V/ms and [Vout, nominal / 0.1] V/ms. Also, for any 5ms segment of the 10% to 90% rise time waveform, a straight line drawn between the end points of the waveform segment must have a slope ≥ [Vout, nominal / 20] V/ms.

Signal Integrity Requirements

T1,min = 0,1msT1,max = 20msT2 ≥ 0msT3 ≥ 0msThe values chosen were selected to be compatible and enable use of ATX specification R2.2

The signal groups listed in the following table have signal-integrity concerns that should be accounted for in module and carrier-board designs. A general description is shown in the table for reference only. The designer should consult the relevant interface specification documents for complete information.

Signal Group General Description Analog VGA 75-ohm single ended ground-referenced lines. Generous isolation recommended. Component and Composite video 75-ohm single ended ground-referenced lines. Generous isolation recommended. Gigabit Ethernet Differential pairs LVDS 100-ohm edge coupled differential pairs PCI Bus Circa 60 ohm single-ended PCI and LPC clocks 50-ohm single ended ground-referenced PCI Express Differential pairs PCI Express clocks 100 ohm edge couple differential pair, ground-referenced Serial ATA Differential pairs USB Differential pairs



Power Sequencing

use a single main power rail with a nominal value of +12V. Two additional rails are specified: a +5V standby power rail and a +3V battery input to power the module Real-time Clock (RTC) circuit in the absence of other power sources. The +5V standby rail may be left unconnected on the

Carrier Board if the standby functions are not required by the application. Likewise, the +3V battery input may be left open if the application does not require the RTC to keep time in the absence of the main and standby sources. be module specific concerns regarding storage of system setup parameters that may be affected by the absence of the +5V standby and / or the +3V battery.

Contemporary chipsets have no power requirements for +5V other than to provide a reference voltage for +5V tolerant inputs. No COM ExpressTM module pins are allocated to accept +5V except for the +5V standby pins. In the case of an ATX supply, the switched (non standby) +5V line would not be used for the COM ExpressTM module, but it might be used elsewhere on the Carrier Board.

The module connector pins limit the amount of power that can be brought into the COM ExpressTM modules. The limits are different for module Pin-out Types 1, and 10 vs. Pin-out Types 2 through 56, based on the number of 12V

(Single Connector, 220 pins)

Derated Input (Volts) Max Input Ripple (mV) Max Module Input Power (w. derated

input) (Watts) Assumed Conversion

Efficiency

11.4 +/- 100 120 68 85%

4.75 +/- 50 9 +/- 20

Modules (Dual Connector, 440 pins)

Derated Input Max Input Ripple Max Module Input Power (w. derated

input) (Watts) Assumed Conversion

Efficiency

11.4 +/- 100 188137 85%

4.75 +/- 50 9 +/- 20

Power Sequencing



rise from ≤10% of nominal to within the regulation ranges within 0.1 ms to 20 ms (0.1 ms ≤ T2 ≤ 20 ms). There must be a smooth and continuous ramp of each DC output voltage from 10% to 90% of its final set point within the regulation band. The smooth turn-on requires that, during the 10% to 90% portion of the rise time, the slope of the turn-on waveform must be positive and have a value of between 0 V/ms and [Vout, nominal / 0.1] V/ms. Also, for any 5ms segment of the 10% to 90% rise time waveform, a straight line drawn between the end points of the waveform segment must have a


The values chosen were selected to be compatible and enable use of ATX specification R2.2

be accounted for in module and carrier-board designs. A general description is shown in the table for reference only. The designer should

General Description Source Spec Reference 75-ohm single ended ground-referenced lines. Generous isolation recommended. 75-ohm single ended ground-referenced lines. Generous isolation recommended.

IEEE 802.3 Specification 100-ohm edge coupled differential pairs National Semiconductor LVDS web site

PCI SIG - PCI Local Bus Spec. Rev. 2.3 50-ohm single ended ground-referenced

PCI SIG - PCI Express Specification 100 ohm edge couple differential pair, ground-referenced

SATA Specification USB 2.0 Specification



Power Sequencing

Two additional rails are specified: a +5V standby power rail and a +3V battery input to power the module Real-time Clock (RTC) circuit in the absence of other power sources. The +5V standby rail may be left unconnected on the be left open if the application does not require the RTC to keep time in the absence of the main and standby sources.

Contemporary chipsets have no power requirements for +5V other than to provide a reference voltage for +5V tolerant inputs. No COM ExpressTM module pins are allocated to accept +5V except for the +5V standby pins.

Pin-out Types 2 through 56, based on the number of 12V

Max Load Power (Watts)

101 58

Max Load Power (Watts)

160116

Power Sequencing



≥0 ms ≥0 ms ≥0 ms ≥0 ms ≥0 ms ≥0 ms

20 ms). There must be a smooth and continuous ramp of each DC output voltage from 10% to 90% of its final set point within the regulation band. The smooth turn-on requires that, during the 10% to 90% portion of the rise time, the slope of the turn-on waveform must be positive and have a value of between 0 V/ms and [Vout, nominal / 0.1] V/ms. Also, for any 5ms segment of the 10% to 90% rise time waveform, a straight line drawn between the end points of the waveform segment must have a


be accounted for in module and carrier-board designs. A general description is shown in the table for reference only. The designer should

Source Spec Reference

National Semiconductor LVDS web site PCI SIG - PCI Local Bus Spec. Rev. 2.3

Environmental SpecificationsThermal SpecificationObjectives

Definitions

Tcase_max Measurement Setup

Tcase_Max Measurement Point

Thermal specification requirements set forth here serve two objectives:1.To provide a method through which any COM ExpressTM module’s thermal performance can be specified and verified against a common reference.2. To provide a method of thermal specification that is independent of the particular components used on the module. These objectives are limited to the modules’ heat-spreader interface, and primary heat sources are limited to the module itself and ambient air.

Tcase. This is the temperature of the outside surface of the module heat-spreader plate. Tcase_max. This is defined as the maximum temperature allowed for the heat-spreader of the module at point M (defined below). This maximum temperature is directly tied to maximum allowed junction temperatures of the chips that are in contact with the heat-spreader Tcase_min. This is defined as the minimum temperature allowed for the heat-spreader of the module. This temperature is directly tied to minimum allowed junction temperatures of the chips that are in contact with the heat-spreader. M. This is defined as the point on the heat-spreader where the maximum case temperature must be measured. The module manufacturer should indicate the location of this point on the module’s heat-spreader and/or in its product documentation. Tambient_max. This is defined as the maximum temperature of the air directly surrounding the module, allowed for the operation of the module. Tambient_min. This is defined as the minimum temperature of the air directly surrounding the module, allowed for the operation of the module. TDPmax. This is defined as the maximum power dissipation of the module for design of a thermal solution to guarantee that the module operates within the manufacturer’s specifications. TDP stands for thermal design power. Tcpu_junction. The junction temperature of the processor. Tcpu_junction can be measured in many processors by accessing an on-die thermal diode. Refer to the manufacturer datasheet for information on how to access the thermal diode. In some instances, software provided by the processor manufacturer or a third party may be used in conjunction with hardware on the module / carrier assembly to monitor the temperature of the processor. Verification of an internal thermal diode accuracy should be done and certified by the OEM. With verified accuracy of the diode, validation with software can then be done by end users. Tcpu_junction_max. The maximum junction temperature for the processor as specified in the silicon manufacturer's datasheet. The module thermal solution (i.e. heat-spreader and heatsink) shall keep the processor junction temperature at or below the Tcpu_junction_max. Note that some manufacturers do not specify maximum junction temperatures but specify maximum case temperatures instead. Tcpu_case. The CPU package case temperature, as specified in the silicon vendor’s data sheet. Note that Tcpu_case and T_case may refer to different locations in the COM ExpressTM module system. Tcpu_case_max. The maximum CPU package case temperature for the processor as specified in the silicon manufacturer's datasheet. The module’s thermal solution (i.e. heat-spreader and heatsink) shall keep the processor case temperature at or below the Tcpu_case_max. Note that some manufacturers do not specify maximum case temperatures but specify maximum junction temperatures instead. The ultimate goal of the system thermal solution is to ensure that Tcpu_junction or Tcpu_case, whichever applies to the CPU at hand, remain below the maximum levels specified by the CPU vendor. Similar concerns apply to other high dissipation components in the module system.

Measurements for Tcase_max should be performed according to a standardized method and under TDPmax conditions. The following figure depicts the standardized measurement setup for Tcase_max measurements.

Module Thermal Specification Requirements

Humidity

Shock and Vibration

This schematic illustration shows the module heat-spreader, the module, and the Carrier Board. Not shown is the user-specific cooling solution that shall attach to the heat-spreader. Modules are not normally operated without a cooling solution attached. The measurement point (M) should be specified, either through a permanent marker on the module’s heat-spreader, or through a mechanical drawing in the product’s support documentation.

A module manufacturer should specify Tcase_max, Tcase_min, Tambient_max, Tambient_min, TDPmax and M (the Tcase_max measurement point). A module manufacturer may specify Tcpu_junction_max and maximum junction temperatures of other critical chips on the module. In this case, the module vendor should provide software to read the junction temperature of the CPU and may do the same for the other critical chips. In that case, the module vendor shall ensure that the software is properly calibrated and that the junction temperature readings are accurate. The efficiency of the module thermal characteristics has an impact on the module’s MTBF (Mean Time Between Failure). Higher junction temperatures result in a shorter silicon life. Module vendors should provide MTBF information.

The module humidity tolerance shall be 0 to 95% humidity, non-condensing.

The shock and vibration characteristics of a system built with a COM ExpressTM module will vary depending on system-implementation details. These details include size, rigidity, and mounting configuration of the Carrier Board and the thermal solution. There is no explicit shock and vibration specification that COM ExpressTM modules are required to meet. If all available COM ExpressTM module and heat-spreader attachment points are used, then a COM ExpressTM based system should be capable of excellent shock and vibration performance.

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