XOR-XNOR gates are investigated in this article, Design Methodologies for High-Performance Noise-Tolerant XOR–XNOR Circuits with Power, Area and Time delay efficiency are considered in the paper. One circuit is chosen and investigated in the articleInitially, basics of XOR-XNOR gate are introduced. After that, XOR circuit is investigated with related characteristics which affect power, area and time delay aspects. Then, different types of noise are investigated. After that effect of abovementioned noises to Input/Output characteristics will be analyzed. Then, possible ways to reduce or eliminate noises through change of circuit will be considered. The last step is improvement of energy and speed efficiency of the circuit. Fifth part of abovementioned content is simulation which is done through the whole project in order to observe circuit’s operation.

Abstract

As integrated circuit technology develops power and area optimization problems have become a crucial issue in the process of circuit design. Due to the fact that XOR-XNOR gate plays essential role in circuit realization it is needed to enhance the circuit in order to achieve lower power dissipation, smaller area and shorter delay.

Introduction

• DesignCircuit given in Figure 2 was constructed in LTSpice software and voltages, width/ length characteristics of MOS Transistors are changed. Moreover, different types of noise are added to the process of the device. After that simulation results are analyzed.

Methods

Input/Output graphs are shown below. It was observed that for AC analysis and noise simulation WEAK HIGH and WEAK LOW regions can occur, They can significantly affect performance of the circuit and with some characteristics overall performance can be completely wrong. Thus, it is important to use appropriate value of capacitances and minimum noise.

Results

Results cont.

XOR-XNOR gates is main aspect which is investigated in this article. One circuit is chosen and investigated with different values of capacitance, W/L values, noises and voltages.

Main focus of the article’s simulation is on AC and DC simulations and changes of voltage, capacitances. The most important part of AC simulation is related to capacitance effect to output: capacitance can affect output and overall performance of the circuit, which should be carefully analyzed.

We would like to express our special thanks of gratitude to Professor Alex James who gave us the golden opportunity to do this wonderful project.Secondly we would also like to thank our parents and friends who helped us a lot in finalizing this project within the limited time frame. We thank our colleagues from Nazarbayev University who provided insight and expertise that greatly assisted the research.

Sanzhar Korganbayev skorganbayev@nu.edu.kz Nurlan Zhakin nzhakin@nu.edu.kz

Conclusion

Acknowledgements

Contact Information

Power, Area and Time Delay Efficiency of XOR-XNOR L

Sanzhar Korganbayev

Nazarbayev University School of Engineering Nurlan Zhakin

Nazarbayev University School of Engineering

Figure 2. Different type of XOR gates

XOR XNOR

Figure 3. Investigated circuit

Figure 1. Main principle

• Research SettingsDC and AC Analysis were done for investigated circuit (Figure 2). Width-Length values are changed with step of 5nm and outputs of XOR-XNOR gates are analyzed. Circuits with lowest noise, power, area parameters will be proposed as variants to improve XOR Logic circuit.• Experimental detailsInitially, Width and Length values are changed for four transistors that are placed near voltage sources. The main detail of the simulation is the fact that changes of W/L characteristics are very difficult to observe in output graph. Thus, main focus of simulation is moved from W/L to AC and DC analysis with noise simulation.

Figure 4. Input output of XNOR Table 1. Figure 4 values

Figure 6 shows simulation for AC analysis with capacitances added to the circuit. Two input DC values are equal and results in high output value. It can be observed, that due to capacitances value of output is increasing in the beginning of simulation from 140 dB to 170 dB. As a result, it is possible to say that some capacitors can result to WEAK LOW or WEAK HIGH values that can affect the whole process of the gate.

Figure 5. I/O of XNOR for higher voltage Table 2. Figure 5 values

Figure 6. AC simulation

time Vin1(V) Vin2(V) V(xnor)

0 0 0 5

1 0 0 5

2 0 0 5

3 5 0 3.5

4 5 0 3.5

5 0 0 5

6 0 5 3.7

7 5 5 4.8

8 5 0 3.5

9 0 0 5

10 0 0 5

time Vin1(V) Vin2(V) V(xnor)

0 0 0 5

1 0 0 5

2 0 0 5

3 5 0 3.5

4 5 0 3.5

5 0 0 5

6 0 5 3.6

7 5 5 5

8 5 0 3.5

9 0 0 5

10 0 0 5

As can be seen from Figure 7, noise changes output: output of the gate is sin wave for HIGH value from 4.3 to 5.0 V approximately. Consequently, if noise amplitude is high enough, output can be WEAK HIGH or WEAK LOW as mentioned for capacitance effect above. As a result, performance of the circuit can be changed too. Thus, it has same effect as capacitance with differences: For capacitance effect is neglected after charging of itFor noise it is observed all time, which is more serious for performance of the device.

Figure 7. Noise simulation