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XRT86L38EVAL User Manual

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XRT86L38EVAL

EVALUATION SYSTEM USER MANUAL


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EVALUATION KIT PART LIST This kit contains the following:

• XRT86L38EVAL Application Board • XRT86L38 GUI Evaluation Software • XRT86L38 420-ball TBGA • XRT86L38EVAL User Manual • XRT86L38 Datasheet

FEATURES

• FPGA Design Which Controls the Framer/LIU and Supports Communication Between the PCI Bridge and the XRT86L38

• PCI Bridge Connector for Easy Connection Through a Standard PC • CD ROM Containing the GUI Software (Executable File) • Line Interface Modules Coupled to the Receiver Inputs and Transmitter Outputs • Power Supply Design Which uses the Supply Voltage From the PCI Bridge • Accessible I/O Interface for Common Laboratory Equipment

SYSTEM CONFIGURATION-LAB SETUP The XRT86L38EVAL application board is setup as a common test circuit. Figure 1 shows a simplified block diagram of the default test configuration.

XC2S200ESpartan IIE(280 I/Os)

XRT86L38T1/E1 Framer /L IU Combo

ADDR[14:0]

DATA[7:0]

ADDR[14:0]

DATA[7:0]

PCI Bridge

Graphical User Interface

Physical Interface

ClockReference

XCF02SP R O M

RJ45

O V E R V O L T A G EPROTECTION

XRT86L38EVAL Board

J T A G

Figure 1 Simplified Block Diagram of the XRT86L38EVAL Application Board


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APPLICATION CIRCUITRY FPGA The XRT86L38EVAL uses an FPGA designed to control the Framer/LIU and support communication between the PCI bridge and the XRT86L38. The FPGA chosen contains enough I/O pins to support all eight channels with one configuration. By default, the FPGA is configured into an FPGA loopback mode, whereby the output pins from the Framer block are internally looped back to the input pins. This allows standard network equipment connected to the physical interface to monitor data integrity through a complete communication path.

XC2S200ESpartan IIE(280 I/Os)

XRT86L38T1/E1 Framer/LIU Combo

PCI Br idge

Figure 2 Simplified Block Diagram of the FPGA Interface

Line Interface Module Internal Impedance The XRT86L38 has the termination impedance inside the LIU. No termination resistors are necessary for the transmit outputs or the receive inputs. This allows the user to have one bill of materials for all three line impedances. Figure 3 is a simplified block diagram of the interface connection.

XRT86L38T1/E1 Framer/LIU Combo

Physical Interface

O V E R V O L T A G EPROTECTION

Figure 3 Simplified Block Diagram of the Interface Connection


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GRAPHICAL USER INTERFACE (GUI) INSTALLATION PROCEDURE

The CD ROM contains the necessary files in order to fully evaluate the XRT86L38 evaluation board. By clicking on the “xrt86l3x evaluation vXXX.exe” file, the GUI will automatically install all components. If properly installed,the GUI can be launched from “C:\Program Files\Exar\XRT86L3X Evaluation Software”. Once the GUI is launched, the user is given a choice to launch the GUI in either T1 or E1 mode.

Selecting will load the T1 FPGA or the E1 FPGA, respectively. The user is then presented with this menu.


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T1 TEST MENU The Test menu contains the necessary GUI for testing Bit-Oriented Signaling, Message-Oriented Signaling, Robbed Bit Signaling and Alarm & PMON Monitoring. In order to test these features, it is necessary to place the device in a Framer Local Loopback or an External Loopback by shorting Ttip/Tring to Rtip/Rring through the RJ45 connectors. Also, one should deselect the FPGA loopback in “General Configuration” from the “Configuration” menu.


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T1 BIT ORIENTED SIGNALING In order to Test BOS, select the desired channel, select a framing format that supports BOS such as ESF and ensure Controller 1 and Data Link Bits are used. Then click Send.


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T1 MESSAGE ORIENTED SIGNALING In order to Test MOS, select a framing format that supports MOS, select a Fill Pattern, select a TSLOT conditioning (note that D/E Timeslot can be used with practically al framing formats) and select a HDLC Controller (Controller 1 must be used when using Data Link Bits). Then click Start which begins the process of checking for received messages. Click Test to send the message.


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T1 SLC96 Test In Order SLC96, ensure the framing format is SLC96, modify the SLC96 message to your liking. Other settings can be left at default. Then click Send. Click Check to check for received messages.


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T1 ROBBED BIT SIGNALING MENU In order to Test RBS, select the desired channel, and then Subchannel (Time Slot) to be configured. Once the desired time slot is selected, the transmit signaling bits can be programmed. This menu is used in conjunction with the “T1 Specific” page from the “General Configuration Menu”.


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ALARM & PMON MONITORING


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E1 TEST MENU The Test menu contains the necessary GUI for testing Message-Oriented Signaling, CAS Signaling and Alarm & PMON Monitoring. In order to test these features, it is necessary to place the device in a Framer Local Loopback or an External Loopback by shorting Ttip/Tring to Rtip/Rring through the RJ45 connectors. Also, one should deselect the FPGA loopback in “General Configuration” from the “Configuration” menu.


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E1 MESSAGE ORIENTED SIGNALING In order to Test MOS, select a framing format that supports MOS, select a Fill Pattern, select a TSLOT conditioning (note that D/E Timeslot can be used with practically al framing formats) and select a HDLC Controller (Controller 1 must be used when using Data Link Bits). Then click Start which begins the process of checking for received messages. Click Test to send the message.


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E1 SIGNALING TEST In order to Test Signaling, select the desired channel, and then Subchannel (Time Slot) to be configured. Once the desired time slot is selected, the transmit signaling bits can be programmed. This menu is used in conjunction with the “E1 Specific” page from the “General Configuration Menu”.


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ALARM & PMON MONITORING

CONFIGURATION MENU The Configuration menu allows the user to provision the device into common modes for the Framer and LIU sections of the combo chip.


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A D 4

L A 3

C 70.1uF

C 10 .1uF

V C C 3 V 3

- S E R R

V C C 3 V 3

AD[31 :0 ]

C L K

L A 5

A D 1 8

A D 3 1

- D E V S E L

V C C 3 V 3

A D 7

R 94.7k

A D 1 7

L A 7

J 1 7 A 1

PCI BR IDGE

B 1B 2B 3B 4B 5B 6B 7B 8B 9B 1 0B 1 1

B 1 4B 1 5B 1 6B 1 7B 1 8B 1 9B 2 0B 2 1B 2 2B 2 3B 2 4B 2 5B 2 6B 2 7B 2 8B 2 9B 3 0B 3 1B 3 2B 3 3B 3 4B 3 5B 3 6B 3 7B 3 8B 3 9B 4 0B 4 1B 4 2B 4 3B 4 4B 4 5B 4 6B 4 7B 4 8B 4 9

B 5 2B 5 3B 5 4B 5 5B 5 6B 5 7B 5 8B 5 9B 6 0B 6 1B 6 2

A 1A 2A 3A 4A 5A 6A 7A 8A 9

A 1 0A 1 1

A 1 4A 1 5A 1 6A 1 7A 1 8A 1 9A 2 0A 2 1A 2 2A 2 3A 2 4A 2 5A 2 6A 2 7A 2 8A 2 9A 3 0A 3 1A 3 2A 3 3A 3 4A 3 5A 3 6A 3 7A 3 8A 3 9A 4 0A 4 1A 4 2A 4 3A 4 4A 4 5A 4 6A 4 7A 4 8A 4 9

A 5 2A 5 3A 5 4A 5 5A 5 6A 5 7A 5 8A 5 9A 6 0A 6 1A 6 2

- D E V S E L

A D 3

C 50.1uF

A D 1 5

R D -

C S n _ 8 6 3 8

A D 2

R 4 4 .7K

-INTA

A D 1 4

V C C 3 V 3

V C C 3 V 3

D 1L E D - 1 2 0 6

21

- IRDY-TRDY

L A 1 4

V C C 3 V 3

A D 1 9

-TRDY

A D 2 8

A D 2 2

- S T O P

V C C 3 V 3

R 8 4.7k

INIT*

- L O C K

- S E R R

L D 3

C 1 10 .1uF

L D 5

+

C 1 4

1 0 u F

A D 9

L D 1

W R -

A D 1 9

V C C 3 V 3

A D S

C 40.1uF

V C C 3 V 3

L A 8

D O N E

P M E -

A D 2 0

L A 9

I D S E L

-RST

A D 5

V C C 3 V 3

- P E R R

A D 1 4

C S n _ F P G A

A D 3 1A D 3 0

A D 2 2

A D 2 8

A D 1 1

I D S E L

DIN

L W _ R

A D 1 6

A D 2 5

LINT

A D 7

L D 4

P R O G R A M *

A D 1 6

A D 1

A D 2 7

R 34 7 k

D O U T

A D 1

- IRDY

LD[7:0 ]

R 64 7 0

- L O C K

A D 2 4

A D 1 5

C 1 00 .1uF

L A 0

A D 2 4

A D 1 3

A D 2 9

C L K

L A 6

- C B E 2

- C B E 3

VIO

L A 1 0

A D 8

V C C 3 V 3

VIO

- C B E 1

L D 2

A D 1 8

A D 1 1

C 80 .1uF

A D 3

V C C 3 V 3

A D 9

A D 3 0

LRST-

A D 2 9

C 30 .1uF

L A 1

A D 5

A D 2 3

R 5 0

C 1 30 .1uF

A D 0

A D 2 1

-RST

V C C 3 V 3

L A 1 3

C 90 .1uF

L A 4

L R D Y n

P A R

A D 8

P M E -

A D 2

A D 1 0

A D 6

Q 1F D N 3 3 5 N

3

12

- INTA

A D 2 7

- C B E 1

R 14.7k

A D 2 5

A D 2 3

- C B E 0

L D 7

U 1PCI9030

1 0 5

1

1 0 6

9 5

1 0 7

9 3

1 0 8

9 2

1 0 9

9 1

1 1 0

9 0

1 1 1

8 9

1 1 4

8 7

1 1 5

8 6

1 1 6

8 4

1 1 8

8 3

1 1 9

8 1

1 2 0

8 0

1 2 1

7 9

1 2 3

7 7

1 2 4

7 4

1 2 5

7 3

1 2 7

7 2

1 2 8

6 9

1 2 9

6 8

1 3 0

6 7

1 3 1

6 56 46 3

13

1 7 31 7 41 7 5

23

31

45

91 0

44

32

1 7 2

1 7 0

1 7 1

2 0

2 2

66

45

2 1

2 4

8

2 3

2 62 7

78

56

71 92 94 0

2 8

88

1 61 71 83 03 33 4

101

70

3 53 63 73 83 94 1

113

4 24 34 64 74 84 95 0

122

85 100

1 4 2

6 05 95 85 5

117

1 3 8

1 3 9

133

1 5 81 6 01 6 11 5 9

1 0 41 0 29 99 89 79 6

8 2

6 26 1

14

6

1 11 21 5

57

1 4 4

1 4 8

1 5 4

2 5

1 5 2

7 6

1 4 5

1 5 1

1 4 3

1 5 0

1 1 2

1 5 3

7 5

1 4 11 4 0

1 4 9

1 4 7

1 5 5

1 5 61 5 7

7 1

1 6 41 6 51 6 61 6 71 6 8

132

146

163

176

1 3 41 3 51 3 61 3 7

9 4

1 6 9

1 2 65 1

53

5 2

1 0 35 4

162

L A 2

VD

D

L A 3

L A D 6

L A 4

L A D 7

L A 5

L A D 8

L A 6

L A D 9

L A 7

L A D 1 0

L A 8

L A D 1 1

L A 9

L A D 1 2

L A 1 0

L A D 1 3

L A 1 1

L A D 1 4

L A 1 2

L A D 1 5

L A 1 3

L A D 1 7

L A 1 4

L A D 1 8

L A 1 5

L A D 1 9

L A 1 6

L A D 2 0

L A 1 7

L A D 2 1

L A 1 8

L A D 2 2

L A 1 9

L A D 2 3

L A 2 0

L A D 2 4

L A 2 1

L A D 2 5

L A 2 2

L A D 2 6

L A 2 3

L A D 2 7L A D 2 8L A D 2 9

VS

S

A D 3 1A D 3 0A D 2 9A D 2 8A D 2 7

VS

S

A D 2 6A D 2 5

A D 2 3A D 2 2

VS

S

VD

D

C L K

INTA#

R S T #

F R A M E #

T R D Y #

VS

S

VD

D

I RDY#

S T O P #

I D S E L

D E V S E L #

P E R R #S E R R #

VS

S

VD

D

C / B E 3 #C / B E 2 #C / B E 1 #C / B E 0 #

P A R

VS

S

A D 1 8A D 1 7A D 1 6A D 1 5A D 1 4A D 1 3

VS

SV

DD

A D 1 2A D 1 1A D 1 0A D 9A D 8A D 7

VS

S

A D 6A D 5A D 4A D 3A D 2A D 1A D 0

VS

SV

DD

VD

D

L W / R #

L B E 0 #L B E 1 #L B E 2 #L B E 3 #

VD

D

A D S #

B L A S T #

VD

D

E E C SE E S KE E D IE E D O

L A D 0L A D 1L A D 2L A D 3L A D 4L A D 5

L A D 1 6

L A D 3 0L A D 3 1

VD

D

A D 2 4

A D 2 1A D 2 0A D 1 9

VS

S

B T E R M #

C S 1 #

G P 0

L O C K #

LINTI1

M O D E

L C L K

L R E Q

LRDYI#

L G N T

TEST

LINTI2

A L E

R D #W R #

L R S T #

C S 0 #

G P 1

C S 2 #C S 3 #

B C L K O

TRST#T C KT M ST D OTDI

VS

SV

SS

VS

SV

SS

G P 7G P 6G P 5G P 4

G P 8

P M E #

LPMIn t#E N U M #

VIO

L E D o n #

L P M E S e tC P C I S W

VD

D

C 1 60 .01uF

C 1 20 .1uF

A D 1 2

R 24 7 k

A D 1 7

C 20 .1uF

L A 1 1A D 4

V C C 3 V 3

V C C 3 V 3

- C B E 0

A L E

P A R

R 74.7k

C 60 .1uF

L A 1 2

A D 2 6

L A 2

A D 2 6 L D 0

- F R A M E

C 1 50 .1uF

V C C 3 V 3

LA[14 :0 ]

- S T O P

- C B E 2

A D 6

A D 0

A D 1 3

A D 2 0A D 2 1

U 2

9 3 C S 6 6

1234

8

7

6

5

C SS KDI

D O

V C C

P R E

P E

G N D

L A 1

L D 6

C C L K

L C L K

- F R A M E

- C B E 3

L A 0

A D 1 2

V C C 3 V 3

- P E R R

A D 1 0

Figure 4 XRT86L38EVAL PCI Bridge (Schematic Page 1)


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LA[14:0]

T E S T M O D E

T P 2

1T

PACK0

D O U T

pDBEN

U6

65.536MHz

8

1

5

4

VDD

O E

O U T

G N D

PCLK

LA5

MCLKIN

PACK0

T P 81

LD4

T1SCLK

LA12

LD[7:0]

TDI

TP111

T P 3

1T

ALE

LA8

LA1

VCC3V3

LA3

U4

5.6MHz

8

1

5

4

VDD

O E

O U T

G N D

LA5

GPIO_0

DIN

LA6C18

0.1UF

pTYPE2

VCC3V3

T 1 O S C C L K

VCC3V3

LA0

LA11

LRST-

LA9

GPIO_2

LD7

GPIO1_3

PREQ1

D O N E

VCC3V3

T X O N

8KEXTOSC

tALE

GPIO1_1GPIO1_2

SPARTAN IIE

RD-

tRD

R12

10

CCLK

GPIO1_3

GPIO1_1

H1

JTAG

135

246

+++

+++

tRD

R13 4.7K

T P 4

1T

LD3

a T E S T M O D E

T1SCLK

GPIO_2

8KEXTOSC

5.6MHz

R14 O P E N

GPIO1_0

T P 1

1T

ADS

LA1

pTYPE0

LD6

T P 91

LA0

E1OSCCLK

LINT

LA[14:0]

tALE

MCLKIN

INIT*

TP121

VCC3V3

LD4

LA7

pTYPE0

R19 4.7K

PREQ1

a T E S T M O D E

E1OSCCLK

LD0

R10

10

CSn_8638

LA10

R18 4.7K

tCSR16 300

GPIO_3

R11

10

TP14

1T

R15 O P E N

M C L K O U T n T 1

LD2

PROGRAM*

BLASTn

T P 5

1T

LA6

GPIO_0C17

0.1UF

LA13

LA2

T M SLA8

T E S T M O D E

LA7

LA4

TP17

1T

LA3

5.6MHz

XC2S200E INTERFACE

CSn_FPGA

GPIO_1

PREQ0

R17 O P E N

M C L K O U T n E 1

E1SCLK

PACK1

LA4TP10

1

LA14

tWR

LA10

XRT86L38

LD3

JTAG_RINGT 1 O S C C L K

LA11

T P 6

1T

pTYPE1

pTYPE1

PCLK

tWR

TP15

1T

LD1

T C K

TP16

1T

LA13

U3F

Y17AA17

Y16W16V16

AA16

M18M21M20N17N18N20

Y19AA19

AB19W18

P18

M19

AB18

Y22V19

P22Y18P21

AA3W17

T21T20T18T19

R21R22R18R19

V20V22U22U20U18U19

N19P17

P19N21

L21

L20L18

AA12AB12

D14C14B14A14E13

A21C19

E6E4

AB20AA20

AA1U5

AB2

W20

Y21W21

C22C21B22

V17

AB17L17K22K21D13C13B13

A11C11

G5G4G3G2G1H3

T X O NLOP

8KEXTOSCT 1 O S C C L KE1OSCCLK

8KHZSYNC

GPIO_0GPIO_1GPIO_2GPIO_3

GPIO1_0GPIO1_1

PREQ1PREQ0

PACK1PACK0

CSn_86L38

BLASTn

pTYPE0

DATA0DATA1

C SR DW R

pTYPE2pTYPE1

ADDR0ADDR1ADDR2ADDR3ADDR4ADDR5ADDR6ADDR7

DATA2DATA3DATA4DATA5DATA6DATA7

GPIO1_2GPIO1_3

T E S T M O D Ea T E S T M O D E

MCLKIN

M C L K O U T n E 1M C L K O U T n T 1

T1SCLKE1SCLK

SCKSCSSDIS R S TS D O

T D OTDIT C KT M S

ADSL W _ R

M 0M 1M 2

D O N E

PROGRAMINIT

DIND O U TCCLK

pDBEN

ADDR8ADDR9ADDR10ADDR11ADDR12ADDR13ADDR14

5.6MHzLCLK

ALEtALEtWRtRD

PCLKtCS

LD6

WR-

ANALOG

GPIO_1

U7F

F5D4

G5N4P5U5W 3W 4W 5V5V4

Y3AB1

Y4

AA2AC1Y5

AB3

AF1AA3AA4AA5

AD11AD13AB18AD20AE22AE24

AA24AB26

Y24Y23

AA26W22

W23

Y25

Y26W24

L26R22W25M23

R25W26

V23V24

V25V26U22U23U24U25U26T22

T25T26P24N25N24M25

T24R23R24P22P25

N22N23

R26

P23

G22B21

E22D23B23E19B18E16

B11

A7

B7A5

D7B6

E7

A4

B5D6

E6

C5

D5C4B3E5

JTAG_TIPJTAG_RING

N CN CN CN CN CN CN CN CN C

T X O NLOP

R E S E T

8KEXTOSCT 1 O S C C L KE1OSCCLK

8KHZSYNC

N CN CN CN C

GPIO_0GPIO_1GPIO_2GPIO_3

GPIO1_0GPIO1_1

PREQ1PREQ0

PACK1PACK0

ful lADDRindirectADDR

pTYPE0

PCLK

pDATA0pDATA1

pCSpASpRDp W R

pTYPE2pTYPE1

pDBENpDACK1

pADDR0pADDR1pADDR2pADDR3pADDR4pADDR5pADDR6pADDR7

pDATA2pDATA3pDATA4pDATA5pDATA6pDATA7

pADDR8pADDR9pADDR10pADDR11pADDR12

pADDR14pADDR13

pINT

pBLAST

GPIO1_2GPIO1_3

N CN CN CN CN CN C

T E S T M O D E

T C K

T R S TT M S

TDIT D O

a T E S T M O D E

MCLKIN

M C L K O U T n E 1M C L K O U T n T 1

N C

ANALOG

N CN CN CN C

L W _ R

LCLK

8KHZSYNC

pDBEN

tCS

LA2

JTAG_TIP

C19

0.1UF

LD0

BLASTn

LD7

T P 7

1T

LA14

LRST-

GPIO1_2

GPIO1_0

LD5

U5

49.408MHz

8

1

5

4

VDD

O E

O U T

G N D

LD[7:0]

E1SCLK

M C L K O U T n T 1

LA12

CSn_8638

LOP

pTYPE2

PREQ0

8KHZSYNC

LA9

LD5

T X O N

VCC3V3

PACK1

TP13

1T

M C L K O U T n E 1

LOP

T D O

LD1

LRDYn

LD2

GPIO_3

Figure 5 XRT86L38EVAL FPGA Control (Schematic Page 2)


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R X S E R 2

R X S E R C L K 0

R X C H C L K 7

TXSERCLK4

R X O H 6

J2

R J 4 5

12345678 9

10

TXSYNC4

RXSYNC6

R X S E R 1

TTIP7

R X C H N 7 _ 2

TTIP5

RXSYNC1

R X O H 7

C22 0.

1uF

R X O H C L K 6 TXSERCLK3

TXSER5

R X S E R C L K 4

R X C H N 7 _ 0

R X C R C S Y N C 7

R X C R C S Y N C 6

RXSYNC7

RXSYNC4

RXSYNC2

XC2S200E NETWORK DATA[7:6]R X S E R C L K 5

R X S E R 2

T X C H N 7 _ 3 C 2 1 0.68uF

TXSYNC2

T X C H N 7 _ 1

TXSERCLK6

R X S E R C L K 2

R X S E R 0

R X L O S 6

R X S E R 7

R X S E R C L K 7

R X S E R C L K 6

T X O H C L K 7

U 3 B

V15W 1 5Y15AA15V14U 1 4W 1 4W 5AB15AA14AB14U 1 3

V13W 1 3AA13AB13U 1 2V12Y12AB11Y11W 1 1V11U 1 0V10

Y10W 1 0AA10U 9V9Y9W 9AB10AA9AB9W 8V8

AA8AB8W 7V7AA5AA7AB7W 6V6AA6AB6AB5AB3

T X O H 7T X O H C L K 7T X C H C L K 7

TXSERCLK7TXSER7

T X C H N 7 _ 4T X C H N 7 _ 3T X C H N 7 _ 2T X C H N 7 _ 1T X C H N 7 _ 0TXSYNC7

TXMSYNC7

R X O H 7R X O H C L K 7R X C H C L K 7

R X S E R C L K 7R X S E R 7

R X C H N 7 _ 4R X C H N 7 _ 3R X C H N 7 _ 2R X C H N 7 _ 1R X C H N 7 _ 0RXSYNC7

R X C R C S Y N C 7R X C A S Y N C 7


TXSERCLK6TXSER6


TXMSYNC6





RXSYNC6

J1

R J 4 5

12345678 9

10

TRING7

TXSER1

R X S E R 3

R X S E R 4

RTIP4

T X C H N 6 _ 1

R X O H C L K 7

TXSER4

TXSER5

TXSER0

R X C A S Y N C 7

R X C H N 6 _ 0

RXSYNC5

TTIP6

R X S E R C L K 0

TXSYNC1

R X C H N 6 _ 2

TXSYNC3

RTIP5

RXSYNC7

TXSYNC5

TXSERCLK0TXSERCLK0

T X C H C L K 7

R X S E R C L K 6

QUAD TRANSFORMER FOR CHANNELS [7:4]

TXSERCLK7

RXSYNC0

T X C H N 6 _ 2

T X O H C L K 6

TXSYNC6

XRT86L38TXSERCLK6

TXSYNC4

TXSER1

T X C H N 7 _ 2

TXSYNC2

TXSERCLK1

J4

R J 4 5

12345678 9

10

R R I N G 5

TXSERCLK2

TXSERCLK4

RXSYNC4

C 2 0 0.68uF

R X C H N 6 _ 4

RXSYNC0R X S E R 4

TXSER0

R X C H N 7 _ 3

R X S E R C L K 1

TXSER6

C25 0.

1uF

H 2

123

TXSER3

TXSER6

TRING5

R X C A S Y N C 6

TXSYNC5

T X C H N 7 _ 0

R X S E R C L K 2

R X S E R C L K 1

R X C H N 6 _ 1


TXSYNC7

R X S E R 5

R X C H N 7 _ 4

RXSYNC1

R X S E R 0

TXSERCLK5

TXSYNC1

R X S E R 6

TXMSYNC7

TXSER4

R X C H N 6 _ 3

C23 0.

1uF

RT IP7

R X S E R 7

TXMSYNC6

TXSERCLK2

R R I N G 7

R R I N G 6

T X C H N 6 _ 0

T X C H N 6 _ 4

TXSERCLK7

RXSYNC3

T X C H C L K 6

R X S E R C L K 7

TXSER7

C24 0.

1uF

TXSERCLK5RXSYNC2

TXSYNC3

J3

R J 4 5

12345678 9

10

R X C H N 7 _ 1

R X L O S 7

TXSYNC7

U 7 B

U 3U 4

V1W 1

A C 2AE1AB2AB5AE3AB4A C 3A D 2A D 3A C 5AE4AF2

AF7AE7AF5AB6AB7AF3AE5AF4A C 7AB8A C 6A D 5AF6

A D 4

AF10AC10AD10

AE6AB9AE8AF8AE9AF9

AB10A D 8A C 8

AE14AE13AE11AB12AE12AF11AD12AF12AB13AC13AB11AE10A C 9

T3R 4

T1U 1

AC12

TTIP7TRING7

RTIP7R R I N G 7

T X O H 7T X O H C L K 7T X C H C L K 7TXSERCLK7TXSER7T X C H N 7 _ 4T X C H N 7 _ 3T X C H N 7 _ 2T X C H N 7 _ 1T X C H N 7 _ 0TXSYNC7TXMSYNC7

R X O H 7R X O H C L K 7R X C H C L K 7R X S E R C L K 7R X S E R 7R X C H N 7 _ 4R X C H N 7 _ 3R X C H N 7 _ 2R X C H N 7 _ 1R X C H N 7 _ 0RXSYNC7R X C R C S Y N C 7R X C A S Y N C 7

R X L O S 7



TTIP6TRING6

RTIP6R R I N G 6

R X L O S 6

TTIP4

TXSER2

R X S E R C L K 4

TXSER3

T X O H 7

TRING4

RXSYNC5

TXSYNC0

SPARTAN IIE

R X S E R 6

T X O H 6

R R I N G 4

TXSERCLK3R X C H C L K 6

R X S E R C L K 3

TXSYNC6

TXSER2

T1

S M D 4 0 8

1

4

2

35

6

9

7

810

11

14

12

1315

16

19

17

1820

21

2223

24

2526

2728

29

3031

3233

34

3536

3738

39

40TTP1

R X C T 1

TRP1

RTP1R R P 1

TTP2

R X C T 2

TRP2

RTP2R R P 2

TTP3

R X C T 3

TRP3

RTP3R R P 3

TTP4

R X C T 4

TRP4

RTP4R R P 4

R R S 4

RTS4TRS4

N C

TTS4R R S 3

RTS3T R S

N C

TTS3R R S 2

RTS2TRS2

N C

TTS2R R S 1

RTS1TRS1

N C

TTS1

TXSER7

TXSYNC0

TRING6

S1

HEADER 25x2

12345678910

11121314151617181920212223242526272829303132333435363738394041424344454647484950

T X C H N 7 _ 4

R X S E R C L K 5

TXSERCLK1

R X S E R 5R X S E R 1

RTIP6

RXSYNC3

T X C H N 6 _ 3

Figure 6 XRT86L38EVAL FPGA Channel Control (Schematic Page 3)


of 23

RXCHN5_1

RXOH4

RXSER5

RRING4

C27 0.68uF

RXOHCLK4

SPARTAN IIE

RXSYNC4

C26 0.68uF

RXSYNC5

RXCHCLK4

RXCASYNC4

TXCHN4_2

TXSERCLK4

RXOH5

RXCHN4_0RXCHN4_1

RRING5

TXCHN5_3

RXCRCSYNC4

RXSERCLK5

TXSERCLK4

TRING4TTIP4

RXSER5

TXSERCLK5

TXOHCLK5

RXSYNC5

RXCHN5_3

RXSYNC4

RXSYNC4

RXSYNC5

RXCHN5_2

TXCHN4_4

H3

123

TXCHN5_1

TRING5

TXSYNC4

RXCHCLK5

TXMSYNC4

RXSERCLK4

XC2S200E FRAMER BLOCK[5:4]

RXOHCLK5

TXSYNC4

U7C

P3P4

P1R1

M3M4

M1N1

AF20AC26

AD14AB16AE16AF15AB15AC14AB14AE15AD15AC15AF16AD16

AE17AF17AE21AC19AC18AD17AC17AB17AF18AD18AF19AF21AE19

AF25AF23AD22AE23AB21AD19AE20AC20AF22AD21AF24AC21

AA22Y22

AB24AD26AC25AB22AC23AF26AE25AD25AE26AB25AD24

TTIP5TRING5

RTIP5RRING5

TTIP4TRING4

RTIP4RRING4

RXLOS5RXLOS4

TXOH5TXOHCLK5TXCHCLK5TXSERCLK5TXSER5TXCHN5_4TXCHN5_3TXCHN5_2TXCHN5_1TXCHN5_0TXSYNC5TXMSYNC5

RXOH5RXOHCLK5RXCHCLK5RXSERCLK5RXSER5RXCHN5_4RXCHN5_3RXCHN5_2RXCHN5_1RXCHN5_0RXSYNC5RXCRCSYNC5RXCASYNC5



TXSERCLK5

RXSER4

RXCASYNC5

TXCHN4_3

RTIP5

RXSER4

TXSER5

TXSYNC5

RXSER5

RXSER4

RXCHN5_0

TXSYNC4

U3C

W 2V2W 1U4U3U2U1T1T5T4T3T2

R5R3R2P6P5P4P3R1P2P1N6N5N4

N3N2M6M5M4M3M1L6L5L2L3L1

K1K4K3K6K5J1J2J3J5J4J6H1H2

TXOH5TXOHCLK5TXCHCLK5

TXSERCLK5TXSER5

TXCHN5_4TXCHN5_3TXCHN5_2TXCHN5_1TXCHN5_0TXSYNC5

TXMSYNC5

RXOH5RXOHCLK5RXCHCLK5

RXSERCLK5RXSER5

RXCHN5_4RXCHN5_3RXCHN5_2RXCHN5_1RXCHN5_0RXSYNC5

RXCRCSYNC5RXCASYNC5


TXSERCLK4TXSER4


TXMSYNC4


RXSERCLK4RXSER4


RXCRCSYNC4RXCASYNC4

TXSER5

TXCHN5_2

RXSERCLK5

TXCHN5_4

RXSERCLK4 RXSERCLK4

TXSYNC5

RXCHN4_2

TXCHN5_0

TXMSYNC5

RXCRCSYNC5

XRT86L38TXSER4

TXCHCLK4

TXSYNC5

TXSERCLK4

RXCHN4_4

TXSER4TXSER4

TXCHN4_1

RXCHN4_3

RTIP4

TTIP5

RXCHN5_4

RXLOS5RXLOS4

TXSERCLK5

TXCHCLK5

TXCHN4_0

TXSER5

RXSERCLK5

TXOH4

TXOH5

TXOHCLK4



of 24

TTIP1

R R I N G 1

R R I N G 3

R X S E R C L K 2

R X C H N 3 _ 1

RXSYNC2

R X O H 2

TXSERCLK3

RTIP1

TXSYNC3

T X O H 3

R X O H C L K 3

TXSYNC3

R X S E R 2

R X C H N 2 _ 0

C33 0.

1uF

SPARTAN IIE

R X C H N 3 _ 2

T2

S M D 4 0 8

1

4

2

35

6

9

7

810

11

14

12

1315

16

19

17

1820

21

2223

24

2526

2728

29

3031

3233

34

3536

3738

39

40TTP1

R X C T 1

TRP1

RTP1R R P 1

TTP2

R X C T 2

TRP2

RTP2R R P 2

TTP3

R X C T 3

TRP3

RTP3R R P 3

TTP4

R X C T 4

TRP4

RTP4R R P 4

R R S 4

RTS4TRS4

N C

TTS4R R S 3

RTS3T R S

N C

TTS3R R S 2

RTS2TRS2

N C

TTS2R R S 1

RTS1TRS1

N C

TTS1

TRING0

T X C H N 2 _ 3

TXSER2

R X C H N 2 _ 3

TXSERCLK3

R X C H N 2 _ 4R X S E R 2 TXSYNC2

T X C H N 3 _ 3

U 3 D

F2F3F4F5E3E2D 1D 2C 1D 3D 5B3

A3A4C 5B4B5A5C 6B6A6E7E8D 7C 7

B7D 8C 8B8A8E9F9D 9C 9E10B9A9

F10D 1 0C 1 0B10A10F11B11A12E12D 1 2B12C 1 2A13


TXSERCLK3TXSER3


TXMSYNC3






TXSERCLK2TXSER2


TXMSYNC2





T X C H N 2 _ 2

R X C H N 3 _ 0

C30 0.

1uF

TTIP3C 2 8 0.68uF

R X L O S 3

RXSYNC3

R X S E R C L K 3

RTIP2

TXMSYNC3


T X O H C L K 3

T X C H N 3 _ 2

RTIP0

RTIP3

TTIP2

R X C R C S Y N C 2

TXSYNC2

R X S E R 3

H 4

123

T X O H C L K 2

TRING1

R X C H N 3 _ 3

R X C H C L K 3

R X C H N 3 _ 4

C31 0.

1uF

TR ING2

J7

R J 4 5

12345678 9

10

R X C A S Y N C 2

TXSER2

R X O H 3

T X C H N 3 _ 1

TXSERCLK3

T X C H N 3 _ 4

TXSYNC2

R X C H C L K 2R X S E R 3

T X C H N 2 _ 1

C32 0.

1uF

TXSER2

TXSERCLK2

TRING3

R R I N G 0

T X O H 2

TXSER3

T X C H N 2 _ 0

R X C H N 2 _ 1

U 7 D

J25K23J22K24K26M 2 6M 2 4M 2 2L25L22K22L24

F26G 2 4F25H 2 5D 2 6K25J26J23H 2 6G 2 6G 2 3G 2 5H 2 3

E26E24B26D 2 2E23E25F23C 2 6D 2 5F22B24C 2 4

D 2 1E21A24C 2 0C 2 1A26C 2 3C 2 2B22A22D 1 9E20A23

K3L4

K1L1

J3K4

H 1J1

H 2 4B20





TTIP3TRING3

RTIP3R R I N G 3

TTIP2TRING2

RTIP2R R I N G 2

R X L O S 3R X L O S 2

J6

R J 4 5

12345678 9

10

TXSYNC3

R R I N G 2

R X L O S 2

TXSERCLK2

R X C A S Y N C 3R X C R C S Y N C 3

QUAD TRANSFORMER FOR CHANNELS [3:0]

RXSYNC3

R X S E R 3

T X C H C L K 3

R X S E R 2

T X C H N 2 _ 4

RXSYNC2

TTIP0

T X C H N 3 _ 0

XRT86L38

RXSYNC3

J5

R J 4 5

12345678 9

10

TXSER3TXMSYNC2

T X C H C L K 2

J8

R J 4 5

12345678 9

10

R X S E R C L K 2

R X S E R C L K 3

TXSERCLK2

R X C H N 2 _ 2

TXSER3

C 2 9 0.68uF

R X S E R C L K 2

RXSYNC2

R X S E R C L K 3

R X O H C L K 2



of 25

TXCHN1_4

RXSER1

RXSER1

RXLOS0RXCHCLK1

TXSER1

TXSER0

TXSYNC1

TXSERCLK1

RXSYNC1

TXSER0RXOHCLK0

RXCHN1_2

TXMSYNC1

RXCHN1_3

RXCASYNC1

TRING1

RXOH0

TXCHN0_0

TXCHN0_4

RXCHN0_0

TXOH1

TXSYNC0

RXSERCLK1

TXOH0

TXMSYNC0

SPARTAN IIE

TXCHCLK1

C35 0.68uF

TXOHCLK1

TXSERCLK1

TXSYNC1

RXSER0

TXSERCLK1

RXCHN1_0

H5

123

TXCHN0_2

RXSYNC0

C34 0.68uF

TXCHN1_0

RXSERCLK0

RXSER1

TTIP0

RXSER0RXSERCLK0

RXSYNC0

TXSERCLK0

RXCHN0_3

TXCHN0_3

RTIP0

RXSYNC1

TXSYNC1

RXCHN0_4

RXOH1

RXCHCLK0 RXSERCLK0

TXCHN0_1

TXSYNC0

TXSER1

RXCHN1_1

TXSER0

RXCRCSYNC1


TTIP1

U3E

E14A15B15C15D15A16B16C16D16E15E17E16

A17B17C17A18B18A19B19C18A20B20E19E20D21

D22F19F20E21F21E22G18G19G20G21F22H18

H19H20H21J17J18H22J19J20J21J22K17K18K19


TXSERCLK1TXSER1


TXMSYNC1


RXSERCLK1RXSER1


RXCRCSYNC1RXCASYNC1


TXSERCLK0TXSER0


TXMSYNC0


RXSERCLK0RXSER0


RXCRCSYNC0RXCASYNC0

RRING1

RXCHN0_1

RXCRCSYNC0RXCASYNC0

RXCHN1_4

TXSERCLK0

RXCHN0_2

TXSER1

TXSERCLK0TXCHCLK0

TRING0

RRING0

TXCHN1_3

RXSERCLK1

TXSYNC0

RTIP1

RXLOS1

TXCHN1_1

RXSYNC0

TXOHCLK0

U7E

A18A19E17C19D17A21A20B19D18C18C16A17

B15D16A14B13B14C17B16A15E14D14D15D13E15

C12E11A12A11D11C14E13A13B12D12

A9B10

C11B9A8A6C7

A10C10

C9E9D8D9B8

E10

G3H4

F1G1

F3G4

D1E1

A16E8





TTIP1TRING1

RTIP1RRING1

TTIP0TRING0

RTIP0RRING0

RXLOS1RXLOS0

RXSER0

RXSERCLK1

XRT86L38

RXOHCLK1

TXCHN1_2

RXSYNC1



of 26

L3

C50

0.1uF

VCC1V8

VDD

R2050

U3A

XC2S200E POWER

E5E18

F6F17G7G8

G15G16

H7H16

R7R16

T7T8

T15T16U6

U17V5

V18

F7F8G9

G10F15F16G13G14G17H17J16K16N16P16R17T17T13T14U15U16

T9T10U7U8N7P7R6T6G6H6J7K7

A1A22B2B21C3C20G11G12J9J10J11J12J13J14K9K10K11K12K13K14L7L9L10L11L12L13L14L16M7M9M10M11M12M13M14M16N9N10N11N12N13N14P9P10P11P12P13P14T11T12

Y3Y20

AA2AA21

AB1AB22

VCCiVCCiVCCiVCCiVCCiVCCiVCCiVCCiVCCiVCCiVCCiVCCiVCCiVCCiVCCiVCCiVCCiVCCiVCCiVCCi

VCCoVCCoVCCoVCCoVCCoVCCoVCCoVCCoVCCoVCCoVCCoVCCoVCCoVCCoVCCoVCCoVCCoVCCoVCCoVCCoVCCoVCCoVCCoVCCoVCCoVCCoVCCoVCCoVCCoVCCoVCCoVCCo

GNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGND

GNDGND

GNDGND

GNDGND

C82

0.1uF

+C36

10uF

FPGA BYPASS CAPACITORS

AVDD

C54

0.1uF

C92

0.1uF

VCC1V8

C38

0.1uF

VCC3V3

C55

0.1uF

C65

0.1uF

C860.1uF

C40

0.1uF

C45

0.1uF

L2

VDD1V8

C81

0.1uF

C56

0.1uF

C63

0.1uF

C89

0.1uF

VDD1V8

C64

0.1uF

C67

0.1uF

RVDD

C41

0.1uF

TP23

1T

C69

0.1uF

C44

0.1uF

C97

0.1uF

VCC3V3

J9

JUMPER

123RVDD

+C83

100uF

+C66

10uF

C95

0.1uF

C39

0.1uF

C53

0.1uF

C52

0.1uF

VCC3V3

C90

0.1uF

FPGA BYPASS CAPACITORS

C47

0.1uF

C49

0.1uF

+C57

10uF

D24.3V

21

C85

0.1uF

C68

0.1uF

C91

0.1uF

+C88

10uF

TP19

1T

C96

0.1uF

VCC1V8

L1

VDD

C62

0.1uF

TVDD

C93

0.1uF

TP21

1T

U7A

XRT86L38

Y1 AA1

AE2

AD6

AD9

AF13

AC16

AB19

AC22

AB23

AA23

V22

P26

L23

H22

C25

B25

D20

B17

C13

D10

C6

Y2AD1

AC4

AD7

AC11

AF14

AE18

AB20

AD23

AC24

AA25

T23

N26

J24

F24

A25

E18

C15

E12

C8 A1 B4

A2 A3

F4 H3 J4 L3 N3 R3 T4 V3 D2 F2 H2 K2 M2 P2 T2 V2 D3 C2 B1 C1

E3 E4 B2 C3H5 J5 K5 L5 M5 N5 R5 T5 E2 G2 J2 L2 N2 R2 U2 W2

D24

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VDD

VDD1

8

VDD

VDD1

8

VDD

VDD1

8

VDD

VDD1

8

VDD

VDD1

8

VDD

VDD1

8

VDD

VDD1

8

VDD

VDD

VDD1

8

VDD

VDD1

8

VDD

DVDD

AVDD

DGND

AGND

TVDD

TVDD

TVDD

TVDD

TVDD

TVDD

TVDD

TVDD

RVDD

RVDD

RVDD

RVDD

RVDD

RVDD

RVDD

RVDD

VDDP

LL11

VDDP

LL12

VDDP

LL21

VDDP

LL22

GNDP

LL11

GNDP

LL12

GNDP

LL21

GNDP

LL22

TGND

TGND

TGND

TGND

TGND

TGND

TGND

TGND

RGND

RGND

RGND

RGND

RGND

RGND

RGND

RGND

VDD1

8

VCC1V8

+C72

10uF

C80

0.1uF

FRAMER BYPASS CAPACITORS

VDD

C98

0.1uF

C84

0.1uF

C79

0.1uF

C59

0.1uF

C61

0.1uF

TP22

1T

C94

0.1uF

C46

0.1uF

C37

0.1uF

+ C8710uF

TP18

1T

L5

U8

REG103A

5 1

3

2

46

VIN VOUT

GND ADJ

ENAB

LEGN

D

C43

0.1uF

C71

0.1uF

TVDD

TP20

1T

C58

0.1uF

+C48

10uF

C74

0.1uF

C73

0.1uF

C76

0.1uF

C78

0.1uF

C60

0.1uF

L4

+C42

10uF

C75

0.1uF

C51

0.1uF

AVDD

R21130

C77

0.1uF

C70

0.1uF

SPARTAN IIE

Figure 10 XRT86L38EVAL Power Supply Design (Schematic Page 7)


of 27

Layout Recommendations RTIP/RRING Traces (Long Haul Applications) The most critical traces are those routed for the receiver inputs in Long Haul applications, where the input may be attenuated up to –42dB of cable loss. The differential pair of each channel should be isolated from other signals on the PCB to prevent unwanted crosstalk or interference. TTIP and TRING transmit an output at full power (0 dB) and should be routed with at least 10 mil spacing away from the receive signals. Center Tap Capacitor on the Transformer For best performance, it is recommended that the center tap of the receive transformer be bypassed to ground with a 0.1uF capacitor if a center tap is available. The capacitor will help filter out noise that otherwise could be AC coupled from the line interface through the transformer. TVDD Transmit Analog Power Supply (3.3V ±5%) TVDD can be shared with DVDD. However, it is recommended that TVDD be isolated from the analog power supply RVDD. For best results, use an internal power plane with copper pour separation. If an internal power plane is not available, a ferrite bead can be used. Each power supply pin should be bypassed to ground through an external 0.1µF capacitor. RVDD Receive Analog Power Supply (3.3V ±5%) For long haul applications, RVDD should not be shared with other power supplies. It is recommended that RVDD be isolated from the digital power supply DVDD and the analog power supply TVDD. For best results, use an internal power plane with copper pour separation. If an internal power plane is not available, a ferrite bead can be used. Each power supply pin should be bypassed to ground through an external 0.1µF capacitor.

Note: In long haul applications where the receive inputs can be severely attenuated, it is critical to have a clean power supply design and clean PCB layout with respect to RVDD. It is highly recommended that RVDD be isolated from DVDD and TVDD.

DVDD Digital Power Supply (3.3V ±5%) DVDD should be isolated from the analog power supplies. For best results, use an internal power plane with copper pour separation. If an internal power plane is not available, a ferrite bead can be used. Every two DVDD power supply pins should be bypassed to ground through at least one 0.1µF capacitor. AVDD Analog Power Supply (3.3V ±5%) AVDD should be isolated from the digital power supplies. For best results, use an internal power plane with copper pour separation. If an internal power plane is not available, a ferrite bead can be used. Each power supply pin should be bypassed to ground through at least one 0.1µF capacitor. GND It’s recommended that all ground pins of this device be tied together at one common ground point.

xrt86l38eval user manual - exar · xrt86l38eval user manual ... in order to test rbs, select the...

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