VCU128 GT IBERT Design Creation

March 2019

XTP529

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Revision HistoryDate Version Description03/21/19 1.1 Added Board Flow Files ZIP.

12/10/18 1.0 Initial version.

VCU128 IBERT Overview˃ Xilinx VCU128 Board˃ Software Requirements˃ Hardware Setup˃ Testing IBERT Designs

Testing IBERT FMC+Testing IBERT PCIeTesting IBERT QSFP

˃ Create IBERT DesignCompile Example DesignRun IBERT Example Design

˃ References

Note: This presentation applies to the VCU128

VCU128 IBERT Overview˃ Description

The LogiCORE Integrated Bit Error Ratio (IBERT) core is used to create a pattern generation and verification design to exercise the UltraScale Virtex GTY transceivers. A graphical user interface is provided through the Vivado Hardware Manager.

˃ Reference Design IPLogiCORE UltraScale IBERT GTY Example Designs

Xilinx VCU128 Board

VCU128 Software Install and Board Setup˃ Complete setup steps in XTP449 – VCU128 Software Install and Board

Setup:Software RequirementsVCU128 Board SetupUART Driver InstallClock SetupIBERT LoopbacksOptional Hardware Setup

Note: Clock Setup must be completed for IBERT testing

VCU128 Setup˃ Open the RDF0490 - VCU128 GT IBERT Design Files (2018.3 C) ZIP file, and

extract the “ready_for_download” files to your C:\ drive:

Note: Presentation applies to the VCU128

VCU128 Setup˃ Extract the VCU128 Board Flow Files to

C:\Xilinx\Vivado\2018.3\data\boards\board_files

Note: Board Flow Files are also available in the Xilinx Board Store:https://github.com/Xilinx/XilinxBoardStore/tree/2018.3/boards/Xilinx

Testing IBERT FMC+

Testing IBERT FMC+˃ Open a Vivado Tcl Shell:

Start → All Programs → Xilinx Design Tools → Vivado 2018.3 →Vivado 2018.3 Tcl Shell

Note: Presentation applies to the VCU128

Testing IBERT FMC+˃ In the Vivado Tcl Shell type:

cd C:/vcu128_ibert/ready_for_downloadsource ibert_bank_fmcp.tcl

Note: Presentation applies to the VCU128

Testing IBERT FMC+˃ If needed, set Vivado GUI Layout to Serial I/O Analyzer

Note: Presentation applies to the VCU128

Testing IBERT FMC+˃ FMC+ line rate is 28.125 Gbps˃ Close Vivado GUI and Tcl Shell when finished viewing

Testing IBERT PCIe

Testing IBERT PCIe˃ In a Vivado Tcl Shell type:

cd C:/vcu128_ibert/ready_for_downloadsource ibert_bank_pcie.tcl

Note: Presentation applies to the VCU128

Testing IBERT PCIe˃ 16 Gbps for PCIe; close Vivado GUI and Tcl Shell when finished

Testing IBERT QSFP

Testing IBERT QSFP˃ In a Vivado Tcl Shell type:

cd C:/vcu128_ibert/ready_for_downloadsource ibert_bank_qsfp.tcl

Note: This test requires a three user-supplied QSFP Loopback modules

Testing IBERT QSFP˃ 28.125 Gbps for QSFP; close Vivado GUI and Tcl Shell when finished

Create IBERT Design

Create IBERT Design˃ Open Vivado

Start → All Programs → Xilinx Design Tools → Vivado 2018.3 → Vivado

˃ Select Create Project

Note: Presentation applies to the VCU128

Create IBERT Design˃ Click Next

Note: Presentation applies to the VCU128

Create IBERT Design˃ Set the Project name and location to ibert_bank_all and C:/vcu128_ibert;

check Create project subdirectory

Note: Vivado generally requires forward slashes in paths

Create IBERT Design˃ Select RTL Project

Select Do not specify sources at this time

Note: Presentation applies to the VCU128

Create IBERT Design˃ Under Boards, select the VCU128

Create IBERT Design˃ Click Finish

Note: Presentation applies to the VCU128

Create IBERT Design˃ Click on IP Catalog

Note: Presentation applies to the VCU128

Create IBERT Design˃ Select IBERT UltraScale GTY, v1.3 under Debug & Verification

Note: Presentation applies to the VCU128

Create IBERT Design˃ Right click on IBERT UltraScale GTY and select Customize IP…

Note: Presentation applies to the VCU128

Create IBERT Design˃ Set the Component name: ibert_bank_all˃ Under the Protocol Definition tab

Select 2 Protocols

Create IBERT Design˃ Under the Protocol Definition tab

Protocol Custom 1: LineRate: 28.125, Refclk: 156.25 Quad Count: 10Protocol Custom 2: LineRate: 16.000, Refclk: 100 Quad Count: 4

Create IBERT Design˃ Under the Protocol Selection tab

Set QUAD_124 to QUAD_129 to Custom 1 / 28.125 Gbps

Create IBERT Design˃ Under the Protocol Selection tab

Set QUAD_131, QUAD_132, QUAD_134, and QUAD_135, to Custom 1 / 28.125 Gbps

Create IBERT Design˃ Under the Protocol Selection tab

Set QUAD_224 and QUAD_225 to Custom 2 / 16.000 Gbps, and MGTREFCLK0 225Set QUAD_226 and QUAD_227 to Custom 2 / 16.000 Gbps, and MGTREFCLK0 227

Create IBERT Design˃ Under the Clock Settings tab, set the System Clock:

Internal Clock: QUAD131 0

Create IBERT Design˃ Review the summary and click OK

Create IBERT Design˃ Click Generate

Note: This step will take about 30 minutes

Create IBERT Design˃ The Generated IBERT IP appears in Design Sources

Wait until checkmark appears on ibert_bank_all_synth_1

Note: Presentation applies to the VCU128

Compile Example Design˃ Right click on ibert_bank_all and select Open IP Example Design…

Note: Presentation applies to the VCU128

Compile Example Design˃ Set the location to C:/vcu128_ibert/ibert_bank_all and click OK

Note: Presentation applies to the VCU128

Compile Example Design˃ A new project is created under <design path>/˃ Click Generate Bitstream; takes about 100 minutes to compile

Note: The original project window can be closed

Compile Example Design˃ Open and view the Implemented Design

Note: Presentation applies to the VCU128

References

References˃ IBERT IP

IBERT for UltraScale GTY Transceivers – PG196‒ https://www.xilinx.com/support/documentation/ip_documentation/ibert_ultrascale_gty/v1_2/

pg196-ibert-ultrascale-gty.pdf

˃ Vivado Programming and DebuggingVivado Design Suite Programming and Debugging User Guide – UG908‒ https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/

ug908-vivado-programming-debugging.pdf

Documentation

Documentation˃ Virtex UltraScale+ HBM

Virtex UltraScale+ FPGA Family‒ https://www.xilinx.com/products/silicon-devices/fpga/virtex-ultrascale-plus.html

˃ VCU128 DocumentationVirtex UltraScale+ FPGA VCU128 Evaluation Kit‒ https://www.xilinx.com/products/boards-and-kits/vcu128-es1.html

VCU128 Board User Guide – UG1302‒ https://www.xilinx.com/support/documentation/boards_and_kits/vcu128/

ug1302-vcu128-eval-bd.pdfVCU128 - Known Issues and Release Notes Master Answer Record‒ https://www.xilinx.com/support/answers/71849.html