yield improvement of an eeprom for automotive applications

Confidential © ams AG 2016

Yield Improvement of an EEPROM for Automotive Applications while Maintaining High Reliability

VLSI Test Symposium 2016

Peter SarsonGregor SchatzbergerFriedrich Peter Leisenberger

25.04.2016


Introduction

• During standard production a problem was seen in production that looked like from production data that a huge issue with regard to reliability of an EEPROM was coming from the FAB.

• In reality this was not the case• I will show how an issue regarding a one parameter made a huge false alarm• I will show how this issue was resolved • I will show how the whole process was made more efficient by

- improving yield and- improving the quality of the reliability test data

• I will show how the new process was qualified • And discuss how the production test data changed• I will conclude with the root cause of the issue


Wafer map of an EEPROM (1kx8)showing abnormal fail pattern


Wafer map of an EEPROM (1kx8)showing random distributed fast EEPROM bit cells (red dots)


Electrical equivalent circuitLayout and TEM image of the EEPROM bit cell


Tunnel Oxide – main WAT parameter that effects reliability


TUX QBD WAT measurement results of maverick lot(LSL lower specification limit)


Drain source current distribution of the EEPROM bit cellsacross the lot.(USL upper specification limit)


Fully differential sense amplifier schematic


Drain source current wafer map of the EEPROM bit cells


1 fast bit @ VPP=9.5V

no fast

Example of fast bit


Abnormal wafer identified as fast bit wafer


Bit cell current distribution (programmed cell)of the maverick lot


Typical wafer map


Bit cell current distribution (programmed cell)of a typical lot. (USL upper specification limit)


Reliability

• The reliability of the bit cells are dependent on the fast bit tests screening out problem die which determine the integrity of the tunnel oxide

• The icell current has nothing to do with fast bits ,something is a miss• If we check the lifetime of the bad die we can prove if there is a reliability risk or not• Therefore we cycled the parts to 60K, lifetime + 10K and checked for failures


Endurance and data retention stress locations


Use the sense amp to measure all the bit cells


Wafer map of the EEPROM bit cell current test


Drain source current wafer map of the EEPROM bit cells


Current reduction explanation


Problem

• For lots that are centered having a fixed reference current has no issue• Once the process shifts to the extremes this no longer works as seen here• Previously the reference current was set to fixed value, this was the issue here• We can see the Digital Margin test correlates to the bit cell current test, this current is where the

reference current needs to be to detect either a 1 or 0.• Therefore the solution is simple, change the procedure to measure the digital margin test current

then set the current dynamically for each device.


Current reference not centered


Current reference centered for every device


CDF of bit cell current showing the median


Going back to the original issue


Wafer mapobtained with optimized production test program


Now it needs to be qualified

• Now we have to prove our theory by qualifying the process• Using a fast bit wafer we Ran 1 time the wafer with the old program, 1 time with the new • Look for devices that the new program missed, cycle these devices and see if they pass• We had one failure, the new tp missed a fast bit


Binflip


Qualified

• As we have moved the reference the previous program and erase voltage limits no longer apply and we needed to requalify this

• This was done by increasing the limit by 300mV therefore making the test more difficult• Running this procedure again on a fast bit wafer saw no issues with bin flips.


Old results vs new results

• It was never fully understood why the majority of the fast bit failures were Erase failures and not so many program failures

• Now looking at the findings from this investigation it was shown that the program test was constructed in such a way that it was very easy to pass and the erase very easy to fail.

• Now by centering the reference for each individual device the failures are now close to 50:50• We believe some maverick lots from the past were not maverick lots


Root Cause

• The root cause for this issue was found several months after the problem was identified and as a result is not in the paper.

• However I will share with you some data,• The issue came from a etch step of the RPOLY layer where some the RPOLY wasn’t etched away

correctly.• This issue came about due to the installation of some new equipment.

• However I'm not allowed to show you any pictures, sorry


Inspiration

• During the development of this idea, new, weird and wacky ideas were developed• There is lots more material to come from ams on this subject• We just need to file a few patents first so be patient!


Conclusion

• I have demonstrated how an issue arising in the FAB caused a huge false alarm regarding quality and reliability

• I have shown how the reduction in icell current of the bit cell resulted in the test program showing a reliability failure with regard to fast bits.

• I have shown how this issue was resolved using the ams EEPROM test interface to dynamically set the reference current to the individual bit cell current of each die.

• I have shown how this was qualified and released into production• I have given details of how the test data has improved • I have also given details on the root cause of the issue


Thank you

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yield improvement of an eeprom for automotive applications

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