your one stop iot solution asic/ soc integration and ......•synopsys primetime–px. ... power...
TRANSCRIPT
![Page 1: Your One Stop IoT Solution ASIC/ SoC Integration and ......•Synopsys PrimeTime–PX. ... Power Verification Power Estimation & Design for Power. PT-PX Check power in term of: •](https://reader034.vdocument.in/reader034/viewer/2022042115/5e92cf88113b4a44fb75c2b9/html5/thumbnails/1.jpg)
Your One Stop IoT Solution
ASIC/ SoC Integration and Verification
![Page 2: Your One Stop IoT Solution ASIC/ SoC Integration and ......•Synopsys PrimeTime–PX. ... Power Verification Power Estimation & Design for Power. PT-PX Check power in term of: •](https://reader034.vdocument.in/reader034/viewer/2022042115/5e92cf88113b4a44fb75c2b9/html5/thumbnails/2.jpg)
PPA space FE
IP
BE
INTG VRFY
TEST
PKG
PW
PR
FA
reaC
ost
Besides on your spec to balanced PPA space.
EX: You want design the max Power .
In the FE begin, you need consider in mind for Power
Performance
Area
Power
Your Design spec
![Page 3: Your One Stop IoT Solution ASIC/ SoC Integration and ......•Synopsys PrimeTime–PX. ... Power Verification Power Estimation & Design for Power. PT-PX Check power in term of: •](https://reader034.vdocument.in/reader034/viewer/2022042115/5e92cf88113b4a44fb75c2b9/html5/thumbnails/3.jpg)
Always think of how to improve PPA
• Bus performance
• Clock/reset arch plan
• ASIC/SOC boot plan
• Memory usage plan
Integrate ASIC/SOCFE
IP
BE
INTG
VRFY
TEST
PKG
PW
PR
FA
rea
Cost
![Page 4: Your One Stop IoT Solution ASIC/ SoC Integration and ......•Synopsys PrimeTime–PX. ... Power Verification Power Estimation & Design for Power. PT-PX Check power in term of: •](https://reader034.vdocument.in/reader034/viewer/2022042115/5e92cf88113b4a44fb75c2b9/html5/thumbnails/4.jpg)
• Performance issue at Host A.
• Host A want read data form Ext memfrom SDRAM Through HOST B to Ext SD Card.
• After analysis with it. We find There have 4 timing path in this critical path. Ext to HOST A . HOST A to SDRAM. SDRAM to HOST B. HOST B to Ext SD.
• After Optimization this arch. Wereduce full path from 4 path to 2 path. This could increase 50% performance.
Scenario #1 FE
IP
BE
INTG VRFY
TEST
PKG
PW
PR
FA
reaC
ost
![Page 5: Your One Stop IoT Solution ASIC/ SoC Integration and ......•Synopsys PrimeTime–PX. ... Power Verification Power Estimation & Design for Power. PT-PX Check power in term of: •](https://reader034.vdocument.in/reader034/viewer/2022042115/5e92cf88113b4a44fb75c2b9/html5/thumbnails/5.jpg)
Scenario #2
• After review system power save plan.
• Optimization RTL for Clock Gate.
• Separate to Operate/Sleep/Slow mode for SW Control.
• After Optimization, power is reduce.
FE
IP
BE
INTG VRFY
TEST
PKG
PW
PR
FA
reaC
ost
![Page 6: Your One Stop IoT Solution ASIC/ SoC Integration and ......•Synopsys PrimeTime–PX. ... Power Verification Power Estimation & Design for Power. PT-PX Check power in term of: •](https://reader034.vdocument.in/reader034/viewer/2022042115/5e92cf88113b4a44fb75c2b9/html5/thumbnails/6.jpg)
• There have a power limit in the ASIC Boot up time.
• After review system power usages in ASIC Boot.
• Optimization RTL for System reset control flow.
• Separate reset to HW Boot/SW Boot/Operate mode.
• After Optimization, power is reduce.
FE
IP
BE
INTG VRFY
TEST
PKG
PW
PR
FA
reaC
ost
Scenario #3
![Page 7: Your One Stop IoT Solution ASIC/ SoC Integration and ......•Synopsys PrimeTime–PX. ... Power Verification Power Estimation & Design for Power. PT-PX Check power in term of: •](https://reader034.vdocument.in/reader034/viewer/2022042115/5e92cf88113b4a44fb75c2b9/html5/thumbnails/7.jpg)
• There are use 16 SRAM on chip.
• After review application use, we
optimization RTL for memory number
and memory size.
• After Optimization, power is reduce.
Scenario #2.3 FE
IP
BE
INTG VRFY
TEST
PKG
PW
PR
FA
reaC
ost
![Page 8: Your One Stop IoT Solution ASIC/ SoC Integration and ......•Synopsys PrimeTime–PX. ... Power Verification Power Estimation & Design for Power. PT-PX Check power in term of: •](https://reader034.vdocument.in/reader034/viewer/2022042115/5e92cf88113b4a44fb75c2b9/html5/thumbnails/8.jpg)
ASIC/SoC Verification
Your One Stop IoT Solution
![Page 9: Your One Stop IoT Solution ASIC/ SoC Integration and ......•Synopsys PrimeTime–PX. ... Power Verification Power Estimation & Design for Power. PT-PX Check power in term of: •](https://reader034.vdocument.in/reader034/viewer/2022042115/5e92cf88113b4a44fb75c2b9/html5/thumbnails/9.jpg)
Verification
Verification
Performance(Function)
Power Com
HW/SW Co-V
FPGA
SW VIP
PTPX EVB& system TestRTL Verification
![Page 10: Your One Stop IoT Solution ASIC/ SoC Integration and ......•Synopsys PrimeTime–PX. ... Power Verification Power Estimation & Design for Power. PT-PX Check power in term of: •](https://reader034.vdocument.in/reader034/viewer/2022042115/5e92cf88113b4a44fb75c2b9/html5/thumbnails/10.jpg)
Always think of how to improve PPA
• HW/SW control flow
• FPGA Verification
• Timing verification
• Chip-level verification
VerificationFE
IP
BE
INTG
VRFY
TEST
PKG
PW
PR
FA
rea
Cost
![Page 11: Your One Stop IoT Solution ASIC/ SoC Integration and ......•Synopsys PrimeTime–PX. ... Power Verification Power Estimation & Design for Power. PT-PX Check power in term of: •](https://reader034.vdocument.in/reader034/viewer/2022042115/5e92cf88113b4a44fb75c2b9/html5/thumbnails/11.jpg)
• Review system Function/TMOD Verification Plan.
• Distinguish Verification for Function/TMOD
Verification (RTL)
Functional Mode
Test Mode
FE
IP
BE
INTG
VRFY
TEST
PKG
PW
PR
FA
rea
Cost
![Page 12: Your One Stop IoT Solution ASIC/ SoC Integration and ......•Synopsys PrimeTime–PX. ... Power Verification Power Estimation & Design for Power. PT-PX Check power in term of: •](https://reader034.vdocument.in/reader034/viewer/2022042115/5e92cf88113b4a44fb75c2b9/html5/thumbnails/12.jpg)
PATTERNGEN
(SDRAM/NOR
/PLL/LDO
)
PIN1
PIN2
PIN3
PIN4
PIN X
JTAG
NOR Flash
MCU
PLL
SDRAM
BIST
LDO
BSD
SCAN
Other
• Review system Function/TMOD
Verification Plan.
• There will Separate.
• Verification IP for TMOD.
• Increase ASIC verification Level.
Functional & Test Mode
![Page 13: Your One Stop IoT Solution ASIC/ SoC Integration and ......•Synopsys PrimeTime–PX. ... Power Verification Power Estimation & Design for Power. PT-PX Check power in term of: •](https://reader034.vdocument.in/reader034/viewer/2022042115/5e92cf88113b4a44fb75c2b9/html5/thumbnails/13.jpg)
Where does SW code boot from?
What is the Application?
• Finish HW IP Level Verification.
• Use SW to build up System level
Verification.
• Use HW&SW Co-work for Deep System
Verification.
HW/SW Co-V
![Page 14: Your One Stop IoT Solution ASIC/ SoC Integration and ......•Synopsys PrimeTime–PX. ... Power Verification Power Estimation & Design for Power. PT-PX Check power in term of: •](https://reader034.vdocument.in/reader034/viewer/2022042115/5e92cf88113b4a44fb75c2b9/html5/thumbnails/14.jpg)
Scenario #4
• This is HW/SW SOC Platform
• ARM C compiler is link with ARM JTAG
• UART could display SW process massage on PC
• FPGA JTAG is use for program SOC Design
• When SOC on, we will program SOC Design and SW
![Page 15: Your One Stop IoT Solution ASIC/ SoC Integration and ......•Synopsys PrimeTime–PX. ... Power Verification Power Estimation & Design for Power. PT-PX Check power in term of: •](https://reader034.vdocument.in/reader034/viewer/2022042115/5e92cf88113b4a44fb75c2b9/html5/thumbnails/15.jpg)
SW VIP
• KeyASIC FPGA verification program
• Implemented 27+ IPs on SoC FPGA.
• If SOC HW Design have any change.This SW VIP could verification quickly.
• KA also implement Linux base Boot-loader• New IP verification can be easily integrated in this Boot-loader.
![Page 16: Your One Stop IoT Solution ASIC/ SoC Integration and ......•Synopsys PrimeTime–PX. ... Power Verification Power Estimation & Design for Power. PT-PX Check power in term of: •](https://reader034.vdocument.in/reader034/viewer/2022042115/5e92cf88113b4a44fb75c2b9/html5/thumbnails/16.jpg)
• Synopsys PrimeTime–PX.
• Create real application test vector estimation.
• Re-view different Operate mode.
Power Verification
Power Estimation & Design for Power
![Page 17: Your One Stop IoT Solution ASIC/ SoC Integration and ......•Synopsys PrimeTime–PX. ... Power Verification Power Estimation & Design for Power. PT-PX Check power in term of: •](https://reader034.vdocument.in/reader034/viewer/2022042115/5e92cf88113b4a44fb75c2b9/html5/thumbnails/17.jpg)
PT-PX
Check power in term of:
• I/O• Memory• Black_Box• Clock• Register• Combo logic• Report Segmented & total
power
![Page 18: Your One Stop IoT Solution ASIC/ SoC Integration and ......•Synopsys PrimeTime–PX. ... Power Verification Power Estimation & Design for Power. PT-PX Check power in term of: •](https://reader034.vdocument.in/reader034/viewer/2022042115/5e92cf88113b4a44fb75c2b9/html5/thumbnails/18.jpg)
Scenario #6
• Analysis 3 system Operate mode for Estimation detail power information.• After design optimization. 20mW drop to 15mw . 51mW drop to 5mW.
![Page 19: Your One Stop IoT Solution ASIC/ SoC Integration and ......•Synopsys PrimeTime–PX. ... Power Verification Power Estimation & Design for Power. PT-PX Check power in term of: •](https://reader034.vdocument.in/reader034/viewer/2022042115/5e92cf88113b4a44fb75c2b9/html5/thumbnails/19.jpg)
• Verification with EVB
• Build real application with PCB Environment
• Camera access KA WIFI SOC
Chip VerificationFE
IP
BE
INTG
VRFY
TEST
PKG
PW
PR
FA
rea
Cost
![Page 20: Your One Stop IoT Solution ASIC/ SoC Integration and ......•Synopsys PrimeTime–PX. ... Power Verification Power Estimation & Design for Power. PT-PX Check power in term of: •](https://reader034.vdocument.in/reader034/viewer/2022042115/5e92cf88113b4a44fb75c2b9/html5/thumbnails/20.jpg)
Summary
• PPAC as the key index to measure how good a chip is Besides having the right
knowledge & skillset
• Execute your flow with disciplines, always check back against PPAC at any stages!
• A chip design methodology outline is presented and will be covered in details in the
coming sessions
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Thank You