114 • 2009 IEEE International Solid-State Circuits Conference

ISSCC 2009 / SESSION 6 / CELLULAR AND TUNER / 6.2

6.2 A SAW-Less Multiband WEDGE Receiver

Olivier Gaborieau1, Sven Mattisson2, Nikolaus Klemmer3, Bassem Fahs1,Fabio T. Braz1, Richard Gudmundsson2, Thomas Mattsson2, Carine Lascaux1, Christophe Trichereau1, Wen Suter3, Eric Westesson2, Andreas Nydahl2

1ST-NXP Wireless, Caen, France, 2Ericsson Mobile Platforms, Lund, Sweden3Ericsson Mobile Platforms, Raleigh, NC

With an ever-increasing number of frequency bands supported by cellulartransceivers (TRX), front-end (FE) complexity increases due to a large num-ber of external SAW filters. The challenge of removing inter-stage filters frommultiband 3G receivers (RX) resides in the additional noise contribution dueto limited transmitter (TX) leakage rejection at the RX input, intermodulation(IM) products and cross-compression due to TX leakage and strong out-of-band blockers. Increased downconverter dynamic range is thus required for aSAW-less RX path. In addition, avoiding SNR degradation from reciprocalmixing imposes additional constraints on LO phase noise.

The presented transceiver (Fig. 6.2.1) integrates all RX and TX functionsrequired to support a tri-band WCDMA/HSPA (bands I-VI, VIII, IX) and quad-band GSM/GPRS/EDGE application in a single chip.

The transmit section uses two separate paths: one for EGPRS (polar modula-tion) and another one for WCDMA (direct conversion). Compared to previous-ly published work [1-3], this TRX provides a higher integration level, yieldinga superior flexibility in the application and a lower bill-of-materials (BOM).

The circuit employs a 2-metal passive integration technology (PICS) allowingthe integration of high-Q LNA degeneration inductors, TX matching networks,PLL filters and high-density supply-decoupling capacitors. The active(10mm²) and passive (40mm²) die are double-flip-chip mounted into a 56-pinpackage. In order to improve the isolation between RX and TX paths (operat-ing simultaneously in 3G mode), octagonal-shaped VCO inductors are usedwith mutually-orthogonal orientations to achieve better than 95dB isolationbetween RX and TX VCOs. RX input and TX output paths are routed orthogo-nally to further minimize the RF coupling.

Figure 6.2.2 shows the FE architecture, comprising seven single-ended gain-switchable LNAs (three in 3G and four in 2G). A double-cascode structure pro-vides high isolation between inputs and minimum group-delay change whenswitching between high and low gain (-16dB) modes. The LNA degenerationinductors are implemented in Al-metal on the passive substrate (PICS), withtypical inductance/Q-factor values of 0.7nH/20 at 2GHz and 2.3nH/18 at 1GHz.In 2G mode, each pair of high/low-band LNAs employs a shared degenerationinductor to save area. The LNA output currents are combined in a 2nd-level cas-code circuit and passed through to the RX balun primary coil. Large PMOSdevices are used to configure this inductance between low- and high-bandsettings, with transfer ratios of 6:4/4:3 in high/low band, respectively. Theinterstage frequency response is tuned per band using a capacitance DAC. TheLNA output-current signal is AC coupled to the downconverter core via thebalun secondary winding. This effectively prevents LNA even-order distortioncomponents from entering the downconverter stage. The balun output currentcirculates through two identical current commutators, consisting of transis-tors Q1, Q2, and Q1′, Q2′ respectively. In high-band operation, the overall cur-rent-commutation sequence is generated by directing the CKp,n controlled,VCO-rate current pulses through switches Q1a,b to the baseband outputs viaCK/2-rate switches Q2a-d. Sequencing signals LIp,n, LQp,n are generated by aconventional divide-by-2 quadrature circuit. The switching transients of Q2a-dare controlled such that the sequencing signals are stable for the duration ofthe corresponding CK half-period. In this way, sequencer output jitter ismasked and low-power operation is possible without impact on reciprocalmixing of out-of-band blockers.

As a result, Q1 RF input current is directed to the I+, Q+, I-, Q- outputs for sub-sequent quarters of the CK/2 signal period. Conversion gain is √2x2/π foreach of the differential baseband outputs. Due to signal current re-use in thesecond commutator, overall conversion gain is √2x4/π, 3dB higher than for atraditional Gilbert I/Q-mixer having the same current consumption. I/Q gainand phase balance are achieved by maintaining accurate 50% duty cyclethroughout the VCO paths, and converter IP2 is maximized by maintaining ahigh degree of active and passive component matching. Out-of-band blocking

is maximized by protecting the baseband filter via a tuned RC roofing filterpole.

The baseband channel filter (BCF) (Fig. 6.2.3) is designed as a reconfigurableLegendre 5th-order (Gain~63 to 65dB, BW~2.15MHz) filter response inWCDMA mode and a Butterworth 3rd-order (Gain~25 to 28dB, BW~230kHz)response in GSM/EDGE mode. GSM/EDGE high-dynamic-range ADC’s are co-integrated on chip [6]. RC auto-calibration and DC-offset cancellation in theBCF help to overcome process and temperature drifts. A group-delay-variationcompensation minimizes WCDMA RX EVM.

Two VCOs are used to generate the RX LO signal at 2× and 4× RX frequenciesfor low and high bands, respectively. Each VCO uses a 6b binary-weightedNMOS varactor bank with 25% and 36% tuning range, respectively. BothVCOs employ octagonal-shaped coils (Q~19 at 4GHz) to mitigate externalmagnetic coupling. Measured phase-noise levels are below −155dBc/Hz at45MHz offset at low- and high-band RX frequencies. VCO supply current is4mA.

The VCOs are locked via the same 3rd-order ΔΣ fractional-N PLL. A tempera-ture-adaptive loop-filter pre-charging system, active only during VCO bandself-calibration, preserves PLL locking in 3G mode over a wide temperaturerange (-30 to +90°C), whatever the initial locking temperature is. The 3rd-orderPLL natural frequency is set to 160kHz, with loop-filter resistors implementedon the active die, while the capacitors are located on the passive die. An RC-calibrator adjusts the filter capacitors to compensate for process and temper-ature variations. Close-in phase noise is -96dBc/Hz @10kHz offset from a2GHz carrier.

Figure 6.2.5 shows measured RX Noise Figure (NF) results for two scenariosin band II (1990MHz):

1) in the presence of a WCDMA modulated blocking signal generated by theon-chip TX at the band-specific duplex offset frequency (80MHz)

2) in the presence of a -45dBm CW blocking signal at half and double duplexoffset frequencies (corresponding to a -15dBm blocker at the antenna and30dB duplexer attenuation).

Cross-compression, IM2 and IM3 performances are shown with CW, WCDMATX, and WCDMA TX & CW blockers respectively. Under worst-case duplexerTX-RX isolation, a -26dBm out-of-band blocker at the LNA input results in2.7dB/3dB NF, under CW and WCDMA modulation respectively.Desensitization due to -26dBm CW blockers in addition to TX leakage is:

0.5/1.7dB at -380/-95MHz offset, respectively (band I)0.6/1.8dB at -160/-40MHz offset, respectively (band II)1/2dB at -90/-22.5MHz offset, respectively (band V)

Figure 6.2.4 shows measured RX EVM for 3GPP test-model 5 HSDPA with 16-QAM modulation. A low EVM of less than 6% is maintained over a wide inputpower range. Figure 6.2.6 shows a comparison with published RX work [2, 3].

A significant contribution to overall WEDGE radio cost is due to phone produc-tion calibration. In this TRX, all filters, VCOs and PLL bandwidths are internal-ly self-calibrated.

The active die is implemented in a 0.25µm BiCMOS process. The carrier sub-strate is realized in PICS and integrates all TRX components, including supplydecoupling into a single package. A crystal resonator is the only external com-ponent required. This TRX is in volume production.

References:[1] H. Darabi et al., “A Fully Integrated Quad-Band GPRS/EDGE Radio in 0.13µm CMOS,”ISSCC Dig. Tech. Papers, pp. 206-207, Feb. 2008.[2] B. Tenbroek et al., “Single-Chip Tri-Band WCDMA/HSDPA Transceiver WithoutExternal SAW Filters and with Integrated TX Power Control,” ISSCC Dig. Tech. Papers,pp. 202-203, Feb. 2008.[3] J. Rogin et al., “A 1.5V 45mW Direct-Conversion WCDMA Receiver IC in 0.13µmCMOS,” IEEE J. Solid State Circuits, pp. 2339-2348, Dec. 2003.[4] C. Takahasi et al, “A 1.9GHz Si Direct-Conversion Receiver IC for QPSK ModulationSystems,” ISSCC Dig. Tech. Papers, pp. 138-139, Feb. 1995.[5] Behzad Razavi, “A 1.5V 900MHz Downconversion Mixer,” ISSCC Dig. Tech. Papers,pp. 48-49, Feb. 1996.[6] Y. Le Guillou et al., “Highly Integrated Direct-Conversion Receiver forGSM/GPRS/EDGE with On-Chip 84dB Dynamic Range Continuous-Time ContinuousTime ΣΔ ADC”, IEEE J. Solid State Circuits, vol. 40, no2, pp. 403-411, Feb. 2005.

978-1-4244-3457-2/09/$25.00 ©2009 IEEE

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Figure 6.2.1: Multi-band WEDGE transceiver block diagram. Figure 6.2.2: WEDGE RX front-end schematic.

Figure 6.2.3: WEDGE RX baseband filter and AGC schematic.

Figure 6.2.5: WCDMA Band II NF versus frequency and versus TX Power at LNA. Figure 6.2.6: Receiver performance summary.

Figure 6.2.4: Out-of-band IIP2 and RX EVM (3GPP test-model 5+8 HS-PDSCH) versusinput power.

0.25μm BiCMOS HVQFN56 7x7

0.13μm digital CMOS 0.25μm BiCMOS HVQFN56 7x7

6

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• 2009 IEEE International Solid-State Circuits Conference 978-1-4244-3457-2/09/$25.00 ©2009 IEEE

ISSCC 2009 PAPER CONTINUATIONS

Figure 6.2.7: Transceiver micrograph highlighting the receiver path.

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