zhang rtp q307

1© 2006, Cisco Systems, Inc. All rights reserved.Base Env

Cisco Base Environment Overview

Joseph ZhangSeptember 2007


• Motivation

• Description

• Benefits

• Q and A

Agenda


Standardize on Reuse Methodology

• Design reuse not enough – Verification increasingly becoming schedule bottleneck.

• Leverage best practices from previous projects.

Focus on methodology, not language or implementation.

• Ultimate goals:unit-level to chip-level reuse. leverage automation to reduce labor intensive tasks.educate and empower DV staff.improve scheduling predictability.

Mot

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• Motivation

• Description

• Benefits

• Q and A

Agenda


Standard ASIC DV Methodology

• Defines Common Topology and Directory Structure

• Leverage Existing Best PracticesShaggy, Scooby, Marmot, Cobalt, GoldenEye, XChip, etc…

• Vertically Scalable from Unit to System

• Horizontally Scalable Across Projects

Des

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Investment

• Development Spanned 10 Calendar MonthsTeam consists of DV leads from RTP and BXB

• Implemented Methodology in Specman Toolkit

Scripts

Templates

12 Verification IP

Documentation and

Training Material and Sessions

• Created Reference Project (Newby)

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Implementation OverviewMY_CHIP csco_tb_u

TB VSD

SeqSeq

Seq

auto-created byeVC topology script

clkgen

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Additional Tool Enhancements

• csco_verbosityDisplays all of the available message loggers Enables user to create a file that can change logger settings (or apply any other Specman command) at specific simulation times

• csco_ovl_specmanPackage consisting of OVL, Verilog, and e code that turns each OVL assertion event into a Specman event for use in either coverage or checkingTies assertion based verification (ABV) with coverage driven verification (CDV)

Des

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• Motivation

• Description

• Benefits

• Q and A

Agenda


Extensive Reuse

• Reuse of TechniquesCoding techniques that address complex testbench functions are in the testbench from the beginning of the project

• Reuse of SpecificationTight integration with Blueprint enables source for RTL creation to also be used for testbench creation

• Reuse of CodeVertical Scaling - all unit benches may be reused at higher levels, even up to system simulationsHorizontal Scaling - verification components may be reused between projects

• Reuse of TestsStandardization of testbench infrastructure allows some tests to be automatically created and many others to be reused or leveraged at higher levels

• Reuse of TrainingCommonality of look and feel of testbench infrastructure means no need to re-learn testbench interfaces

Ben

efits


Improved Predictability• Planning

Common infrastructure allows more detailed and accurate planning

• ExecutionHorizontal scaling and improved training results in quicker ramp up time for verification resourcesVertical scaling enables focused unit testing resulting in greater parallel use of resourcesLarge reusable code base reduces code development

• SuccessEarly testing ensures DUT is sanity checked earlyMethodology and underlying packages ensure that DUT has been adequately exercised and checked

Ben

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Higher Return on VIP Development

• Methodology is required to support VIP reuseCommon language helps but is not nearly enoughStandardization required

Configuration interfaceInter-process communicationStimulus generationScoreboarding schemes

• Cisco Base Environment VIPStandard interface and usage model allows quick integration into TBMore mileage and maturity from our VIP will reduced verification costPeople will actually want to use the VIP!

Ben

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Solves Common DV Problems

• How can I quickly start a DV environment?The templates and scripts in Cisco Base Environment make it easy to instantiate the infrastructures of a DV environment in < 1 day

Invoke make_proj_vob.pl to create directory structure and chip-level TB skeleton

Invoke mkevc.pl to create skeleton VIP packages to drive/monitor interface

Invoke make_unit_pkg.pl to create skeleton environments for each unit-level TB

Ben

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• How can I make sure my unit-level TB and testcases can be reused at the chip-level and higher?

csco_addrmap package ensures that CPU transactions are transparent from unit-level to chip-levelcsco_event package ensures that interrupt handling is transparent from unit-level to chip-levelcsco_trans enables sum-of-parts scoreboarding where unit-level scoreboards are chained to form end-to-end scoreboardcsco_testflow ensures that all TB components execute in sync. with reach other, across all TB levelscsco_clkgen provides transparent clock generation and sampling across all TB levels

Ben

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• How do I know I’ve accurately and sufficiently modeled the DUT registers?

Tight Blueprint integration means same RDL is used to generate both RTL and DV code

Predefined test sequences in csco_addrmapand csco_event are used to perform automatic structural testing on registers and interrupts

Blueprint code generator also creates DV configuration modules from control registers in RDL

Ben

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• How can I make sure my TB can support dynamic resets?

csco_config supports dynamic full or partial regeneration of TB configuration tree

csco_testflow supports reset of all or any portion of the TB with automatic re-launching of initialization and test stimulus

Ben

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• How do I start debugging once something goes wrong?

csco_trans links and archives all transactions in the TB, reducing the need to generate huge waveforms

csco_testflow issues timeout errors when a TB component stalls the simulation

csco_trans issues timeout errors when a transaction spends too much time in the TB

csco_verbosity allows user to interactively inject TB commands, reducing dependency on often slow and cumbersome GUI

Ben

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• Motivation

• Description

• Benefits

• Q and A

Agenda

zhang rtp q307

Documents

cisco systems

unitlevel tb base env

projects base env

testbench interfaces

chiplevel reuse

chiplevel csco

chiplevel benefits csco

unitlevel scoreboards