The Novel Chinese Abacus Adder

Zhongkai Chen

Literature Information

Appears in: VLSI Design, Automation and Test, 2007. VLSI-DAT 2007. International Symposium on Date:25-27 April 2007

Zi-Yi Zhao, Chien-Hung Lin, Yu-Zhi Xie, Yen-Ju Chen, Yi-Jie Lin, and Shu-Chung Yi.

National Changhua University of Education, Changhua, Taiwan 500, ROC

Outline

Introduction BA (Binary to Abacus) Module PA (Parallel Addition) Module TB (Thermometric to Binary) Module Example Extension to 4n-Bit Adder Results

Introduction

The first digital arithmetic circuits employing the method of the Chinese abacus were proposed on 1998.

The most drawback is the delay time due to serial addition of each bead by the Shift-Up module

Introduction

(a) Chinese abacus coding with base 10 of the decimal number 6

(b) the proposed Chinese abacus adder coding with base 16 of the decimal number 9

5

1

4

1

Introduction

Block diagram of the 4-bit abacus adder

BA (Binary to Abacus) Module

This module converts a 4-bit binary number (I3I2I1I0)2 into an abacus representation (H2H1H0 | L2L1L0)abacus.

H2H1H0 and L2L1L0 are determined by:

H2=I3I2, H1=I3, H0=I3+I2

L2=I1I0, L1=I1, L0=I1+I0

Where 0≤H2 ≤H1 ≤H0 ≤1,

and 0 ≤L2 ≤L1 ≤L0 ≤1.

H2H1H0: Higher BeadsL2L1L0: Lower Beads

PA (Parallel Addition) Module This block can parallel

add two abacus numbers simultaneously.

The sum of (X2X1X0) and (Y2Y1Y0) will then be represented as the thermometric transformation (K5K4K3K1K0), where 0 ≤Ki ≤Kj ≤1 for i>j.

PA (Parallel Addition) Module The behavior of PA module is modeled in the

following equations:

1. This module acts similarly as a multiplexer. The addend X2~X0

2. are as signal selectors to modify the configuration of augend Y2~Y0.

3. The thermometric results will be then represented in K5~K0.

4. There are only four configurations of addend (X2X1X0), i.e., (000), (001), (011), or (111).

PA (Parallel Addition) Module

PA (Parallel Addition) Module

PA (Parallel Addition) Module

TB (Thermometric to Binary) Module

This module transforms thermometric representation to binary numbers. The outputs O1, Oo and C0ut are determined by the following equations:

O0=K0∙Cin+K1∙K0∙Cin+K2∙K1∙Cin

+K3∙K2∙Cin+K4∙K3∙Cin+K5∙K4∙Ci

n+K5∙Cin

O1=K5+K4 ∙Cin+K2 ∙K0 ∙Cin+K4 ∙K1 ∙Cin

Cout=K3+ K2 ∙Cin

Example: 9+13

9=>(1001) 13=> (1101) (1001)+(1101)BA Module: BA1: (1001)2=(011|001)abacus

BA2: (1101)2=(111|001)abacus

PA Module: PA1: X2=0 X1=1 X0=1 Y2=1 Y1=1

Y0=1 PA2: X2=0 X1=0 X0=1 Y2=0 Y1=0

Y0=1

Example: 9+13

PA1: X2=0 X1=1 X0=1 , Y2=1 Y1=1 Y0=1, f1=X2X1=1, f2=X1X0=0

K0=1, K1=1, K2=Y0=1, K3=Y1=1, K4=Y2=1 K5=0

Example: 9+13

PA2: X2=0 X1=0 X0=1, Y2=0 Y1=0 Y0=1, f1=X2X1=0 f2=X1X0=1

K0=1 K1=Y0=1 K2=Y1=0 K3=Y2=0 K4=0 K5=0

Example: 9+13

TB Module:

TB2: Cin=0, K0=1 K1=1 K2=0 K3=0 K4=0 K5=0 O0=…=0+0+0+0+0+0+0=0 O1=…=0+0+0+1=1 Cout=…=0

O0=K0∙Cin+K1∙K0∙Cin+K2∙K1∙Cin+K3

∙K2∙Cin+K4∙K3∙Cin+K5∙K4∙Cin+K5∙Ci

n

O1=K5+K4 ∙Cin+K2 ∙K0 ∙Cin+K4 ∙K1 ∙Cin

Cout=K3+ K2 ∙Cin

Example: 9+13

TB1 Cin=0, K0=1, K1=1, K2=1, K3=1, K4=1 K5=0 O0=…=0+0+0+0+0+1+0=1 O1=…=0+0+0+0=0 Cout=…=1+0=1

Final Answer: (10110)2 =22

O0=K0∙Cin+K1∙K0∙Cin+K2∙K1∙Cin+K3

∙K2∙Cin+K4∙K3∙Cin+K5∙K4∙Cin+K5∙Ci

n

O1=K5+K4 ∙Cin+K2 ∙K0 ∙Cin+K4 ∙K1 ∙Cin

Cout=K3+ K2 ∙Cin

Extension to 4n-Bit Adder

Generally, conventional fast adders of high bit number are all connected by 4-bit unit adders. The Chinese abacus adder can also extend to 4n-bit adder by CLA-like or conditional-sum-adder-like methods.

Replace it with Abacus Adder

Extend both A and B to 4 bits

The Cout of CLA:Ci+1=Gi+PiCi

The Cout of Abacus Adder:Cout=K3+K2Cin

Compared the above two equations, the 4-bit basic unit abacus adder can be extended to a 4n-bit CLA-like abacus adder

Results

The delay of the 8-bit abacus adders are 22%, and 14% less than those of CLA adders for 0.35um, and 0.18um technologies, respectively.

The power consumption of the abacus adders are 30%, and 60% less than those of CLA adders for 0.35um, and 0.18um technologies, respectively.

The transistor count of abacus adder is similar to that of CLA

Results

The delays of the 32-bit abacus adder are 17%, and 12% less than those of CLA adder for 0.35um, and 0.18um technologies, respectively.

Thank you. Questions?