zuken - improve pcb quality and cost with concurrent power integrity analysis - pcb west 2011

Improve PCB Quality and Cost with

Concurrent Power Integrity Analysis Ralf Brüning, Product Manager High-Speed Design

Solutions/Senior Partner

Humair Mandavia, Senior Technical Marketing Manager

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Agenda

• Increasing challenges with power

distribution systems on modern

high-speed PCBs

• The problem:

– IC input impedance behavior

– Resonance behavior of PDS

– Role of decoupling capacitors

• EDA methodology for concurrent

power integrity simulation

throughout PCB design process

• Summary/Outlook

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PCB Design

Problems

PCB Design

Problems

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Traditional Verification Disciplines

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Power Distribution Systems

DC Voltages are not equally distributed and not considered ideal over

copper planes

“Voltage drops” occur on the copper area and within the vias

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Voltage

Source

Loads

3.3V 3.25V

3.27V

Example: 3.3V Power Distribution System

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Basic Electrical Concepts

5

• Resistors dissipate energy

– Resistance = Voltage / Current (R = V / I)

– Voltage = Current Resistance (V = I R)

• Capacitors store energy in an electric field

– Charge = Capacitance Voltage (q = CV)

– Current (q / time) = C (V / t) (I = C V / t)

– Power plane over ground plane is a great capacitor!

• Inductors store energy in a magnetic field

– Voltage = Inductance (I / t) (V = L I / t)

– Oppose current changes with a voltage

– Inductive kick: pull the plug on a vacuum cleaner

when it’s running!

R

V

I

C

L

VVV I

+

+ V I / t

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Voltage Supply for ICs:

Power Distribution System (PDS)

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• The power distribution system (PDS) will provide voltages and charge to the ICs

on a PCB

• Charge on the board must be supplied over a broad frequency range:

- Low frequency activities (we still have them)

- In MHz range for CPU-peripheral interfaces

- At the clock frequency (several hundreds of MHz)

- Provide a low impedance path for parasitic voltages at various

harmonics of the clock

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Power Plane Resonances Impedance

Behavior

• Power Plane Pair input impedance vs. frequency shows varied behavior

in different ranges:

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Local dependency of Plane Impedance

Capacitive

behavior

(“DC”)

Z=1/jC

LC-Series

resonance of the

plate capacitor

with the plane’s

inductance

Inductive

behavior of the

plane

2D-Resonances

Continue to

infinity…

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Power Plane Pairs Concerns

• Power plane pairs are used to provide the switching current to the ICs in a

higher frequency range where decoupling capacitors cannot work effectively

(f>20-50 MHz).

• A constant low impedance is required in a wide frequency range between the

fundamental clock frequency f0 of the ICs and several 10x harmonics of f0

• Resonances cause significantly higher impedances!

If one or more harmonics of f0 coincide with a plane’s resonance frequency, the IC’s

function may fail!

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Local dependency of Plane Impedance

f0

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When Integrated Circuits Switch ….

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• They need charge.

• Voltage has to be delivered (for reaching logic levels).

• A switching current will occur!

Relation between voltage & current? Ohm’s law

VH

VL

1.8V

GND

GND

VCC

R

V(t)

1

3

2R

R

Q

Q

Q

Q

Last

D

1

1

2

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Input Intern Output

+-

TTL Inverter

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Power Integrity in Reality Proper Power Supply of a Large FPGA

A Xilinx FPGA with 456 pins:

• Controls a video grabber card

• 64 bits can switch in parallel (worst case, with

a rise time of 750ps)

• Output pin drives into a load of 15pf

The maximum switching current can be

determined by:

Based on this maximum current, the

impedance limit to guarantee a ripple of

less than 125 mV (5% of 2.5 V) :

10

Ans

Vpf

t

VccCnI 2.3

75.0

5.215*64**

039.02.3

125

A

mV

I

UZ

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Power Integrity: Switching Current

• IC Switching current depends on:

- Number of active outputs

- Activity state

- Driver rise and fall times

- Clock frequencies

- Load conditions

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GND

VCC

R

V(t)

1

3

2R

R

Q

Q

Q

Q

Last

D

1

1

2

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Input Intern Output

+-

TTL Inverter

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Example: Ztarget of a Freescale Power-PC

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Area to be determined by PCB design

Picture © Freescale

Table © Freescale

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PCB Design Process Changing

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Traditional design flow to address power integrity issues

Design flow with power integrity analysis during layout

Concurrent PI Simulation

Conceptual Design

Schematic Placement Layout Prototyping Test

Measurements

Conceptual Design

Schematic Placement Layout Prototyping Test

Measurements

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Common Management of Power Integrity

Decoupling Capacitors (DeCaps): • Often used on “per default” basis (eg.; each IC)

• Values are based on past experience or design guidelines (eg.; 47nF, 100nF,…)

• Decision drivers are typically “rules of thumb” or “fear-decouplers”

• Connection between ICs and power-planes using discrete components and long traces

usually result in:

– Parasitic inductances

– Parallel connection in series to GND very high impedance and parallel capacitor circuit

– Outcome:

‒ Efficiency is reduced (can be narrowed down to zero)

‒ Low-pass filters with low resonance frequencies (LC-Resonance)

‒ Current loops EMC antennas

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Vdd

Ground

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Parasitic Inductance of DeCaps

1

4ln2

d

hhLVia

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The following inductance should be taken into account for PI consideration:

• Connecting traces (rule of thumb: ~1nH per mm)

• ESL of the DeCap (Package)

• Inductance of the PDS (eg,; Vcc/GND)

• 2 x Via-Inductance, which can be calculated by hand as follows:

IC

GND

Decap

Vcc

With:

h = PCB-thickness resp. Via-length

and:

d = Via-diameter

Source: Johnson & Graham’s : A Handbook of Black Magic

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Real Capacitors

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Z

log f

ESR

fres1 fres2

C=10nF, L= 25nH (including trace) f res 10 MHz

C=10nF, L= 2.5nH (SMD-Pads) f res 33 MHz

CLfres 2/1

Resonance frequency of a

capacitor

ESR L C

Capacitor

Equivalent Circuit

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Decoupling Capacitors and Resonances

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Decoupling Capacitors: Design Rules

Distance of decoupling capacitor to IC pin:

- Investigation of the influence of distance d between IC (source) and a

decoupling capacitor

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Source

DeCap

d

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Distance of DeCaps to IC Pin:

Distance d has significant influence on efficiency and resonance behavior, but not in the

high frequency range (where DeCaps are not effective at all).

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Pure Plane

d=2mm

d=5cm

d=10cm

d

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• Does more DeCaps result in improved resonance behavior?

- Distance = 2cm, up to 4 DeCaps at 10nF

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Source

DeCaps

Port2

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• Variation of the number of the DeCaps

– Identical DeCaps with identical connection

• Consequence: Number of DeCaps have limited impact in quality and

quantity (resonance in frequency point and magnitude) but there is no

general rule more does not always mean better

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Pure Plane

1 Decap

2 Decaps

3 Decaps

4 Decaps

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Application: Decoupling Analysis & What If

DeCap potentially not effective ?

Change Value within Lightning from 470p to 100N Quick What-If

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Application: Effectiveness of Decoupling

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• Impedance distribution at target frequencies show impact of decoupling capacitors

• Indicate quality of placement location, value and connection inductance

• Placement or connection can be changed on the fly in Lightning for what if capabilities

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Application: DDR2 Power Supply Symetrical modules, with different Power/GND connection

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D1

better

V1

D2

V2

11Ohm @650MHz

35Ohm @550MHz

D1

D2 V2

V1

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Application: Plate Capacitance of PDS

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Plate capacitance should be considered for

power and ground plane overlaps

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Application: Decoupling Capacitor

Connection Inductance Effect

• Automotive Motor Control Unit – Changed connection strategy reduces inductance from

16nH to 7.5nH

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Application: Changing PWR/GND Shapes

to Improve PDN Behavior

Motor Control Unit – Increased PDS shapes and better connection of decoupling capacitors allows reduction in the

number of decoupling capacitors by 40% saving PCB and manufacturing costs.

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Power Integrity in Reality: 2.5 V PDS Impedance for the Xilinx Spartan3

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Target impedance: 0.039

Ohm (=limit voltage ripple

to +/- 5 %)

Computation time to

get these figures?

Resonances at 33MhZ and 990 MHz a problem?

Is a modification of the decoupling scheme or a shift of these

resonances needed?

Minimum at

66 MHz – intended,

or at least known?

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There are more voltages to supply…

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12 Layer Design Task: Optimization of PDS

+1.2V

Capacitance between the layer + 1.2 V and GND 0.48 nF

decaps

plane area

Impact of Decaps

Capacitance between the layer

+ 2.5 V and GND 0.47 nF

Impact of Decaps

+2.5V

plane area

decaps

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Results: Different Power Trace Length

30

track

plane

28 mm

35 m

m

165 mm

Length 165 mm

track

plane

28 mm

35 m

m 25 mm

Length 25 mm

track

plane

28 mm

35 m

m 86 mm

Length 86 mm

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Summary

Power integrity analysis early in the design flow can save cost and

improve quality

• Early detection of issues in power distribution systems

• Verify effectiveness of decoupling capacitors

• Confirm quality of voltage and current distribution to avoid voltage

drops

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zuken - improve pcb quality and cost with concurrent power integrity analysis - pcb west 2011

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