مرتضي صاحب الزماني 1 vhdl language and syntax. application fields vhdl برای...

مرتضي صاحب الزماني 1

VHDL Language and Syntax

Application Fields

•VHDL برای مستندسازی و مدل سازی:

توصیف فرمال و دقیق یک سخت افزار –موجود

مثال: سیکل خواندن و نوشتن در تراشه های •حافظه صنعتی

فواید: •توصیف دقیق و بدون ابهام–امکان شبیه سازی سیستم در سطح بورد–


Application Fields

•VHDL برای مستندسازی و مدل سازی:

مدل کردن فرمال و دقیق طرحی که –قرار است ساخته شود

امکان توصیف و چک و دیباگ کردن عملکرد •طرح پیش از درگیر شدن به طراحی

رفع ابهامات صورت مسأله در مراحل اولیه•مثال: توصیف یک پروتکل ارتباطی•


Application Fields

•VHDL:برای سنتز طراح باید زیرمجموعه قابل سنتز را –

بداندباید بداند چگونه کد را بنویسد تا مدار –

خوبی تولید شود


Application Fields

•VHDL:برای درستی یابی طرح تولید بردارهای آزمون:–

هوشمندانه )دستی(: وقت گیر•تصادفی••ATPG

امکان استفاده از همه امکانات – برای تست VHDLبرنامه نویسی روالی

بنچ نویسیخواندن ونوشتن فایل•چک کردن خودکار نتایج•


Application Fieldsچک کردن خودکار نتایج:•


…L1:L_MODULE (X, Y, L);

LL: process(...)Begin for X in 0 to 63 for Y in 0 to 63 begin L_BEHAVE := (X**2+Y**2)**0.5; if (L != L_BEHAVE) then ERROR_SIG <= ‘1’; end if; end for; end for;end process LL;…

VHDL Syntax



General ----------------------------------

-- Example VHDL Code ------------------------------------

signal mySignal: bit; -- an example signalMYsignal <= '0', -- start with '0' '1' AFTER 10 ns, -- and toggle after '0' after 20 ns, -- every 10 ns '1' afTer 30 ns;

• Statements are terminated by ';'(may span multiple lines)

• List delimiter: ',' • Signal assignment: '<=' • User defined names:

• letters, numbers, underscores • start with a letter

• Comments: '--' until end of line


Naming Convention in Our Slides

architecture CONVN of NOTN is

end architecture CONVN ;

• VHDL keywords are writtenin lower case letters

• Important parts are written inbold letters

Output port modes have to match • Pointing out particular issues to watch out for


Convention

• Pointing out synthesis aspectsNot generally synthesizable

• Gives a tip in using thelanguage effectively

The direction of arrays shouldalways be defined the same way


VHDL Structural Elements

• Entity: Interface • Architecture: Implementation, behavior• Configuration: Structure, hierarchy • Process: Sequential Execution• Package: Components (Modular design), Utilities (data types,

constants, subprograms)• Library: Group of compiled units, object code


Use of VHDL Objects


Entity

entity HALFADDER is port( A, B: in bit; SUM, CARRY: out bit);end entity HALFADDER;

• Interface description • No behavior/implementation

definition

entity ADDER is port( A, B: in integer range 15 to 0; SUM: out integer range 15 to 0; CARRY: out bit );end ADDER;

• Linking via port signals • data types • signal width • signal direction

in bit_vector (3 downto 0); out bit_vector (3 downto 0);


Architectureentity HALFADDER is port( A, B: in bit; SUM, CARRY: out bit);end HALFADDER;

architecture RTL of HALFADDER isbegin SUM <= A xor B; CARRY <= A and B;end architecture RTL;

• Implementation of the design • Always connected with a specific

entity • one entity can have several

architectures • entity ports are available as

signals within the architecture • Contains concurrent statements


Architecture Structure

architecture EXAMPLE of STRUCTURE is subtype DIGIT is integer range 0 to 9; constant BASE: integer := 10; signal DIGIT_A, DIGIT_B: DIGIT; signal CARRY: DIGIT;

begin DIGIT_A <= 3; SUM <= DIGIT_A + DIGIT_B; DIGIT_B <= 7; CARRY <= 0 when SUM < BASE else 1;end EXAMPLE ;

• Declarative part: • data types • constants • intermediate signals• component declarations • ...

• Statement part (after 'begin'): • signal assignments • processes • component instantiations • concurrent statements:

order not important Simulator recalculates

sum any time an operand changes• Port is a kind of signal.

تکليف



Entity Port Modes• in:

• signal values are read-only

• out: • signal values are write-

only • multiple drivers

• buffer: • similar to out • signal values may be read,

as well • only 1 driver

• inout: • bidirectional port

Output port modes have to match.


Structural Model

را صريحاٌ توصيف نمي functionality توصيف ساختاري, •كند بلكه فقط ليستي از اجزا و نحوة اتصال آنهاست.


Component Declaration

entity FULLADDER is port (A,B, CARRY_IN: in bit; SUM, CARRY: out bit);end FULLADDER;

architecture STRUCT of FULLADDER is

component HALFADDER port (A, B : in bit; SUM, CARRY : out bit); end component;

component ORGATE port (A, B : in bit; RES : out bit); end component;begin signal W_SUM, W_CARRY1, W_CARRY2 : bit;

. . .

• In declarative part of architecture

• Can use any name for the components

• but better to use the same as entity’s name

entity HALFADDER is port( A, B: in bit; SUM, CARRY: out bit);end entity HALFADDER;

entity ORGATE is port( A, B: in bit; RES: out bit);end entity ORGATE;


Component Instantiationarchitecture STRUCT of FULLADDER is component HALFADDER port (A, B : in bit; SUM, CARRY : out bit); end component; component ORGATE port (A, B : in bit; RES : out bit); end component; signal W_SUM, W_CARRY1, W_CARRY2: bit;begin MODULE1: HALFADDER port map( A, B, W_SUM, W_CARRY1 ); MODULE2: HALFADDER port map ( W_SUM, CARRY_IN, SUM, W_CARRY2 ); MODULE3: ORGATE port map ( W_CARRY2, W_CARRY1, CARRY );end STRUCT;

• May need many of each • Instantiation in statement

part of architecture (after 'begin')

• Wires signals together: • default: positional

association


Named Signal Associationentity FULLADDER is port (A,B, CARRY_IN: in bit; SUM, CARRY: out bit);end FULLADDER;


component HALFADDER port (A, B : in bit; SUM, CARRY : out bit); end component;. . . signal W_SUM, W_CARRY1, W_CARRY2 : bit;begin MODULE1: HALFADDER port map ( A => A, SUM => W_SUM, B => B, CARRY => W_CARRY1 ); . . .end STRUCT;

• Named association: • left side: "formals"

(port names from component declaration)

• right side: "actuals"(architecture signals)

• Independent of order in component declaration


Configurationentity HALFADDER is port(A, B: in bit; SUM, CARRY: out bit);end HALFADDER;

. . .

component HALFADDER port(A, B: in bit; SUM, CARRY: out bit); end HALFADDER;

signal W_SUM, W_CARRY1, W_CARRY2: bit;

· · ·

MODULE1 : HALFADDER port map(A, B, W_SUM, W_CARRY1);

Entities may be instantiated directly without preceding component declaration (Not recommended)


Configurationentity FULLADDER is. . .end FULLADDER;


for MODULE1: HALFADDER use entity work.HALFADDER (RTL);for MODULE2: HALFADDER use entity work.HALFADDER (RTL); begin

….end STRUCT;

• Selects entity/architecture pairs for instantiated components • Generates the hierarchy • Creates a simulatable object • Default binding rules:

• selects entity with same name as component • last compiled architecture is used


Configuration Example

entity HALFADDER is

port(A,B: in bit; S, CY: out bit);end A;

architecture RTL of HALFADDER is· · ·

end RTL;

entity FULLADDER is port(A, B, CARRY_IN: in bit; SUM, CARRY: out bit);end FULLADDER;architecture STRUCT of FULLADDER is component HA port(A, B: in bit; SUM, CARRY: out bit); . . . signal W_SUM, W_CARRY1, W_CARRY2: bit;begin MODULE1: HA port map (A, B, W_SUM, W_CARRY1);

MODULE2: HA port map(W_SUM, CARRY_IN, SUM, W_CARRY2); . . .end STRUCT;architecture GATE of HALFADDER

is· · ·

end GATE;


Simple Configuration Specificationentity FULLADDER is port(A, B, CARRY_IN: in bit; SUM, CARRY: out bit);end FULLADDER;architecture STRUCT of FULLADDER is component HA port(A, B: in bit; SUM, CARRY: out bit);end component;

for MODULE1:HA use entity work.HALFADDER (RTL);

for MODULE2:HA use entity work.HALFADDER (GATE); signal W_SUM, W_CARRY1, W_CARRY2: bit;

begin MODULE1:HA port map (…, …);

MODULE2:HA port map(…, …);

end STRUCT;

entity HALFADDER is

port(A,B: in bit; S, CY: out bit);end A;

architecture RTL of HALFADDER is· · ·

end RTL;

architecture GATE of HALFADDER is· · ·

end GATE;


Configuration Example

configuration CFG_FULLADDER of FULLADDER is for STRUCT for MODULE2:HA use entity work.HALFADDER(GATE); end for;

for others:HA use entity work.HALFADDER(RTL); end for; end for;end CFG_FULLADDER;

• Entity/architecture pairs may be selected by use of • instance names • 'all': all instances of the specified component • 'others': all instances not explicitly mentioned

• Possible to reference an existing configuration of a submodule

Configuration CONFNAME of ENTITYNAME is

for ARCHNAME

for INSTANCENAME use entity LIBNAME.ENTNAME(ARNAME);

for all:FA use configuration work.CFG_FULLADDER;


CONFIGURATION average_gate_delay OF d_register IS FOR latch_based FOR dr FOR di : dl USE ENTITY WORK.d_latch(sr_based); FOR sr_based FOR c1 : sr USE ENTITY WORK.sr_latch(gate_level); FOR gate_level FOR g2, g4 : n2 USE ENTITY WORK.nand2_t(average_delay) END FOR; FOR g1, g3 : n2 USE ENTITY WORK.nand2_t(less_delay) END FOR; END FOR; END FOR; FOR c2 : n1 USE ENTITY WORK.inv_t(average_delay) END FOR; END FOR; END FOR; END FOR; END FOR;END average_gate_delay;


Configuration را configuration بعضي از ابزارهاي سنتز جمالت •

در نظر نمي گيرند و ممکن است قوانين پيش ها:declarationفرض را اعمال کنند. بنابراين در

باشدentityها عين نام component بايد نام • باشدentityها عين پورت port نام، مود و نوع •


Processentity AND_OR_XOR is port (A,B : in bit; Z_OR, Z_AND, Z_XOR : out bit);end AND_OR_XOR; architecture RTL of AND_OR_XOR isbegin

A_O_X: process (A, B) begin Z_OR <= A or B; Z_AND <= A and B; Z_XOR <= A xor B; end process A_O_X ; end RTL;

• Contains sequentially executed statements • Only within an architecture• Several processes run concurrently • Execution is suspended either via

• sensitivity list (contains trigger signals), or

• wait-statements • Signal values don’t change until

suspension

process_exec.aviprocess_value_change.avi


Process

بزاcرهاي سنتز معموالً ليست حساسيت را ا•ناديده مي گيرند

براي مدارهاي ترکيبي همة وروديها بايد •در ليست قرار گيرند تا نتيجة شبيه سازي

قبل از سنتز با سخت افزار سنتز شده مطابقت داشته باشد.

و clock براي مدارهاي ترتيبي، فقط •( در reset, presetوروديهاي آسنکرون )

ليست قرار گيرند.


VHDL Communication Model

• Processes are concurrent statements • Several processes • run in parallel • linked by signals in the sensitivity

list • Link to processes of other

entity/architecture pairs via entity interface

multi_process_exec.avi

multi_process_exec2.rar


Signals

• Every signal has a specific data type • possible values

• Predefined data types • bit, bit_vector, integer, real, ...


Packages

• Collection of definitions, datatypes, subprograms

• Reference made by the design team • Any changes are known to the team

immediately • same data types ("downto vs. to") • extended functions for all • clearing errors for all


Packages

پکيجها در دو بخش نوشته مي شوند:••Package Header شامل اعالن :subprogram

prototype ،هاdata type... ،ها•Package Body شامل پياده سازي :subprogramها

بايد headerکامپايل را آسان مي کند: فقط • جاري با تعاريف VHDLخوانده شود تا تطبيق کد

اعالنهاي قبلي مشخص شود.


:

Library

• (can be mapped to another user-defined library)


Design Structure: Example

قرار داده شده چون ماجولهاي مختلف Pفرمت داده ها در پکيج •طرح از آن استفاده مي کنند.

CTRLدو معماري مختلف از •


Sequence of Compilation

• Primary units are analyzed before secondary units • entity before architecture • package before package body

• All units that are referred to have to be analyzed first • entity after package • configuration after entity/architecture


Testbench

• VHDL code for top level • No interface signals • Instantiation of design • Statements for stimuli generation • Simple testbenches: response analysis by waveform inspection • Sophisticated testbenches may need >50% of complete project

resources


Simple Testbench Exampleentity ADDER IS port (A,B : in bit; CARRY,SUM : out bit);end ADDER;architecture RTL of ADDER isbegin ADD: process (A,B) begin SUM <= A xor B; CARRY <= A and B; end process ADD;end RTL;

entity TB_ADDER ISend TB_ADDER;architecture TEST of TB_ADDER is component ADDER port (A, B: in bit; CARRY, SUM: out bit); end component; signal A_I, B_I, CARRY_I, SUM_I : bit;begin DUT: ADDER port map (A_I, B_I, CARRY_I, SUM_I); STIMULUS: process begin A_I <= ´1´; B_I <= ´0´; wait for 10 ns; A_I <= ´1´; B_I <= ´1´; wait for 10 ns; -- and so on ... end process STIMULUS;end TEST;configuration CFG_TB_ADDER of TB_ADDER isfor TEST for DUT:ADDER use entity work.ADDER(RTL);end for;end CFG_TB_ADDER;

Summary


• Object classes in VHDL• VHDL constructs

• Entity & Architecture• Configuration

• Sequential vs. concurrent• Structural specification

• Netlist• Instantiation and connections

• Sequential construct:• Process

• Library and Package• Testbench

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