© 2009, renesas technology america, inc., all rights reserved 1 course introduction purpose: this...

1© 2009, Renesas Technology America, Inc., All Rights Reserved

Course Introduction

Purpose: This course provides an overview of the SH-2 32-bit RISC CPU core

used in the popular SH-2 series of microcontrollers.

Objectives: Gain a basic knowledge of the SH-2 CPU Understand key features of this 32-bit RISC architecture Learn about the CPU’s addressing modes Explore the SH-2 instruction set Get the details about subroutine calls

Content: 18 pages 3 questions

Learning Time: 15 minutes


Overview of SH-2 CPU

General A member of the SuperH® family Powers many popular 32-bit microcontrollers Operates at clock speeds up to 80MHz

Software RISC-type instruction set and

addressing modes based on “C” 16-bit fixed-length basic instructions

for excellent code density Upwardly compatible with SH-1 CPU

at object-code level Includes delayed branch instructions

Hardware Load-store design with 5-stage pipeline Executes up to 1 instruction/cycle Includes 16 general-purpose 32-bit

registers Built-in multiplier-accumulate unit (MAC)

for DSP-type operations (32x32-bit multiply to 64-bit result in 2 to 4 states)

Provides a 4GB address space

Support Supported by a comprehensive set of Renesas software/ hardware tools, plus many

products and services from large vendor community


SH-2 CPU Model

R0

R1

R2

R3

R4

R5

R6

R7

R8

R9

R10

R11

R12

R13

R14

R15

031- - - - - - - - - - - - - - - - - - - -M Q I[3:0] - - S T

031

Status Register (SR)

GBR031

Global Base Register (GBR)

VBR031

Vector Base Register (VBR)

MACH031

Multiply and accumulate registers

MACL

PR

Procedure Register (PR)

PC

Program Counter (PC)

031

031

© 2009, Renesas Technology America, Inc., All Rights Reserved

Load-Store Architecture

Arithmetic instructions have operands in the register A generous register set is required and provided Operands must be loaded from memory Execution time is very fast and

predictable. Local arithmetic execution time is

independent of data path

Standard data length is 32 bits (longword)

Any 8- or 16-bit data is sign-extended for arithmetic operations, or zero-extended for logic operations

OperatedUpon

Memory

Register


Immediate Data

Byte immediate data is stored in instruction code

Word or longword immediate data is located in memory tables (literal pools) accessed via a PC-relative addressing mode MOV instruction

Classification SH-2 CPU Example of another CPU

PROPERTIESOn passing, 'Finish' button: Goes to Next SlideOn failing, 'Finish' button: Goes to SlideAllow user to leave quiz: At any timeUser may view slides after quiz: After passing quizUser may attempt quiz: Unlimited times


Addressing modes define how/where to find operandsAddressing modes define how/where to find operands

Single-Address Machine

Because the SH-2 is a SINGLE-ADDRESS machine . . . At least one operand is always stored in a register The other operand is defined by the addressing mode The addressing mode defines the Effective Address (EffA) calculation.

Exception: MAC @Rm+,@Rn+

Example: Store contents of register R1 in memory; address of memory is in R2

• MOV.L R1,@R2

- Source operand is general register R1- Destination is memory; address is in R2 (Addressing mode: Register indirect)


Register direct: Rn

Register indirect: @Rn

Register indirect with post-increment: @Rn+

Register indirect with pre-decrement: @-Rn

Register indirect with displacement: @(dd:4,Rn)

Indexed register indirect: @(R0,Rn)

GBR indirect with displacement: @(dd:8,GBR)

Indexed GBR indirect: @(R0,GBR)

PC relative with displacement: @(disp:8,PC)

PC relative: disp:8

disp:12

Rn

Immediate: #imm:8

Addressing Modes

Used by standard arithmetic & logic operations

Used to push values onto the stack

Used for array handling & popping values from stack

Great for accessing C/C++ structure contents

Used to access 16-bit and 32-bit constant data from

memory tables/literal poolsFacilitates far branching to anywhere in address space

8-bit data can be held in 16-bit instructions


Features of Instruction Set

Types of Operations:

Data transfer

Arithmetic

Logic

Shift / Rotate

System control

Program flow control

MOV.B @(3,R15),R0EXTU.B R0,R0MOV.L L278+14,R3ADD R0,R3MOV.B @(3,R15),R0EXTU.B R0,R0MOV.L L278+22,R1MOV.B @(R0,R1),R2MOV.B R2,@R3MOV.B @(3,R15),R0ADD #1,R0MOV.B R0,@(3,R15)MOV.B @(3,R15),R0EXTU.B R0,R0MOV #6,R3CMP/GT R3,R0BF L268


Data Transfer Instruction: Move

MOV: General move to / from registers; byte, word and longword operand No modification of status register (in contrast to H8 series)

Immediate 8-bit: MOV.B #value:8,Rn

Immediate 16-bit: MOV.W @(displ:8,PC),Rn address: displ*2 + PC

Immediate 32-bit: MOV.L @(displ:8,PC),Rn address: displ*4 + PC

InLiteral Pools

R0R1R2R3R4R5R6R7R8R9R10R11R12R13R14R15

31 0

(SP)

Memoryor I/O

In Instruction


Arithmetic/Logic Instructions

ADD, SUB

Compare: CMP

Divide support: DIV

Multiply Rn * Rm MUL

Multiply @Rn * @Rm MAC

Negate: NEG

AND, OR, TST, XOR Addressing modes for AND, OR, TST, XOR:

– AND Rm,Rn, AND #dd:8,Rn, AND #dd:8,@(R0,GBR)

TAS: TAS.B @Rn ;"test and set" operates on byte and T-bit

NOT: NOT Rm,Rn ; ~Rm Rn


Shift/Rotate Instructions

Shift / rotate one bit

Shift / rotate one bit with T-bit

Shift n bit(s), n=2, 8, 16 n=2: x4 or /4 n=8: shift by one byte (or x256, /256) n=16: shift by one word (or x65536, /65536)

>>

<<Note: These instructions are only suitable for unsigned arithmetic!


System Control Instructions

Set/clear T-bit: SETT, CLRT

MAC clear: CLRMAC

Load/Store system registers (SR, GBR, VBR): LDS, STS Copy contents of system register to/from

any general-purpose register or memory, using @-Rn/@Rn+ addressing (stack compatible)

Load/Store control registers (MAC, PR): LDC, STC Copy contents of control registers to/from

any general-purpose register or memory, using @-Rn/@Rn+ addressing (stack compatible)

Sleep (either standby or sleep)

Return from exception: RTE

TRAPA


Program Flow Instructions

Conditional & unconditional delayed branches

Conditional branch coding and handling sequence: T-bit handling with COMPARE instruction Result of condition is tested in T-bit Then branch conditional

Unconditional branch

A subroutine call instruction causes the hardware to: Copy PC contents in PR Put new value into PC Go to next instruction

A return from subroutine instruction causes the hardware to: Copy PR contents in PC Go to next instruction

Exception handling


Boosts program execution speed and reduces code size!

Subroutine Calls

Instructions: BSR, JSR, RTS

Hardware support for single-level subroutine calls

Multiple-level calls require support: "PUSH" and "POP" of previous PC under software control

Sequence: Enter subroutine (BSR/JSR): Hardware: Copy PC to PR Load new value to PC (Software: Push PR to stack)

Execute next instruction ...code... Exit subroutine:

(Software: Pop PR from stack) Hardware: RTS instruction Copy PR to PC Continue

PR

Procedure Register

Program Counter = One-level-deep buffer!

PC


Course Summary

Overview of SH-2 RISC CPU features, architecture

Internal CPU registers

Addressing modes

Instruction set

Subroutine calls

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